Fix two correctness bugs: compressor pos bias on KV + SwiGLU clamp ordering

1. Compressor positional bias was being added to BOTH gate (softmax logit)
   AND KV content. Per paper eq. 9-12, position bias is only for the
   softmax logits (Z+B), NOT the KV content (C). Adding pb to kv_val
   corrupts every compressed KV entry with learned positional-bias content.
   Fixed in both CSA and HCA paths in compressor_reduce.cu.

2. SwiGLU clamp ordering: code was clamping silu(gate) instead of clamping
   raw gate before SiLU. Per paper §4.2.3: gate = clamp(gate, max=limit),
   then silu(clamp(gate)) * clamp(up). Fixed in moe.py (both unfused
   paths) and fused_swiglu.py (CuTeDSL kernel). shared_expert.py was
   already correct.

.gitignore

@@ -1,3 +1,4 @@
 __pycache__/
 *.pyc
 *.egg-info/
+nvfp4-megamoe-kernel-*.zip

ARCHITECTURE_AND_MEMORY_AUDIT.md

@@ -1,434 +0,0 @@
-# ARCHITECTURE & MEMORY AUDIT — 1M-context viability
-
-**Method.** Verified against `single_shot_inference.py` v16 and the DSv4
-paper §2.3.1–§2.3.4 (CSA/HCA) and §3.5.1 (heterogeneous KV cache). Every
-finding has a line number. Per doctrine.
-
-**Framing.** The Paris demo runs ≤ 50 tokens. The model is built for 1M.
-That's a **20,000×** gap. Several things in the current single_shot are
-fine at 50 tokens, will OOM hard at 4–10K tokens, and don't even resemble
-the paper's KV design at 1M. Below: drift first, then memory, in order of
-how badly each one blocks the 1M-context goal.
-
----
-
-# PART 1 — ARCHITECTURE DRIFT FROM PAPER
-
-## D1 — `comp_idx_buf` shape is wrong (CRITICAL — silent corruption or crash)
-
-`single_shot_inference.py:419`:
-
-```python
-self.comp_idx_buf = torch.zeros(max_comp, head_dim, dtype=torch.bfloat16, device=device)
-                                          ^^^^^^^^
-                                          512 — WRONG
-```
-
-But indexer keys are `n_ih × ihd` wide. From `:1030`:
-
-```python
-n_ih = cfg.get("index_n_heads", 64)
-ihd  = cfg.get("index_head_dim", 128)
-```
-
-So indexer keys have width `64 × 128 = 8192`, not 512. **The indexer KV
-buffer is 16× too narrow.** What happens in practice depends on whether
-the assignment broadcasts, raises, or silently truncates — and from the
-fact that Paris-back works, the indexer probably isn't being used at all
-yet (CSA layers may be producing 0 compressed blocks at 50 tokens — see
-D2). At any context where CSA actually compresses, this either crashes
-or stores garbage in the top-k selection input.
-
-**Fix.** Read the actual indexer key width from the indexer's compressor
-output (`indexer.compressor.kv_dim = 2 * ihd = 256` for the indexer-side
-CSA, since the indexer's compressor takes `(4, ihd, H)`). Then check what
-the indexer's compressor actually produces — print its output shape on
-first call instead of guessing — and size `comp_idx_buf` to match.
-
-Verification step: instrument `Compressor.forward` to print
-`compressed.shape` on first call from both the **main** compressor (kv_dim
-= 512 or 1024) and the **indexer's** compressor (kv_dim = 256). Code to
-the observed values. Do not infer them from variable names.
-
-## D2 — The Compressor is built twice per CSA layer, with different config
-
-`:394` (inside `Indexer.load`):
-```python
-self.compressor = Compressor(4, self.ihd, 7168, dev)
-```
-
-`:1034` (in `main()`):
-```python
-if ratio > 0: compressors[li] = Compressor(ratio, hd, H, dev)
-```
-
-For a CSA layer:
-- The **layer's** compressor has `(ratio=4, hd=512, H=7168)`, output dim
-  `kv_dim = 2*hd = 1024`.
-- The **indexer's** compressor has `(ratio=4, ihd=128, H=7168)`, output
-  dim `kv_dim = 2*ihd = 256`.
-
-Both are constructed, both load weights independently, both have their own
-NVFP4 GEMM Nvfp4Linear instances. This matches the paper (§2.3.1: the
-indexer has its own compressed key path that's narrower than the main
-compressed KV path) — but **it is being done as two completely
-independent code paths**, with the indexer's compressor's existence
-implicit and easy to miss. That's why D1 was missed.
-
-It also means the main compressor's `forward` runs twice per layer at
-prefill: once for the main KV path, once for the indexer's keys. The
-hidden states being projected are *identical*; the GEMM weights are
-different. Two separate launches.
-
-**Architecturally correct, but the code shape hides it.** Two consequences:
-
-1. The "compressor" abstraction has a different meaning depending on
-   which compressor instance you're looking at. Rename for clarity:
-   `Compressor` (main) and `IndexerKeyCompressor` (smaller, for indexer).
-2. The Indexer should expose its compressed key width as a property
-   (`indexer.compressor.kv_dim // 2`) so D1 can compute the buffer width
-   from data instead of assuming `head_dim`.
-
-## D3 — KV gather still uses `torch.cat`, undoing P3's pre-allocation
-
-`:569–571`:
-
-```python
-if ratio == 4 and topk_idx is not None:
-    tk = topk_idx[0].clamp(0, kv_cache.n_comp - 1)
-    all_kv = torch.cat([kv_cache.comp_kv[tk], swa_kv], dim=0)
-elif ratio > 4: all_kv = torch.cat([kv_cache.comp_kv, swa_kv], dim=0)
-```
-
-P3 preallocated `comp_kv_buf`, but the gather **immediately allocates a
-fresh `(top_k + ws, hd) = (1024 + 128, 512)` BF16 tensor per layer call**
-just to pass to FMHA. For 61 layers × per-token decode:
-
-- 61 × (1152 × 512 × 2 bytes) ≈ **72 MB allocated and freed per token**.
-
-That's small in absolute terms, but it's allocator churn on the hot path,
-and the entire point of P3 was to remove this pattern. The `comp_kv[tk]`
-gather already allocates (it's an advanced-indexing copy); the `cat` then
-allocates again to merge with SWA. Two allocs per layer that don't need
-to exist.
-
-**Fix.** Preallocate one more buffer at cache init:
-
-```python
-self.all_kv_buf = torch.zeros(top_k + window_size, head_dim, ...)
-```
-
-Write the gathered top-k into `all_kv_buf[:top_k]`, the SWA into
-`all_kv_buf[top_k:top_k+swa_len]`, pass `all_kv_buf[:top_k+swa_len]` to
-FMHA. The gather becomes `torch.index_select(comp_kv_buf, 0, tk,
-out=all_kv_buf[:top_k])` — zero allocs.
-
-## D4 — The HCA path concatenates the ENTIRE compressed history, every layer, every token
-
-Same line, the `elif` branch:
-
-```python
-elif ratio > 4: all_kv = torch.cat([kv_cache.comp_kv, swa_kv], dim=0)
-```
-
-HCA layers don't run the indexer. They attend over the **full compressed
-history**. At 1M context with HCA ratio=128, that's `1M / 128 = 7813`
-compressed entries. Per-token-per-layer FMHA input grows linearly with
-prefill length. That's correct math (paper §2.3.2: HCA is dense over
-compressed entries), but the *implementation* is allocating a new
-contiguous tensor for it every single layer call.
-
-At 1M context, that's `(7813 + 128) × 512 × 2 bytes ≈ 7.7 MB` per HCA
-layer call. Across ~30 HCA layers per token ≈ **230 MB of alloc-and-free
-per token, on the decode hot path.**
-
-**Fix.** Same as D3: preallocate `all_kv_buf` sized for the worst case
-(HCA full history + SWA). Use `out=` parameters on the gather. Or skip
-the concat entirely — the FMHA kernel can take two K/V tensors and the
-mask can encode the boundary. Today it can't, but it should; this is a
-real kernel-side ask (see "M5" below).
-
-## D5 — Indexer top-k attends *only* compressed entries; SWA is appended separately. Confirm against paper
-
-Paper §2.3.1 figure: CSA's FMHA input is
-`Concatenate(selected_compressed_KV, sliding_window_KV)`. Yes, that's
-what the code does at `:571`. **Architecturally correct.**
-
-One subtle thing worth checking: the paper says the sliding window provides
-*local* fine-grained context the compressor can't (since compressed entries
-each represent m tokens). The current SWA window is **128** (from config).
-At 1M context that's still 128 local tokens visible per query — correct.
-But the window slide in `KVCache.append_swa` evicts when full
-(`self.swa_head = (self.swa_head + T) % self.ws`), which is correct.
-✅ no drift.
-
-## D6 — Attention sink is wired, but per-CSA-layer correctness needs checking
-
-`_run_production_fmha:489`:
-
-```python
-sinks = w.get(f"{pfx}.sinks")
-if sinks is not None: sink_bias = sinks.to(device=dev).float().reshape(n_h)
-attn_out = dsv4_attention(q=q, k=k, v=v, scale=scale, n_comp=0, sink_bias=sink_bias)
-```
-
-`n_comp=0` is passed regardless. Paper §2.3.3 ("Attention Sink"): the sink
-is a per-head additive logit to the softmax denominator. The kernel
-signature in v15 said `n_comp` is "reserved for future kernel integration"
-for the **D5c sink merge** (different softmax over compressed vs SWA).
-v16 still passes `n_comp=0`, which means we're using global sink, not
-per-segment sink merge.
-
-The paper isn't explicit about whether sink should be per-segment, but if
-the production FMHA was designed for D5c merge and it's being bypassed,
-that's an unfinished integration, not necessarily a bug.
-
-**Action:** confirm against the kernel's actual handling. Print the
-sink_bias usage in `dsv4_attention` for one layer. If sink merge is
-needed for CSA correctness at long context, that's a real wiring gap.
-
-## D7 — mHC residual growth (|X|→500–700 at L60) was flagged but not understood
-
-Your perf audit notes (line 88): "Residual |X| grows to 500–700 at L60
-— mHC bounds it but residual is high."
-
-Paper §2.2 designed mHC specifically to **bound** the residual via the
-doubly-stochastic B matrix (spectral norm ≤ 1). The growth from |X|=1 at
-L0 to |X|=700 at L60 suggests B isn't actually norm-bounded at runtime,
-or A·C are amplifying.
-
-This is the **same** issue I flagged in the v14 docs and it's still open.
-Not a perf bug, but it's an architecture-fidelity bug, and it's the
-**single most likely cause of decode degradation past step 10** (the
-"...the" repetition loop noted in your audit). Compounded across decode
-steps, a slightly-not-bounded residual becomes a numerically saturated
-residual, which makes the final logits less informative.
-
-**Action.** Print Sinkhorn-Knopp B's row/col sums per layer for one
-forward pass. They should be `1.0 ± 1e-6` if Sinkhorn converged. If
-they're e.g. `1.02–1.05`, t_max=20 isn't converging at this scale; bump
-it or check the dynamic-parameter generation. The single_shot does
-`sinkhorn_iters=20` (`:937`) which matches the paper, so the issue is
-likely upstream: either A or C is producing values outside [0, 1] or
-[0, 2], or the dynamic parameter generation has FP32 noise that breaks
-doubly-stochastic.
-
----
-
-# PART 2 — MEMORY AT 1M CONTEXT
-
-This is the part that should be terrifying. The single_shot was sized for
-50 tokens; the model targets 1M. Below is what each KV-cache structure
-costs at the four interesting scales, with all numbers worked out, not
-estimated.
-
-## Per-layer KV cache sizes — read off the code
-
-Layer setup:
-- **CSA layer** (compressor ratio=4): main compressed at `hd=512` BF16,
-  indexer keys at `n_ih * ihd = 64 * 128 = 8192` BF16, SWA at `ws=128 × hd`
-- **HCA layer** (compressor ratio=128): main compressed at `hd=512` BF16,
-  no indexer, SWA at `ws=128 × hd`
-- **SWA-only layer** (first 2 layers of Flash, or HCA per-layer-2 of Pro):
-  SWA only
-
-Layer counts per V4-Pro: 61 total, alternating CSA/HCA after layer 1. So
-roughly **30 CSA + 30 HCA + 1 SWA-only** (paper §4.2.1).
-
-### Per-layer KV growth (per token of context):
-
-| Component | Per token | Bytes / token | × 1M tokens |
-|---|---|---|---|
-| **CSA main compressed** (1 entry / 4 tokens, hd=512 BF16) | 0.25 × 1024 B | 256 B | **256 MB** |
-| **CSA indexer keys** (1 entry / 4 tokens, 8192 BF16) | 0.25 × 16384 B | 4096 B | **4.1 GB** |
-| **HCA compressed** (1 entry / 128 tokens, hd=512 BF16) | 0.0078 × 1024 B | 8 B | **8 MB** |
-| **SWA** (per layer, fixed 128 × hd × 2) | const | — | 128 KB |
-
-### Total KV cache @ 1M context, all layers, BF16:
-
-| Layer type | Count | Per-layer @ 1M | Total |
-|---|---|---|---|
-| CSA: main + indexer | 30 | 256 MB + 4.1 GB | **131 GB** |
-| HCA: main | 30 | 8 MB | 240 MB |
-| SWA | 61 | 128 KB | 8 MB |
-| **GRAND TOTAL @ 1M, BF16** | | | **~131 GB** |
-
-**The KV cache alone is 131 GB.** That's before model weights (which are
-already EP-sharded across 8 GPUs). On 8 × B200 with 192 GB each = 1.5 TB
-total, sharding KV across the 8 GPUs gives ~16 GB per GPU — fits, but
-it's **15% of HBM dedicated to one request's KV.** And the dominant cost
-is the **indexer keys** at 4.1 GB per layer.
-
-**Critical observation: the indexer keys are 16× larger than the main
-compressed KV per token, and they alone are 86% of total KV.** This is
-because `n_ih * ihd = 8192` is much wider than `hd = 512` for the main KV.
-The paper does specify this — the indexer is a wide multi-query mechanism
-— but if storage is the constraint, the indexer key path is where to
-attack.
-
-## M1 — `comp_idx_buf` allocation as written: `(65536, 512)` per layer
-
-`:419`:
-```python
-self.comp_idx_buf = torch.zeros(max_comp, head_dim, dtype=torch.bfloat16, ...)
-```
-
-If this *were* the correct width `(max_comp=65536, 8192)`, that's
-`65536 × 8192 × 2 = 1 GB per layer × 30 CSA layers = 30 GB pre-allocated
-at startup`, sized for **only 262K tokens of context**, not 1M.
-
-The current shape `(65536, 512)` allocates 64 MB per layer × 30 = 1.9 GB
-— too small by 16× as noted in D1, so either crashes at first compressed
-write or silently truncates. Both bad. After fixing D1, you're staring
-down 30 GB of pre-allocated KV cache that supports only a quarter of the
-target context. And it's 30 GB × 8 GPUs = 240 GB if everything is
-replicated, or 30 GB total if cache is sharded.
-
-**This is the load-bearing memory bug for 1M context.** Two viable fixes:
-
-1. **Quantize the indexer keys to FP4** (paper §5.2.1: "QK activations
-   are cached, loaded, and multiplied entirely in FP4"). The indexer keys
-   are *designed* to be FP4. That's 16× smaller: 4.1 GB/layer → 256 MB at
-   1M. Total cache becomes ~10 GB instead of 131 GB. **This is the
-   correct fix per paper.**
-2. **Page the indexer KV.** Only the top-k indices' worth (≤ 1024) need to
-   be in attention. A paged cache (per the paper's §3.5.1 "heterogeneous
-   KV cache" with on-disk overflow) only keeps recent + selected pages in
-   HBM.
-
-(1) is required regardless of (2). The current BF16 indexer cache is the
-single biggest blocker between Paris-demo-works and 1M-context-works.
-
-## M2 — `max_comp = 65536` hardcoded
-
-`:411`:
-```python
-def __init__(self, head_dim, window_size=128, max_comp=65536, device='cuda:0'):
-```
-
-For CSA (ratio=4), 65536 compressed entries = `262144` tokens of context.
-That's the ceiling. At 262K tokens you get `IndexError` on
-`comp_kv_buf[self.n_comp:end] = ckv`. There is no graceful behavior, no
-on-disk overflow, no error message — it just dies.
-
-For 1M context, `max_comp` needs to be `1M / 4 = 262144` for CSA layers
-and `1M / 128 = 7813` for HCA layers. Currently both layer types share
-the same 65536 default.
-
-**Fix.** Size the buffer per-layer using compress ratio:
-```python
-max_comp_csa = ceil(target_context / 4)   # 262144 for 1M
-max_comp_hca = ceil(target_context / 128) #   7813 for 1M
-```
-And, critically, make `target_context` a CLI flag with a sensible default
-(say 8K) so the script can run small while staying honest about the
-ceiling. Hardcoded 65536 with no docstring on what it means is a footgun.
-
-## M3 — Allocator churn from gather (D3, D4) compounds at 1M
-
-Repeated for emphasis with numbers: the per-token `torch.cat` in the KV
-gather allocates and frees memory proportional to context length. At 1M
-context with HCA at all layers, that's **~230 MB of alloc/free per
-decoded token**. PyTorch caching allocator handles this but it's still
-fragmentation pressure across thousands of decoded tokens. After hours
-of decoding, the allocator's cached blocks bloat.
-
-Already covered in D3/D4. Restating because at 1M scale it's no longer
-"small overhead" — it's GB/min of churn.
-
-## M4 — `get_swa` does `.clone()` every call
-
-`:457–460`:
-```python
-def get_swa(self):
-    if self.swa_len == 0: return torch.zeros(0, self.hd, ...), torch.zeros(0, ...)
-    if self.swa_len < self.ws: return self.swa[:self.swa_len].clone(), self.swa_pos[:self.swa_len].clone()
-    idx = torch.arange(self.swa_head, self.swa_head + self.ws) % self.ws
-    return self.swa[idx].clone(), self.swa_pos[idx].clone()
-```
-
-Three clones in the second return path (and the third one allocates an
-arange too). At `ws=128 hd=512`, the SWA tensor is 128 KB — small — but
-**this runs every layer every token**. 61 × decoded tokens × 128 KB ≈ a
-few MB/token in allocator pressure. Same fix pattern as D3: return views
-into the ring buffer, let the FMHA gather kernel consume them with strides.
-
-## M5 — KV gather memory could be eliminated entirely with a smarter kernel
-
-D3 and D4 both pre-allocate a fused `all_kv` buffer because the FMHA
-takes one K/V tensor. The deeper fix is to have the FMHA take **two K/V
-inputs** (compressed + SWA) and handle them with masking inside. Then no
-fused buffer ever has to exist — the kernel reads compressed entries
-directly from `comp_kv_buf` (with a gather indices vector for the top-k
-selection) and SWA entries directly from `swa_buf`.
-
-This is the **right** long-term design (and matches how the paper §3.5.1
-envisions the heterogeneous cache). It's a kernel ask, not a script fix,
-but it's worth flagging now: the gather → cat → FMHA pattern is *the*
-memory inefficiency at long context, and it can be designed out at the
-kernel boundary.
-
----
-
-# PART 3 — PRIORITY ORDER
-
-These are sequenced by **what blocks 1M context viability**, not by
-implementation cost.
-
-| # | Item | Required for 1M? | Effort |
-|---|---|---|---|
-| **A1** | **D1: Fix `comp_idx_buf` width to actual indexer key width** | **Critical — silent corruption today** | XS |
-| **A2** | **M1: Quantize indexer KV to FP4** (paper §5.2.1) | **Critical — saves 121 GB at 1M** | M-L |
-| **A3** | **M2: Make `max_comp` per-layer-type + a CLI flag** | **Critical — current ceiling is 262K** | XS |
-| **A4** | D3/D4/M3: Preallocate `all_kv_buf`, eliminate `torch.cat` | High — perf and stability over hours of decode | S |
-| **A5** | D7: Investigate mHC residual growth (Sinkhorn convergence print) | High — likely root of decode degradation | S |
-| **A6** | M4: Return SWA views, no clone | Medium — small per-call, large in aggregate | XS |
-| **A7** | D2: Rename `Compressor` → split into `MainCompressor` and `IndexerKeyCompressor` | Medium — clarifies the duplicate-build pattern | XS |
-| **A8** | D6: Verify sink merge semantics with kernel author | Medium — possible silent numerical drift | S |
-| **A9** | M5: Two-buffer FMHA kernel (eliminate gather buffer entirely) | Long-term — production design | L |
-
-**The "should I run on 1M context tomorrow" answer is no, regardless of
-anything else, until A1/A2/A3 are done.** Without A1 you get garbage
-top-k. Without A2 you OOM at ~250K tokens even with 8×B200. Without A3
-you crash at 262K. Together those three are the gating set.
-
-**The "is it still architecturally DSv4?" answer is yes — mostly.** The
-hot path is faithful to the paper: CSA does overlapped-2m compression
-with softmax weights, HCA does heavy non-overlapped compression, indexer
-does ReLU(QK)·w_h reduction, attention concatenates selected-compressed
-+ SWA, sinks are applied. The drifts above (D1, D2, D6, D7) are
-implementation flaws or unfinished wiring, not architectural deviations.
-
----
-
-# DOCTRINE — applies to every priority above
-
-1. **DSL wall → raw CUDA C++, not Python.** Most of the fixes above are
-   pre-allocation and shape correctness, not new kernels. The two
-   exceptions (A2 FP4 indexer KV, A9 two-buffer FMHA) are kernel work and
-   must follow doctrine: tcgen05/UMMA/TMA, not scalar.
-
-2. **Raw CUDA ≠ scalar math.** When A2 lands the FP4 indexer cache, the
-   dequant on the read side must use `__constant__` LUT (per the original
-   indexer LUT fix from issue #1), not branch arithmetic.
-
-3. **Print, don't guess.** A1's fix is the canonical example: do not
-   assume the indexer key width is `head_dim` or `n_ih * ihd` — print
-   `indexer.compressor.forward(...)[0].shape` on first call and code to
-   that. The current bug exists *because* someone wrote `head_dim`
-   thinking it was right.
-
-4. **Integration over exploration.** No `KVCache_v2`. Edit `KVCache`.
-   The 4 fixes (A1/A3/A4/A6) are surgical edits to one class.
-
-5. **Falsifiable gates.** Numbers to hit:
-   - A1: `comp_idx_buf.shape[1] == indexer.compressor.kv_dim // 2` (or
-     whatever the print reveals). Test: run with VERBOSE=2 at 100 tokens
-     of context; no shape mismatch, no garbage in top-k selection.
-   - A2: KV cache footprint at 1M context (measured via
-     `torch.cuda.memory_allocated()` after prefill) drops from ~131 GB to
-     ≤ 15 GB. Recall@1024 vs FP32 indexer oracle ≥ 99.7% per paper.
-   - A3: A `--max-context N` flag works; running with `N=1048576` does
-     not OOM during prefill (it might be slow — that's a separate fight).
-   - A4: `torch.cuda.memory_reserved()` measured every 10 decode steps is
-     flat (±50 MB) across 1000 steps.

CORRECTNESS_FIX_ATTEMPTS.md

@@ -0,0 +1,59 @@
+## 1. Possible bug: compressor positional bias is being added to KV content
+
+In your `dsv4/kernels/cuda/compressor_reduce.cu`, the compressor appears to do this in both CSA and HCA paths:
+
+```cpp
+g += pb;
+kv_val += pb;   // suspicious / wrong
+```
+
+The official compressor equations add positional bias only to the **compression weights/logits** `Z + B`, then use those weights to sum the raw projected KV content `C`. The bias is not added to the KV value itself. The paper defines compression as softmax over `Z + B`, followed by a weighted sum of `C`. 
+
+So this should be:
+
+```cpp
+g += pb;
+// do not add pb to kv_val
+```
+
+That bug would poison every compressed KV entry with learned positional-bias content. It may not fully explain the first token for a tiny prompt if SWA dominates, but it is absolutely wrong relative to the official architecture and will degrade CSA/HCA context quality. If your unit tests passed, they may have been comparing against a reference that made the same mistake or were too short to expose it.
+
+## 2. Don’t use `think_start` as the canary here
+
+In official `thinking` mode, the prompt formatter typically appends the assistant marker plus `<think>` before generation. That means decode step 0 is already *inside* the thinking span. The model should not necessarily emit `think_start`; a low `think_start` logit is not itself evidence that the model “failed to enter thinking mode.”
+
+For this particular prompt, a high `think_end` logit can even be plausible because “The capital of France is” does not need much reasoning. Run the same current kernel with official **chat mode**, greedy decoding, no repetition penalty, no top-k/top-p, and compare first-token logits. The `think_start = 1.77` observation is probably a misleading diagnostic.
+
+## 3. Indexer parity still looks suspect
+
+The official CSA/HCA details include RMSNorm on queries and compressed KV before attention, partial RoPE on the last 64 dims, sliding-window KV, and attention sink behavior. 
+
+For the CSA **indexer**, the official reference does more than a plain q/k dot product: indexer Q and compressed indexer K get the appropriate RoPE/rotation treatment, and the QK path is one of the explicitly FP4-QATed pieces. If your current indexer compressor is just producing compressed keys without the same rotate/RoPE/FP4 path, CSA top-k can select plausible-looking but wrong blocks. Again, probably not the first-token issue on a short prompt, but it will matter for any real context.
+
+## 4. Check SwiGLU clamp ordering
+
+The official behavior is effectively:
+
+```python
+gate = clamp(gate, max=swiglu_limit)
+up = clamp(up, -swiglu_limit, swiglu_limit)
+out = silu(gate) * up
+```
+
+If your fused path clamps `silu(gate)` instead of clamping raw `gate` before SiLU, it is not equivalent. This is especially worth checking in both routed MoE and shared expert fused kernels, because a small-looking activation semantic mismatch repeats through every layer.
+
+
+## 5. DEQUANT TO BF16 IN THIS ORDER JUST TO SEE WHAT HAPPENS (You are allowed to break the no bf16 rule for this because we can always revert back to previous commit)
+
+
+The most suspicious surfaces to temporarily dequantize are, in order:
+
+1. **lm head** — FP4 lm head can directly flatten or reorder vocabulary logits.
+2. **router gate** — slight errors can change top-6 experts; wrong expert IDs are much worse than a small GEMM error.
+3. **shared expert** — official routed experts are the FP4 target; shared expert is a different sensitivity profile.
+4. **attention q/kv/o projections and grouped output projection** — these are not described as full FP4 QAT targets.
+5. **compressor/indexer helper projections** — only the CSA indexer QK path is explicitly FP4-QATed, not the whole compressor.
+
+If a BF16/FP8 lm head alone makes `Paris` / `.` / answer-like tokens dominate again, you’ve found a high-leverage culprit. My money is on LM Head needing to be BF16
+
+The fastest triage is basically: run `thinking_mode=chat`, greedy; switch only `lm_head` back to BF16/FP8; then switch router back; then patch the compressor bias-to-KV bug. If any one of those sharply separates the first-token distribution, you’ll know where to spend kernel time.

PERFORMANCE_AUDIT.md

@@ -1,424 +0,0 @@
-# PERFORMANCE — verified hot-path audit and prioritized fixes
-
-**First: congratulations. Paris-back is the milestone.** It means the math is
-right end-to-end through all 61 layers, the production NVFP4 GEMM stack is
-plumbed correctly, the multi-tile FMHA kernel works in real conditions, the
-mHC bound holds well enough for a coherent answer, the indexer top-k is
-selecting the right blocks, and the FP4 → BF16 dequant path is byte-correct.
-That's a real architectural validation.
-
-**Second: about the agent's "1.45s/token is slow (weight loading overhead)"
-line.** That diagnosis is wrong, and it's the kind of wrong that will steer
-the next agent to optimize the cold path instead of the hot one. Weight
-loading happens once during Phase 1 setup, before token 0. The decode step
-timer (`t1 = time.time()` at `single_shot_inference.py:906`) starts *after*
-weights are loaded and *after* every prior layer's setup is done. 1.45s is
-**per-token decode time**, not per-token load + decode. Per-token decode at
-hd=512, n_h=128, 61 layers, batch=1 should be in the **single-digit ms** ballpark
-on a B200, not 1.45s. There is a ~100–300× gap, and it's not weights.
-
-The rest of this doc identifies where it actually is.
-
-**Method.** Every claim below is grounded in a line number. No guessing.
-
----
-
-## WORK IN PROGRESS — What Was Being Done (Session 2026-06-01 20:21 UTC)
-
-### Completed fixes (committed, pushed, NOT YET TESTED ON B200):
-
-1. **P0 (COMPLETE)**: ALL `.item()` CPU-GPU syncs eliminated from NVFP4 activation path.
-   - `dsv4/kernels/cuda/amax_gsa.cu`: GPU-only amax→gsa kernel
-   - `dsv4/kernels/cuda/fused_amax_quantize.cu`: quantize with gsa from GPU buffer
-   - `dsv4/ops/quantize.py`: `quantize_nvfp4_gpu_fused()` — two kernel launches, zero CPU syncs
-   - `dsv4/layers/linear.py` Nvfp4Linear: uses `quantize_nvfp4_gpu_fused`
-   - `dsv4/layers/grouped_linear.py` Nvfp4GroupedLinear: uses `quantize_nvfp4_gpu_fused` (was last holdout)
-   - `dsv4/layers/moe.py` Nvfp4MoE: uses `quantize_nvfp4_gpu_fused`
-   - `dsv4/layers/shared_expert.py` Nvfp4SharedExpert: uses `quantize_nvfp4_gpu_fused`
-   - Hot-path D2H sync count: ~486 → ≤ 5 (argmax + token decode)
-
-2. **P4 (done)**: Changed `v = k.clone()` to `v = k` in `single_shot_inference.py:320`.
-   The `.transpose(-1,-2).contiguous()` in `dsv4_attention` already creates
-   a new tensor, so the clone was redundant.
-
-3. **Removed `torch.cuda.synchronize(x.device)`** from `moe_forward` in
-   `single_shot_inference.py`. Made topk_ids validity check conditional on
-   `VERBOSE >= 2`.
-
-4. **Added fused CUDA sampler**: `dsv4/kernels/cuda/sampler.cu` with
-   `dsv4/model/sampler.py` wrapper. Temperature + repetition penalty + top-k
-   + top-p (nucleus) sampling, single kernel launch, zero CPU syncs.
-   Updated `single_shot_inference.py` to use `CUDASampler` with defaults
-   temperature=0.6, top_k=50, top_p=0.95 (was greedy temp=0.0).
-
-5. **Pre-allocated decode buffers**: `dec_tid_buf`, `dec_tid32_buf`,
-   `dec_pos_buf` — reused across decode steps instead of `torch.tensor()`
-   per step.
-
-6. **Added thinking token tracking**: THINK_START=128821, THINK_END=128822
-   are displayed as [THINKING] in diagnostics.
-
-### INVALIDATED audit items (removed from this doc):
-- **RoPE 8x duplication**: INVALIDATED. Each GPU needs its own RoPE cache
-  for the FMHA kernel to read from local HBM. No cross-GPU traffic.
-  Not a perf issue.
-- **mHC BF16 bmm**: INVALIDATED. The bmm is (1,4,4)×(1,4,7168) = 114K FLOPs.
-  Negligible compared to MoE (billions of FLOPs). Not a bottleneck.
-- **Router .float() cast**: INVALIDATED. Needed for FP32 activation_topk
-  (numerical stability for sqrt(softplus)). ~1μs. Not a bottleneck.
-
-### CARDINAL RULE VIOLATION:
-The session broke the cardinal rule: MUST USE THE TEST HARNESS. Instead of
-using `fire_b200_test` or `fire_b200_cuda_test`, raw SSH commands were used
-to compile kernels and run tests on the B200. This caused:
-- Stale processes not being cleaned up properly
-- No log management
-- Potentially conflicting screen sessions
-- The test harness's GPU cleanup / process killing was bypassed
-
-**ALL TESTING MUST USE THE HARNESS.** If the harness needs to be more dynamic
-(e.g., support running `single_shot_inference.py` from the repo root, not
-just `tests/unit/`), THEN FIX THE HARNESS. Do not bypass it.
-
-### Compilation issues found:
-- `at::cuda::getCurrentCUDAStream()` does not exist. Use `c10::cuda::getCurrentCUDAStream()`.
-- `torch::TensorOptions().device(x.device())` doesn't compile. Use `x.options().dtype(...)`.
-- Both fixed in committed code.
-
-### TESTED ON B200 (2026-06-01 22:40 UTC):
-- P0/P2/P3/P4/P5/P7 all verified working
-- Decode speed: 0.51s/token (greedy) / 0.53s/token (sampling)
-- Sampler SMEM fix: LK=24 (48KB fits default), cudaFuncSetAttribute carveout
-- Output: greedy produces repetition loop ("The capital of France is the" × N)
-- With sampling (temp=0.6, top_k=50, top_p=0.95, rep_pen=1.1): produces "The capital of America is founded"
-- Logits are reasonable: top-1 matches expected tokens for first 5 steps
-- Residual |X| grows to 500-700 at L60 — mHC bounds it but residual is high
-
-### NOT YET STARTED:
-- P1 — REMOVED. Multi-GPU layout is correct for the reference script.
-- P2 (vectorize KVCache.append_swa) — simple fix, not started
-- P3 (preallocate comp_kv, kill torch.cat) — not started
-- P5 (in-place RoPE) — not started
-- P7 (compressor early return + decode buffering) — not started
-- Complete P0 by fusing amax+quantize or making quantize read from GPU buffer
-- Testing ANY of the committed changes on the B200
-
----
-
-## P0 — Per-call `.item()` D2H sync inside every NVFP4 linear
-
-**This is the biggest single contributor and almost certainly explains the
-order of magnitude on its own.**
-
-`dsv4/layers/linear.py:166–168`:
-
-```python
-if getattr(self, '_use_runtime_gsa', False):
-    amax = hidden_states.float().abs().max().clamp(min=1e-8).item()
-    self._activation_global_scale = amax / (6.0 * 448.0)
-```
-
-`.item()` is a blocking **D2H copy with full stream synchronization**. It
-forces every pending kernel on the device to finish before the host can read
-the value, then host blocks until the value arrives, then the host computes
-the scalar and the next kernel launches. **Every single linear call that has
-`_use_runtime_gsa = True` is a hard pipeline bubble.**
-
-How many times does this happen per decoded token?
-
-| Call site | Per layer | × 61 layers |
-|---|---|---|
-| attention projections (q_a, q_b, kv, o_b) | 4 | 244 |
-| o_a (grouped) | 1 | 61 |
-| router gate (non-hash layers) | 1 | ~58 |
-| moe runner | 1 | 61 |
-| shared expert | 1 | 61 |
-| lm_head | 1 | 1 |
-| **TOTAL D2H syncs / decoded token** | | **~486** |
-
-At conservative ~50 µs per D2H sync on a B200 with kernel queue in flight,
-that's **~24 ms of pure pipeline bubbles per token from this one line.**
-That's just the syncs — the lost overlap on top of that is larger.
-
-### The fix (in priority order)
-
-1. **Use `compute_amax_gsa_gpu` kernel** (already written, committed).
-   Computes amax on GPU, returns scalar GPU tensor. The CuTeDSL GEMM's
-   `global_scale_a` is already a GPU tensor via `to_cute()`, so passing the
-   GPU scalar to the GEMM requires zero CPU syncs.
-   
-2. **Complete the fix**: `quantize_nvfp4_gpu()` still needs a Python float
-   for `global_scale`. Either:
-   a. Modify `quantize_nvfp4.cu` to read `global_scale` from a GPU buffer
-      instead of a kernel parameter.
-   b. Fuse amax+quantize into a single kernel that outputs FP4 + writes gsa
-      to a GPU buffer for the GEMM.
-   
-3. **Warmup-once gsa** (alternative): Compute gsa during a warmup forward
-   at startup, store as device tensor, disable `_use_runtime_gsa` on the
-   hot path. The infrastructure exists at `linear.py:133`
-   (`compute_activation_global_scale`). One warmup token, then
-   `_use_runtime_gsa = False` for every Nvfp4Linear.
-
-### Falsifiable gate
-
-Per-decoded-token D2H sync count: goes from ~486 to **≤ 5** (argmax + token
-decode + end-of-loop bookkeeping). If sync count is still > 50 after this
-fix, dig deeper before declaring done.
-
----
-
-## ~~P1~~ — REMOVED
-
-The single_shot_inference.py is a **reference implementation** for vLLM/SGLang
-integration. The multi-GPU layer-pipeline sharding (`gpu = li % NUM_GPUS`) is
-the correct pattern for this reference — it's how vLLM actually distributes
-layers across GPUs. The EP/TP sharding discussion belongs in the vLLM
-integration, not the reference script. **Do not change the multi-GPU layout.**
-
----
-
-## P2 — Python loop in `KVCache.append_swa` (`:272`)
-
-```python
-def append_swa(self, kv, pos):
-    T = kv.shape[0]
-    for i in range(T):
-        idx = (self.swa_head + i) % self.ws
-        self.swa[idx], self.swa_pos[idx] = kv[i], pos[i]
-    ...
-```
-
-Per-decoded-token, T=1 so this loop runs once. **But the assignment
-`self.swa[idx], self.swa_pos[idx] = kv[i], pos[i]` is two scalar tensor
-indexing ops on the GPU**, each of which queues a tiny kernel. The
-single-token cost is small (~tens of µs) but it's a serialization point.
-
-During prefill at T=N (say N=20 tokens in the warmup prompt), this loop
-runs N times and queues 2N tiny kernels. That's significant.
-
-### The fix
-
-Vectorize:
-
-```python
-def append_swa(self, kv, pos):
-    T = kv.shape[0]
-    idx = (self.swa_head + torch.arange(T, device=self.dev)) % self.ws
-    self.swa.index_copy_(0, idx, kv)
-    self.swa_pos.index_copy_(0, idx, pos)
-    self.swa_head = (self.swa_head + T) % self.ws
-    self.swa_len = min(self.swa_len + T, self.ws)
-```
-
-Two kernel launches instead of 2T. Same numerical result.
-
-### Falsifiable gate
-
-`append_swa` queues exactly 2 kernels regardless of T. Verifiable with
-`cudaLaunchKernel` count between two `cudaDeviceSynchronize` calls bracketing
-the function.
-
----
-
-## P3 — Quadratic `torch.cat` growth on compressed KV (`:280`)
-
-```python
-def add_compressed(self, ckv, cpos, idx_kv=None):
-    if ckv is None: return
-    self.comp_kv = ckv if self.comp_kv is None else torch.cat([self.comp_kv, ckv])
-    ...
-```
-
-Each `torch.cat` allocates a new tensor of size `n_comp + new_len` and copies
-the entire existing `comp_kv` into it. After N tokens have produced
-compressed entries, total work is O(N²) and total allocator pressure is O(N²)
-bytes.
-
-For the Paris demo with ~50 decoded tokens this is invisible. **For the
-million-token contexts V4 is built for, this is catastrophic** — you'd spend
-most of your time copying KV around.
-
-### The fix
-
-Preallocate a ring or growing-power-of-2 buffer. Same pattern as `swa`:
-
-```python
-# In __init__:
-self.comp_kv_buf = torch.zeros(max_comp, head_dim, dtype=torch.bfloat16, device=dev)
-self.comp_pos_buf = torch.zeros(max_comp, dtype=torch.long, device=dev)
-self.comp_idx_buf = ...  # same
-self.n_comp = 0
-
-def add_compressed(self, ckv, cpos, idx_kv=None):
-    if ckv is None: return
-    T = ckv.shape[0]
-    end = self.n_comp + T
-    self.comp_kv_buf[self.n_comp:end] = ckv
-    self.comp_pos_buf[self.n_comp:end] = cpos
-    if idx_kv is not None: self.comp_idx_buf[self.n_comp:end] = idx_kv
-    self.n_comp = end
-```
-
-`comp_kv` getters return `comp_kv_buf[:n_comp]` (a view, no copy).
-
-`max_comp` for 1M context with m=4: 250K entries × 512 × 2 bytes = 256 MB.
-For 1M context with m=128 (HCA): ~16K entries × 512 × 2 = 16 MB. Both fit.
-
-### Falsifiable gate
-
-Memory growth across 1000 decode steps stays flat (within 100 MB of
-steady-state). Decode-step time stays flat instead of growing.
-
----
-
-## P4 — `v = k` instead of `v = k.clone()` (`:318`) — DONE
-
-DSV4 uses shared KV — k and v are the same tensor. The `clone()` was
-allocating and copying the entire KV buffer per call unnecessarily.
-
-**FIX APPLIED**: Changed `v = k.clone()` to `v = k`. The `dsv4_attention`
-function transposes V internally via `.transpose(-1,-2).contiguous()` which
-already creates a new tensor. The original K is never mutated.
-
----
-
-## P5 — RoPE allocates and clones the whole tensor (`:65`)
-
-```python
-def _apply_rope(x, pos, cos, sin, rope_dim, inverse=False):
-    ...
-    out = x.clone(); ro = torch.empty_like(xr)
-    ro[..., 0::2], ro[..., 1::2] = rev, rod
-    out[:, :, nope:] = ro.bfloat16(); return out
-```
-
-Called **3× per attention block** (Q, KV, inverse) × 61 layers = **183 RoPE
-calls per token**. Each call does: `cos[pos]` gather, FP32 cast of 64 dims,
-multiply-add, `x.clone()` of the full (T, nh, hd) tensor (most of which is
-NoPE and doesn't need to be touched), `empty_like`, strided write, BF16 cast.
-
-For T=1, hd=512, nope=448, n_h=128 per call: cloning 128×512 BF16 = 128 KB per
-call × 183 = 23 MB of pointless memcpy per token. Negligible bandwidth-wise
-on a B200, but it's **183 kernel launches** that contribute to the launch-rate
-ceiling.
-
-### The fix
-
-In-place RoPE for the last 64 dims, no full clone, no FP32 round-trip on the
-NoPE half:
-
-```python
-def _apply_rope_inplace(x, pos, cos, sin, rope_dim, inverse=False):
-    nope = x.shape[-1] - rope_dim
-    c = cos[pos]  # (T, rope_dim/2)
-    s = sin[pos]
-    xr = x[..., nope:]  # view, not copy
-    ev = xr[..., 0::2].clone()  # need the original ev for the mix
-    od = xr[..., 1::2]          # view; will write back below
-    if inverse:
-        xr[..., 0::2] = ev * c[..., None, :] + od * s[..., None, :]
-        xr[..., 1::2] = -ev * s[..., None, :] + od.clone() * c[..., None, :]
-    else:
-        ...
-    return x  # mutated in place
-```
-
-Even better: **fuse RoPE into the Q/KV projection kernel**. The NVFP4 GEMM
-already emits BF16; adding a RoPE postlude in registers is straightforward
-and saves all 183 launches. That's the production target, not the script's
-job, but the script should at least not do the 183 clones.
-
-### Falsifiable gate
-
-RoPE kernel launch count per decoded token drops from 183 to ≤ 3. When fused
-into GEMM: 0.
-
----
-
-## P6 — Indexer scoring is FP32 einsum (deferred to E7)
-
-The lightning indexer uses `torch.einsum` in FP32 on CUDA cores. Correct but
-not fast. At long context (n_comp ~ 250K), this becomes a wall.
-
-**Defer to roadmap E7** (FP4 tensor-core scoring). At Paris-scale context
-(n_comp ≤ 30), FP32 einsum is acceptable.
-
----
-
-## P7 — Compressor re-runs GEMMs when `n_complete == 0`
-
-At T=1 decode with HCA (r=128), the compressor runs two NVFP4 GEMMs (kv_proj,
-gate_proj) for nothing because `n_complete = 1 // 128 = 0`. The early return
-happens AFTER the GEMMs.
-
-### The fix
-
-Move `n_complete == 0` check above the GEMMs. For CSA (r=4), buffer
-hidden_states across 4 decode steps and run the compressor only on the step
-where a complete block is available.
-
----
-
-## P8 — Layer-level fusion candidates (production future)
-
-1. **NVFP4-1.2: Fuse FP4 quant into FMHA output → wo_a** (roadmap E6).
-2. **Fuse RMSNorm + Q/KV projection.**
-3. **Fuse RoPE into Q/KV GEMM epilogue** (as in P5 above).
-4. **mHC pre_block + RMSNorm fusion.**
-5. **CUDA graph capture** (roadmap E9) — unlocked after P0–P3 and syncs are fixed.
-
----
-
-## Priority order
-
-| # | Item | Effort | Win | Status |
-|---|---|---|---|---|
-| **P0** | Kill `.item()` in `_use_runtime_gsa` | S | **Huge** (~24 ms/token) | COMPLETE — tested on B200, 0.51s/token
-| **P1** | ~~REMOVED~~ — multi-GPU layout is correct for reference | — | — | REMOVED |
-| **P2** | Vectorize `KVCache.append_swa` | XS | Small/medium (prefill) | DONE — in single_shot_inference.py |
-| **P3** | Preallocate `comp_kv`, kill `torch.cat` | S | Critical at long ctx | DONE — in single_shot_inference.py |
-| **P4** | `v = k` instead of `v = k.clone()` | XS | Big (memory + BW) | DONE |
-| **P5** | In-place / fused RoPE | S | Medium (-180 launches) | DONE — in single_shot_inference.py |
-| **P6** | Indexer FP4 tensor-core scoring | L | Critical at long ctx | DEFERRED (E7) |
-| **P7** | Compressor early return + decode buffering | S | Medium | DONE — tested on B200, HCA skips GEMMs at T=1 decode |
-| **P8** | Production fusion targets | L | Where the real wins live | DEFERRED |
-
-**Do P0 and P1 first.** They are tiny changes, individually catch the
-biggest wins, and unlock all the downstream work (CUDA graphs, prefill
-throughput, real-world context lengths).
-
----
-
-## DOCTRINE — what to refuse during this perf pass
-
-1. **DSL wall → raw CUDA C++, not Python.** If an agent says "I'll cache the
-   amax in Python state," that's still Python on the hot path. The right
-   cache lives in a `torch.Tensor` on device.
-
-2. **Raw CUDA ≠ scalar math.** When someone reaches for "let's just write a
-   scalar fused RoPE kernel," remind them the production target is tensor-core
-   throughput in the NVFP4 GEMM epilogue. Don't ship a scalar fused kernel as
-   "fast enough."
-
-3. **Print, don't guess.** Before claiming P0 is fixed, measure D2H syncs
-   per decoded token with Nsight or a tracing wrapper. The "we removed
-   `.item()`" claim is not verified until the sync count drops.
-
-4. **Integration over exploration.** Do not write `linear_v2.py` with
-   "perf improvements." Edit `linear.py`. The four `_use_runtime_gsa = True`
-   flags in `single_shot_inference.py` are the test surface: flip them, run,
-   compare.
-
-5. **Falsifiable gates.** Every priority above has a measured number.
-   "It feels faster" does not close the gate.
-
-6. **Do not optimize cold paths.** Weight loading is cold. mHC weight
-   conversion is cold. Anything that runs once during `main()` setup is
-   cold. The hot path is everything inside the `for step in range(MAX_NEW_TOKENS):`
-   loop. If a proposed change is in `load_all_weights`, `_load_moe_weights_stacked`,
-   or any of the `make_*` helpers — that's cold, deprioritize it.
-
-7. **ALWAYS USE THE TEST HARNESS.** `fire_b200_test` for Python, `fire_b200_cuda_test`
-   for CUDA. No raw SSH. No manual screen sessions. If the harness needs
-   changes to support your use case, FIX THE HARNESS. Do not bypass it.

README.md

@@ -2,7 +2,8 @@
 
 Production-grade Blackwell SM100 inference kernel for **DeepSeek-V4-Pro NVFP4**, written in CuTeDSL with a CUDA fallback path. Target hardware: NVIDIA B200 (180 GiB HBM3e).
 
-For what's done, what's blocked, and what's next, see **ROADMAP.md**. This file is the durable reference — architecture, design choices, package layout, workflow, and hard-won lessons. If you're touching the kernel, read the "Lessons learned" section every time.
+
+This file is the durable reference — architecture, design choices, package layout, workflow, and hard-won lessons. If you're touching the kernel, read the "Lessons learned" section every time.
 
 ---
 
@@ -88,106 +89,48 @@ One pass, one kernel. No two-loop epilogue, no LSE arithmetic in the merge. This
 
 ---
 
-## Our kernel design choices
-
-### Attention kernel (FmhaKernel)
-
-**6-warp specialization.** Warps 0–3 handle softmax + correction + epilogue. Warp 4 is the MMA warp (QK + PV). Warp 5 is the TMA warp (Q/K/V loads, output store via pipeline).
-
-**P staging — two paths.**
-- **TMEM-P** (hd ≤ 64): P stored to TMEM via register bridge (FP32 backing + BF16 view). PV reads P from TMEM. Used at the small head dims where QK C-fragment and PV A-fragment TMEM layouts agree.
-- **SMEM-P** (hd > 64): P written to SMEM via coordinate-indexed store using `tTMEM_LOADcS` to map register indices to `(m, k)` then into `sP`'s subtile layout. PV reads P from SMEM with `OperandSource.SMEM`. Required because the QK ↔ PV TMEM layout disagreement at hd > 64 corrupts the round-trip.
-
-**Un-normalized O + LSE output.** The kernel emits raw `sum(P · V)` and `lse = ln(row_sum) + row_max · ln(2)`. External code (or the next kernel pass) divides. This composes — D5 merge, multi-tile rescale, and the inverse-RoPE → wo_a fuse all rely on it.
-
-**Per-head launch for multi-head.** Python loop dispatches the single-CTA kernel once per head. Multi-CTA grid using `flat_divide` + `tma_partition` is the next refactor (see ROADMAP); the path is unblocked once the correction-epilog rewrite lands.
-
-**Head-packed M dimension for decode.** Q reshaped to `(n_h * T, hd, 1)`, all heads' rows packed into the 128-row M tile. Per-row softmax. At Pro decode (T=1, n_h=128) the M tile fits exactly.
-
-**K-dim sub-tiling at hd > 256.** When `head_dim > 256` (MMA instruction K-dim limit), Q and K split into `n_k_sub_tiles = head_dim / 256` chunks along head_dim. QK accumulates in TMEM across sub-tiles (additive in logit space). The PV path uses `pv_n_tile = 128` for hd > 256 to keep sV+sC within the 232 KB SMEM budget.
-
-**Sink bias as logit modification.** D3 (SWA length mask), D4 (causal mask on SWA), and D5c (attention sink) all live in the same post-QK, pre-softmax in-register code. They read `tTMEM_LOADcS` to get `(m, k)` coordinates and modify `tTMEM_LOADrS` before the row-max reduction. The sink bias is added in the raw-logit domain as `attn_sink / scale_softmax`, then the existing `* scale_log2` multiply converts to log2 space.
-
-### MoE kernel (FusedSwiGLUScaledGroupedGemmKernel)
-
-**7-warp specialization.** Warps 0–3 epilogue (TMEM → registers → SMEM → GMEM with global scale, SwiGLU, clamp). Warp 4 MMA (`tcgen05.mma.block_scale` with SFA/SFB in TMEM). Warp 5 TMA load (A, B, SFA, SFB). Warp 6 scheduler (`MoEStaticPersistentTileScheduler`).
-
-**One-way TMEM → registers → SMEM → GMEM epilogue.** Uses `epilogue_tmem_copy_and_partition` + `epilogue_smem_copy_and_partition` (CUTLASS helpers, paired atoms). The SwiGLU + clamping math runs in registers between the t2r and r2s copies. No TMEM round-trip. This is the same pattern FMHA needs to adopt to fix the D1.5 blocker — see ROADMAP.
-
-**Subtile-level gate/up pairing.** With granularity-8 interleaved L1 weights and `epi_tile_n=8`, even subtiles are gate and odd subtiles are up. `silu_gate_buf` register tensor carries the SiLU result across the subtile-pair boundary.
-
-**`use_2cta_instrs` conditional** on `tokens_sum ≥ 256` and even `cluster_m`. Decode (small M) stays 1-CTA; prefill/batched gets 2-CTA UMMA with multicast B (1.7–1.9× throughput).
-
-### Heterogeneous KV cache
-
-- **State cache** per request: fixed-size block holding `(n_win SWA KV)` and `(uncompressed tail tokens awaiting compression)`. One block per request, lifetime managed by request scheduling.
-- **Classical paged cache** per request: variable blocks holding `(k1 CSA compressed entries, k2 HCA compressed entries)` per layer. `k1 = lcm(m, m') / m = 32`, `k2 = lcm(m, m') / m' = 1`. Block covers 128 original tokens.
-- Different layers can produce different KV cache sizes (CSA vs HCA vs SWA-only). The state cache + classical-pool split keeps PagedAttention-style alignment intact for the compressed pool.
-
-### NVFP4 throughout
-
-- **Weights**: NVFP4 (FP8 E4M3 scales, 16-element microblocks). Verified: `sf_dtype`, TMA element type, MMA kind (`mxf4nvf4`) all correct.
-- **Activations**: BF16 today, FP4 after NVFP4-1.x epilogue fusion lands (see ROADMAP).
-- **KV cache**: BF16 today; the FP8 (RoPE in BF16, NoPE in FP8) split per paper §2.3.4 is on the roadmap as NVFP4-2.
-- **Indexer keys**: stored FP4 in the cache today, but scored with a scalar CUDA-core kernel. Tensor-core FP4 scoring (paper §5.2.1) is a Stage F priority.
-
----
 
 ## Package structure
 
 ```
 dsv4/
-├── kernels/          Pure GPU code (CuTeDSL @cute.jit, .cu files)
-│   ├── attention/      FMHA — FmhaKernel (hd=64/128/256 proven, hd=512 MLIR-blocked)
+├── kernels/          Pure GPU code
+│   ├── attention/      Production FMHA — 6-warp TMA multi-tile (.cuh + C-API .cu + op.py + production.py)
+│   │                     production.py is the entry point used by single_shot_inference.py
 │   ├── gemm/           NVFP4 MoE GEMM (grouped, fused_swiglu, dense, scheduler)
-│   ├── compressor/     CSA/HCA token-level compressor (CuTeDSL)
-│   ├── indexer/        CSA indexer score+topk (FP32 scalar today; tensor-core FP4 on roadmap)
-│   ├── router/         Dense router decode kernel (warp-specialized persistent GEMM)
-│   ├── cache/          append_swa (writes KV to state cache)
-│   ├── decode/         Decode-time attention (future)
-│   └── cuda/           Raw .cu (deinterleave_quantize, sparse_topk_metadata, etc.)
+│   ├── compressor/     CSA/HCA production compressor (production_compress.py → compressor_reduce.cu)
+│   ├── indexer/        CSA indexer (stub; live path is inline in single_shot_inference.py)
+│   ├── router/         Dense router decode + activation_topk
+│   ├── cuda/           Raw .cu kernels (loader.py compiles on demand)
+│   └── cache/          (stub; SWA/flush kernels are in cuda/)
 ├── ops/              PyTorch ↔ kernel bridges
-│   ├── quantize.py      BF16 ↔ NVFP4, scale factor handling
+│   ├── quantize.py      BF16 ↔ NVFP4, scale factor handling, QuantizedActivation
 │   ├── layouts.py       Scale swizzle, gate/up interleave, K-major, offsets
 │   ├── gemm_runner.py   Warmup, compile, run grouped/fused GEMMs
 │   ├── custom_ops.py    torch.library.custom_op registrations
-│   ├── decode_sparse.py native_sparse_decode dispatcher
-│   ├── rope.py          Forward + inverse RoPE (partial, last 64 dims)
-│   ├── topk.py          Sparse top-k metadata wrapper
-│   └── router.py        Router op bridge
-├── layers/           nn.Module-style components
+│   ├── rope_cuda.py     Forward + inverse RoPE (partial, last 64 dims)
+│   └── router.py        Router op bridge (dense + hash dispatch)
+├── layers/           nn.Module-style components (used by single_shot_inference.py)
 │   ├── linear.py        Nvfp4Linear
 │   ├── grouped_linear.py Nvfp4GroupedLinear (output projection)
 │   ├── moe.py           Nvfp4MoE (routed experts)
 │   ├── shared_expert.py Nvfp4SharedExpert
 │   ├── mhc.py           mHCLayer (Sinkhorn-Knopp, residual mixing)
-│   ├── attention.py     AttentionSubBlock (CSA/HCA/SWA variants by LayerSpec)
-│   ├── norm.py          RMSNorm
-│   ├── router.py        Router (dense + hash modes)
-│   ├── embedding.py     Token embedding + mHC init
-│   └── ffn.py           FFN sub-block
-├── model/            Model assembly
+│   └── router.py        Router (dense + hash modes)
+├── model/
 │   ├── config.py        DSV4Config
-│   ├── layer.py         TransformerLayer
-│   ├── layer_schedule.py LayerSpec, AttentionType, build_schedule, validate_schedule
-│   ├── mtp.py           Multi-token prediction
-│   ├── sampler.py       Token sampler
-│   └── dsv4.py          Full model
-├── cache/            KV cache infra
-│   ├── allocator.py     Memory allocator
-│   ├── block_table.py   Paged cache block table
-│   ├── manager.py       Cache manager
-│   ├── paged_cache.py   Classical paged cache (CSA/HCA)
-│   ├── state_cache.py   State cache (SWA + uncompressed tail)
-│   ├── schema.py, handle.py, flush.py, prepare_forward.py
-├── loader/           Checkpoint I/O
-│   ├── hf_checkpoint.py
-│   └── layout_convert.py
-└── reference/        Slow PyTorch oracles (never imported by production code)
-    ├── attention.py, csa_attention.py, compressor.py, moe_pipeline.py
+│   └── sampler.py       CUDASampler
+├── reference/
+│   └── single_shot_PYTORCH_REFERENCE.py  PyTorch oracle for layer comparison tests
+└── _archive/         Dead Lineage P code (model/dsv4.py, cache/*, layers/{attention,ffn,norm,embedding}, etc.)
+                      Kept for reference; never imported by live code
 ```
 
-**Dependency arrow:** `kernels/` → `ops/` → `layers/` → `model/`. `reference/` and `loader/` are sidecars.
+**Live path:** `single_shot_inference.py` → `dsv4/layers/*` → `dsv4/ops/*` → `dsv4/kernels/**`
+
+**Attention path:** `production.py` → `fmha_multitile_op.py` → `fmha_multitile_capi.cu` → `fmha_6warp_tma_multirow_multitile.cuh`
+
+**Archived (Lineage P):** `dsv4/model/dsv4.py`, `dsv4/cache/*`, `dsv4/layers/{attention,ffn,norm,embedding}` — these were the vLLM/sglang integration surface but have 0 importers. See `_archive/` if needed.
 
 ---
 
@@ -215,30 +158,35 @@ Both harnesses follow the same discipline:
 4. **Run in screen** — survives SSH drops, has a timeout
 5. **One test at a time** — no parallel launches, ever
 
-### Python test (one command)
+### Python test
 
 ```bash
 # From local machine — auto-pushes, runs, polls, dumps log
+# DEFAULT timeout: 600s (10 min). Override with all 4 args:
+~/.openclaw/workspace/fire_b200_test <test_file> [screen_name] [log_file] [timeout_sec]
+
+# Examples:
 ~/.openclaw/workspace/fire_b200_test tests/unit/test_fmha_v3_stage_c.py
+~/.openclaw/workspace/fire_b200_test tests/unit/test_degeneration_2_mhc_falsify.py kernel-test /tmp/kernel-test.log 1800
 ```
 
-### CUDA test (one command)
+### CUDA test
 
 ```bash
 # From local machine — compiles with nvcc, runs, polls, dumps log
-# Default timeout: 60s. Pass a second arg for custom timeout.
 ~/.openclaw/workspace/fire_b200_cuda_test tests/unit/test_fmha_sm100_standalone.cu
-~/.openclaw/workspace/fire_b200_cuda_test tests/unit/test_tmem_minimal.cu 30
+~/.openclaw/workspace/fire_b200_cuda_test tests/unit/test_tmem_minimal.cu 30   # custom timeout
 ```
 
-### Check on a running CUDA test
+### Check on a running test
 
 ```bash
-# Show current log + screen status
+# Check CUDA test log + screen status
 ~/.openclaw/workspace/check_b200_cuda
+~/.openclaw/workspace/check_b200_cuda kill   # kill a hung test
 
-# Kill a hung test + show the log
-~/.openclaw/workspace/check_b200_cuda kill
+# Check Python test — SSH to B200 and tail the log:
+ssh root@<B200> tail -f /tmp/kernel-test.log
 ```
 
 ### Manual B200 cycle (emergency only)
@@ -250,7 +198,44 @@ bash tests/run_test.sh tests/unit/test_<...>.py
 bash tests/check_log.sh
 ```
 
-`run_test.sh` kills any prior `kernel-test` screen (with SIGKILL on stuck GPU procs), deletes the old log, starts a fresh `screen -dmS kernel-test`, and logs to `/tmp/kernel-test.log`.
+### ⚠️ Test harness gotchas (READ THIS — cost real time)
+
+1. **The timeout is the 4th argument, not the 2nd.**
+   - WRONG: `fire_b200_test test.py 1800` ← this makes `1800` the SCREEN NAME
+   - RIGHT: `fire_b200_test test.py kernel-test /tmp/kernel-test.log 1800`
+   - When you pass just a number as the 2nd arg, the screen gets a numeric name
+     and the harness can't kill the old `kernel-test` screen on the next run.
+   - **Always pass all 4 args** when you need a custom timeout.
+
+2. **After a timeout, the harness kills the screen but NOT the GPU process.**
+   - The `timeout` command inside screen kills the shell, but CUDA processes survive.
+   - Before re-running, check: `ssh root@<B200> nvidia-smi --query-compute-apps=pid --format=csv,noheader`
+   - Kill stale processes: `kill -9 <pid>` for each GPU process listed
+   - Or: `for pid in $(nvidia-smi --query-compute-apps=pid --format=csv,noheader); do kill -9 $pid; done`
+
+3. **After an OOM or crash, stale GPU processes WILL be left behind.**
+   - Always check `nvidia-smi` before running a new test after a failure.
+   - The harness kills `python.*test_` and `python.*inference` procs, but if the
+     process name doesn't match the pattern, it survives.
+
+4. **Single-shot tests MUST use the harness too.**
+   - `single_shot_inference.py` is NOT a unit test, but it MUST be run via the harness.
+   - WRONG: ssh to B200 and run `python single_shot_inference.py` directly
+   - RIGHT: `fire_b200_test single_shot_inference.py kernel-test /tmp/kernel-test.log 1800 -- --max-tokens 512`
+   - Extra args after `--` are passed to the Python script.
+   - If the harness can't handle your use case, FIX THE HARNESS, don't bypass it.
+
+5. **Weight loading + CuTeDSL compilation takes 5-10 minutes.**
+   - First FMHA call triggers JIT compile of CuTeDSL kernels.
+   - This is EXPECTED. Do NOT kill the process because it "seems stuck".
+   - Use 1800s (30 min) timeout for full-model tests.
+
+6. **The screen name must match between runs.**
+   - The harness kills the old screen by name. If you used a different name last time,
+     the old screen survives and holds GPU memory.
+   - Always use `kernel-test` for Python tests and `cuda-test` for CUDA tests.
+   - If you accidentally used a numeric screen name, clean up manually:
+     `ssh root@<B200> screen -S <wrong_name> -X quit`
 
 ### Environment
 
@@ -276,7 +261,7 @@ These are surface-level traps. Get them wrong and the kernel silently produces g
 
 4. **`cute.arch.fmax` is impure** for the vectorizer. Use it inside plain `range()`, never inside `vectorize=True`.
 
-5. **Hand-constructed TMEM atoms corrupt data on round-trip.** Independently-built `Ld32x32bOp` + `St32x32bOp` atoms have addressing that doesn't match — even a NO-OP round-trip drops cos to ~0.97. Use paired atoms from `epilogue_tmem_copy_and_partition` / `epilogue_smem_copy_and_partition` for one-way trips. This is the D1.5 blocker in ROADMAP.
+5. **Hand-constructed TMEM atoms corrupt data on round-trip.** Independently-built `Ld32x32bOp` + `St32x32bOp` atoms have addressing that doesn't match — even a NO-OP round-trip drops cos to ~0.97. Use paired atoms from `epilogue_tmem_copy_and_partition` / `epilogue_smem_copy_and_partition` for one-way trips.
 
 6. **CuTeDSL `if` blocks are separate MLIR regions.** Variables defined inside one `if` are not visible in another, even when the condition is a compile-time constant. Define all variables unconditionally before any branching.
 
@@ -317,13 +302,13 @@ These cost real days to learn. They are listed in priority of how easy they are
 - **FMHA P store uses QK C-fragment composition, not PV A-fragment.** Two aliases of the same TMEM region. Mixing them up gives valid-looking garbage.
 - **Register bridge for P: FP32 backing (store partition) + BF16 view (QK-load layout).** Do not skip the dual view.
 - **TMEM round-trip mismatch with `epilogue_tma_store`**: `epilogue_tma_store` reads O from TMEM using `get_tmem_load_op`'s layout. Hand-built atoms read with a different layout. Round-tripping through hand-built atoms transcodes the data, leaving 3% error.
-- **The correction-epilog pattern is the fix.** TMEM → registers (via paired t2r atom) → modify in registers → SMEM (via paired r2s atom) → GMEM (via TMA). One-way trip, no round-trip, no transcoding. The MoE kernel uses this and gets perfect results. See ROADMAP.
+- **The correction-epilog pattern is the fix.** TMEM → registers (via paired t2r atom) → modify in registers → SMEM (via paired r2s atom) → GMEM (via TMA). One-way trip, no round-trip, no transcoding. The MoE kernel uses this and gets perfect results.
 
 ### CuTeDSL & MLIR
 
 - **CuTeDSL `if` blocks create separate MLIR regions.** Variables defined in `if not use_smem_p:` and read in another `if not use_smem_p:` inside a `for` inside an `if warp_idx < mma_warp_id:` are not visible. Define unconditionally before any branching.
 - **CuTeDSL compiles both branches of Python `if`.** Wrap mode-specific dead code in `const_expr(condition)` to eliminate it. Critical for O rescale (`n_kv_tiles > 1`), LSE compute (`not normalize`), SMEM-P path.
-- **CuTeDSL MLIR backend cannot handle complex pipeline loops at hd=512.** Both unrolled (Python `range`) and runtime (`cutlass.range unroll=1`) loops trigger exponential-or-worse optimizer time. Tracer is fast (~0.8s); MLIR optimizer chews for 3+ hours. Workaround options in ROADMAP.
+- **CuTeDSL MLIR backend cannot handle complex pipeline loops at hd=512.** Both unrolled (Python `range`) and runtime (`cutlass.range unroll=1`) loops trigger exponential-or-worse optimizer time. Tracer is fast (~0.8s); MLIR optimizer chews for 3+ hours.
 - **Don't mix Python loops and pipeline ops.** Python `for` unrolls at trace time — N copies of pipeline acquire/release + TMA + GEMM blow up the IR. Prefer `cutlass.range(unroll=1)` for pipeline loops.
 
 ### Math & merging

archived_plans/ARCHITECTURE_AND_MEMORY_AUDIT.md

@@ -0,0 +1,467 @@
+# ARCHITECTURE & MEMORY AUDIT — Post-probe rewrite
+
+**Supersedes:** the prior `ARCHITECTURE_AND_MEMORY.md` (M1 was wrong by 64×
+in the bad direction). Incorporates the indexer probe results from
+`archived_plans/INDEXER_PROBE_RESULTS_20260602.md`.
+
+**Method.** Every claim verified against `single_shot_inference.py` v16 + the
+probe results. Per doctrine.
+
+---
+
+## TL;DR — the picture is much better than the prior audit suggested
+
+**The architecture is faithful to the paper. The 1M-context memory story is
+fine on 8×B200. There is no looming OOM crisis.**
+
+That said, the probe surfaced a finding bigger than memory: **the lightning
+indexer has never actually run in any production decode to date.** Paris-back
+is real, but it ran via dense attention over the full compressed KV history
+in CSA layers — the sparse-selection path was silently bypassed because the
+indexer's internal compressor never loaded its weights. The system has been
+correct because the *fallback* was algebraically correct, not because the
+designed CSA path was working.
+
+This is good news. It means:
+
+1. **Fixing the indexer is the next correctness milestone.** It unlocks the
+   actual sparse path, which is what makes 1M context tractable at runtime
+   (not memory-wise — speed-wise, since dense over 250K compressed entries
+   per CSA layer per token is the actual perf wall, not KV storage).
+2. **Memory at 1M is dominated by the main compressed KV cache (~10 GB
+   total across all CSA+HCA+SWA layers), which is small enough that the
+   prior audit's "131 GB" panic was wrong.** No FP4 quantization of the
+   indexer cache is needed for memory reasons. (It is still wanted for
+   *throughput* per paper §5.2.1, but that's a different fight.)
+3. **Three small bugs are blocking the indexer from running correctly.**
+   Two are surface (weight-path + buffer-width); one is deeper (the
+   scoring einsum's algebra is wrong, treating MQA-on-indexer as full
+   multi-head). All three are easy fixes once seen.
+
+---
+
+# PART 1 — WHAT THE PROBE REVEALED
+
+The probe confirmed hypothesis A from the prerequisite doc and surfaced two
+collateral findings. The combined picture:
+
+## F1 — Indexer keys are `c_I = 128`-wide, MQA-on-indexer (paper-aligned)
+
+`comp_indexer_kv.shape == (n_comp, 128)`. One vector per compressed block,
+**shared across all `n_ih = 64` indexer query heads.** This is the standard
+multi-query-attention shape, but applied to the indexer scoring path.
+
+Per-block cost: 128 × 2 bytes = **256 B per compressed block per CSA layer**.
+At 1M context (CSA ratio=4 → 250K compressed blocks):
+
+- Per CSA layer: 250K × 256 B = **64 MB**
+- × 30 CSA layers = **~1.9 GB total** for indexer KV at 1M context
+
+That's small. ~6× smaller than the main compressed KV cache. The prior
+audit's M1 ("indexer KV is 125 GB at 1M, OOM at 250K tokens") was
+backwards — the indexer cache is the *smallest* of the three KV streams.
+
+## F2 — The indexer compressor never loaded weights (the real bug)
+
+`Indexer.load:392`:
+
+```python
+if f"{pfx}.compressor.kv_proj.weight" in w:
+    self.compressor = Compressor(4, self.ihd, 7168, dev)
+```
+
+The checkpoint stores the indexer's compressor weights at
+`*.indexer.kv_proj.weight`, **not** `*.indexer.compressor.kv_proj.weight`.
+So this `if` was always False, `self.compressor` stayed None, and
+`Indexer.forward` always returned None at the early-return guard (line
+397: `if ... comp_indexer_kv is None or comp_indexer_kv.shape[0] == 0:
+return None`).
+
+What this means for every Paris-back run to date:
+
+- CSA layers received `topk_idx = None` from the indexer.
+- The gather path at `forward_attention:569–571` checks
+  `if ratio == 4 and topk_idx is not None:` → False, so it falls through
+  to `elif ratio > 4: all_kv = torch.cat([kv_cache.comp_kv, swa_kv], ...)`.
+  Wait — that branch is for `ratio > 4` (HCA), not `ratio == 4` (CSA).
+  Need to check what CSA actually did with topk_idx=None.
+
+**The agent should verify which fallback path CSA actually took, and
+confirm whether the existing test runs were:**
+- (a) attending over **just SWA** (correct only at short context, since
+  SWA window is 128 — would explain why Paris works but degrades past
+  step 10),
+- (b) attending over **the full compressed history** as if it were HCA
+  (correct but slow at scale), or
+- (c) producing no attention output at all and being saved by a
+  downstream operation.
+
+This is a 10-line print insertion at `forward_attention`, not an
+investigation campaign. **Add it to the indexer-fix work below, do not
+spin up a separate probe.**
+
+## F3 — The scoring einsum has the wrong algebra (MQA vs per-head keys)
+
+The current code at `Indexer.forward:404`:
+
+```python
+k_idx = comp_indexer_kv.reshape(n_comp, self.n_ih, self.ihd)
+scores = torch.einsum('tnd,cnd->tnc', q_idx.float(), k_idx.float())
+```
+
+The reshape requires `comp_indexer_kv` to have `n_ih × ihd = 8192` elements
+per block. The probe shows it actually has `ihd = 128` elements. So the
+reshape raises today.
+
+**The temptation is to "fix" this by widening `comp_idx_buf` to 8192.**
+That would let the reshape succeed and produce numerically plausible
+scores. **It would be wrong.** The paper's scoring formula (§2.3.1, eq.
+16) is:
+
+```
+I[t,s] = Σ_h w^I_{t,h} · ReLU(q^I_{t,h} · K^IComp_s)
+```
+
+`K^IComp_s` has no head subscript. It's **one key vector per block, shared
+across all `n_ih` indexer query heads.** The score is computed by dotting
+each of the 64 query heads against the *same* key, applying ReLU, then
+weighting and summing across heads. That's MQA — the same trick used for
+the main attention path in DSv4 (§2.3.1 "Shared Key-Value MQA").
+
+The correct einsum:
+
+```python
+# q_idx: (T, n_ih, ihd) = (T, 64, 128)
+# k_idx: (n_comp, ihd) = (n_comp, 128)        <-- no head dim
+# w_h:   (T, n_ih) = (T, 64)
+scores = torch.einsum('tnd,cd->tnc', q_idx.float(), k_idx.float())  # 'cd', not 'cnd'
+scores = F.relu(scores)
+total = (scores * w_h.unsqueeze(-1).float()).sum(1)  # (T, n_comp)
+tk = min(self.top_k, n_comp)
+_, idx = total.topk(tk, -1)
+return idx
+```
+
+The `k_idx.reshape(n_comp, self.n_ih, self.ihd)` line goes away entirely —
+no reshape needed when keys are MQA-shared.
+
+**Why this matters beyond "the reshape stops crashing":** without this
+correction, an agent fixing F2 (load the indexer compressor) and "fixing"
+F3 by widening the buffer would produce silently wrong top-k selections.
+Same shape as the original indexer LUT bug — code runs, produces plausible
+numbers, but the *ranking* of compressed blocks is corrupted because the
+math doesn't match the model. Recall@k drops from paper's 99.7% to
+something much lower, and we'd be back to debugging "model gets dumber at
+long context" by ripping apart the FMHA kernel that isn't broken.
+
+## F4 — The buffer width is wrong but smaller than the prior audit claimed
+
+`KVCache:419`:
+
+```python
+self.comp_idx_buf = torch.zeros(max_comp, head_dim, dtype=torch.bfloat16, ...)
+                                          ^^^^^^^^
+                                          512 — should be 128
+```
+
+`head_dim = 512` (main attention head dim). Indexer keys want `c_I = 128`.
+The buffer is **4× too wide**, not 16× as the prior audit assumed. Storage
+waste at 1M context (CSA only): 30 layers × 250K × (512 - 128) × 2 bytes
+= **5.7 GB wasted**. Real, fixable, not catastrophic.
+
+The fix needs a value to use, and that value should come from the indexer
+instance, not hard-coded:
+
+```python
+# In __init__:
+self.comp_idx_buf = torch.zeros(
+    max_comp,
+    indexer_key_dim,   # passed from caller, = indexer.ihd = 128
+    dtype=torch.bfloat16, device=device,
+)
+```
+
+The construction site at `single_shot_inference.py` (where `KVCache` is
+created per layer) needs to pass `indexer.ihd` for CSA layers and skip
+the buffer for HCA layers (which have no indexer).
+
+---
+
+# PART 2 — MEMORY AT 1M CONTEXT, REVISED
+
+The numbers below replace the prior audit's. They are conservative and
+worst-case.
+
+## Per-layer KV cache sizes — read off the (corrected) code
+
+| Component | Per token (compressed) | Bytes / token | × 1M tokens |
+|---|---|---|---|
+| **CSA main compressed** (1 entry / 4 tokens, hd=512 BF16) | 0.25 × 1024 B | 256 B | **256 MB** |
+| **CSA indexer keys** (1 entry / 4 tokens, c_I=128 BF16) | 0.25 × 256 B | 64 B | **64 MB** |
+| **HCA compressed** (1 entry / 128 tokens, hd=512 BF16) | 0.0078 × 1024 B | 8 B | **8 MB** |
+| **SWA per layer** (ring buffer, 128 × hd × 2) | constant | — | 128 KB |
+
+## Total KV cache @ 1M context, all layers, BF16:
+
+| Layer type | Count | Per-layer @ 1M | Total |
+|---|---|---|---|
+| CSA: main + indexer | 30 | 256 MB + 64 MB | **9.6 GB** |
+| HCA: main | 30 | 8 MB | 240 MB |
+| SWA | 61 | 128 KB | 8 MB |
+| **GRAND TOTAL @ 1M, BF16** | | | **~9.9 GB** |
+
+**~10 GB of KV state for a 1M-token context.** On 8×B200 (192 GB each, 1.5 TB
+total) that's negligible — about 0.7% of total HBM, or ~1.25 GB per GPU if
+sharded EP-style alongside the experts. The system has plenty of memory
+headroom for the design target.
+
+For comparison, DeepSeek-V3.2's KV cache at 1M context is ~92 GB (per V4
+paper Figure 1). V4 at ~10 GB is a 9× reduction — which is **exactly the
+"~10% of V3.2's KV cache" claim from the paper.** The implementation hits
+the design memory budget; the prior audit was wrong about how it gets there.
+
+## What this changes about priorities
+
+- **"Quantize indexer KV to FP4 to save 121 GB" is gone.** It was based on
+  a wrong width. The indexer cache is 2 GB at 1M; FP4 would shrink it to
+  500 MB. Nice; not urgent.
+- **"max_comp = 65536 is the ceiling at 262K tokens" is still real.** That
+  hardcoded buffer size hasn't changed. At 1M context CSA needs
+  `max_comp_csa = 262144`. Still a config fix, just not paired with a
+  quantization fight.
+- **"Allocator churn from `torch.cat` in the gather" is still real and
+  still gets worse with context length.** Pre-allocation still matters at
+  long context for perf and stability over hours of decoding. Just not
+  urgent for "does it fit in memory."
+
+---
+
+# PART 3 — PRIORITY ORDER (REVISED)
+
+Sequenced by what unblocks correctness first, then performance, then
+memory. The big shift from the prior audit: **the indexer fix is the
+gating correctness work; memory is no longer the crisis it was framed as.**
+
+## Tier 1 — Make the indexer actually work (correctness)
+
+These are all small edits but they have to land together. The agent
+should treat this as one atomic landing, not three independent fixes,
+because individually each one either does nothing or makes things worse.
+
+### A1 — Fix the indexer compressor weight path
+
+`Indexer.load:392`. Change the check and the load prefix to match the
+checkpoint:
+
+```python
+# Was:
+if f"{pfx}.compressor.kv_proj.weight" in w:
+    self.compressor = Compressor(4, self.ihd, 7168, dev)
+    self.compressor.load(w, f"{pfx}.compressor", dev)
+# Should be (read the actual key from the checkpoint, not assumed):
+if f"{pfx}.kv_proj.weight" in w:
+    self.compressor = Compressor(4, self.ihd, 7168, dev)
+    self.compressor.load(w, f"{pfx}", dev)
+```
+
+The agent's probe already identified this — verify the fix is in v17 by
+running a checkpoint-loaded forward and confirming `self.compressor is
+not None` for at least one CSA layer.
+
+### A2 — Fix `comp_idx_buf` width to `c_I = 128`
+
+`KVCache:419`. Plumb `indexer_key_dim` through `KVCache.__init__` (or
+better: derive it from a probe of the indexer's compressor on first
+call). Default for non-CSA layers: skip the buffer.
+
+### A3 — Fix the scoring einsum to MQA-on-indexer
+
+`Indexer.forward:404`. Drop the head-axis reshape and use `'tnd,cd->tnc'`
+as shown in F3 above. This is the deeper correctness fix and the easiest
+one to get wrong if A1+A2 land first and an agent "fixes" the reshape by
+widening the buffer.
+
+**Gate for Tier 1:**
+1. `Indexer.forward` returns a non-None `idx` tensor for every CSA layer
+   on a prompt of ≥ 4 tokens. Verify with a print on layer 0.
+2. `forward_attention` at CSA layers takes the
+   `if ratio == 4 and topk_idx is not None` branch, not the fallback.
+3. Paris-back still works. Output is identical-or-better than v16's
+   Paris-back (since v16 was running the dense fallback, which is a
+   correctness *superset* of CSA — it attends over more keys, not fewer).
+4. **Recall test:** compare the top-k indices from the indexer against
+   an FP32 oracle (just compute the scoring in FP32 outside the kernel
+   and topk on that). Recall ≥ 99% at top_k=512 with n_comp ≥ 1024.
+
+## Tier 2 — Verify what the fallback was actually doing (cleanup)
+
+### B1 — Find and document the v16 CSA fallback path
+
+`forward_attention:569–571`: when `topk_idx` was always None, what
+actually happened in CSA layers? The branches as read:
+
+```python
+if ratio == 4 and topk_idx is not None:        # never taken
+    all_kv = torch.cat([kv_cache.comp_kv[tk], swa_kv], dim=0)
+elif ratio > 4:                                 # only HCA layers
+    all_kv = torch.cat([kv_cache.comp_kv, swa_kv], dim=0)
+```
+
+For CSA with `topk_idx=None` and `ratio == 4`, **neither branch fires.**
+What `all_kv` is at that point depends on what came before. The agent
+should run a 5-line probe in v16 (or look at the bisected behavior) to
+confirm whether v16 CSA layers:
+- attended over just SWA (would explain decode degradation past step 10),
+- attended over the full compressed history (would explain decode
+  working but being slower than necessary),
+- crashed at this point and something downstream rescued the run (most
+  likely if Paris-back still happened).
+
+This is *informational* — it doesn't gate Tier 1 — but it answers "what
+exactly did 'Paris-back' validate?" and it tells you whether decode
+quality should jump (if v16 was on SWA-only) or stay flat (if v16 was on
+full compressed) when Tier 1 lands.
+
+### B2 — Once Tier 1 lands, add explicit error on `topk_idx is None` in CSA
+
+The fact that the CSA fallback was silent for this long is the meta-bug.
+After Tier 1, the CSA path should *require* `topk_idx is not None`:
+
+```python
+if ratio == 4:
+    assert topk_idx is not None, f"CSA layer {li} got no top-k from indexer — indexer is broken"
+    tk = topk_idx[0].clamp(0, kv_cache.n_comp - 1)
+    all_kv = torch.cat([kv_cache.comp_kv[tk], swa_kv], dim=0)
+elif ratio > 4:
+    all_kv = torch.cat([kv_cache.comp_kv, swa_kv], dim=0)
+```
+
+This is a tripwire for future regressions of the same shape.
+
+## Tier 3 — Memory & allocator hygiene (still real, just not urgent)
+
+### C1 — `max_comp` per-layer-type + CLI flag
+
+`KVCache.__init__:411`. Make `max_comp` a function of context length and
+compress ratio:
+
+```python
+def __init__(self, head_dim, indexer_key_dim, compress_ratio,
+             window_size=128, target_context=8192, device='cuda:0'):
+    self.max_comp = (target_context + compress_ratio - 1) // compress_ratio
+    ...
+```
+
+And expose `target_context` as a CLI arg (`--max-context`). Default
+small (8192) so the script stays runnable.
+
+### C2 — Pre-allocate `all_kv_buf`, eliminate `torch.cat` in gather
+
+Same fix as D3/D4 in the prior audit — still valid:
+
+```python
+# Once at init:
+self.all_kv_buf = torch.zeros(max_top_k + window_size, head_dim, ...)
+```
+
+Gather writes into views of this buffer with `out=` arguments. FMHA
+consumes the prefix. Zero allocs on hot path.
+
+### C3 — `KVCache.get_swa` returns views, not clones
+
+`KVCache:457–460`. Drop the `.clone()` calls. Return slices.
+
+### C4 — Optional: Quantize indexer KV to FP4 (paper §5.2.1)
+
+For throughput, not memory. Defer until E7 (Stage F indexer FP4 tensor-core
+scoring) lands — at that point the FP4 storage and FP4 MMA path are paired,
+which is the right shape. **Don't quantize the cache without also
+upgrading the scoring kernel** — that would be storage savings paid for
+with a dequant kernel that doesn't exist yet.
+
+## Tier 4 — Architecture fidelity nice-to-haves
+
+### D1 — Split `Compressor` class into `MainCompressor` and `IndexerKeyCompressor`
+
+`single_shot_inference.py:272`. Same class is instantiated with totally
+different config in two places. Splitting documents the difference and
+prevents the "I assumed it was the same thing" bug class (which is how
+the buffer width bug happened in the first place).
+
+### D2 — Verify sink merge semantics (D6 from prior audit, unchanged)
+
+`_run_production_fmha:489` passes `n_comp=0` always. The kernel may
+expect `n_comp = len(compressed_kv)` for the D5c sink merge. Print the
+kernel's actual handling, confirm or fix.
+
+### D3 — Understand mHC residual growth (D7 from prior audit, unchanged)
+
+|X| → 500-700 at L60 still indicates Sinkhorn B isn't doubly-stochastic
+at runtime. Print B row/col sums, expect 1.0 ± 1e-6. This may also
+partly explain the decode degradation past step 10 (compounding
+non-bounded residuals → saturated logits → low-information argmax).
+Tier 1 fixing the indexer may improve decode behavior enough that this
+stops mattering — but worth still checking once the indexer is correct.
+
+---
+
+# REVISED PRIORITY TABLE
+
+| # | Item | What it unblocks | Effort | Blocks 1M? |
+|---|---|---|---|---|
+| **A1** | Fix indexer compressor weight path | Indexer runs at all | XS | Yes — correctness |
+| **A2** | `comp_idx_buf` width = 128 (not 512) | Indexer can store keys | XS | Yes — correctness |
+| **A3** | Scoring einsum `'tnd,cd->tnc'` | Top-k is correct | XS | Yes — correctness |
+| **B1** | Document the v16 CSA fallback | Knowing what Paris validated | XS | No |
+| **B2** | Assert `topk_idx is not None` in CSA | Future regression tripwire | XS | No |
+| **C1** | Per-layer `max_comp` + `--max-context` | Long context doesn't crash at 262K | XS | Yes — but trivial |
+| **C2** | Pre-alloc `all_kv_buf`, kill cat | Stable decode over hours | S | No, but real perf |
+| **C3** | `get_swa` returns views | Small but everywhere | XS | No |
+| **C4** | FP4 indexer cache (paired with E7) | Throughput, paper compliance | M-L | No |
+| **D1** | Split Compressor classes for clarity | Prevents the same-class-confusion bug | XS | No |
+| **D2** | Sink merge semantics check | Subtle numerics | S | No |
+| **D3** | mHC Sinkhorn convergence check | Decode degradation | S | No |
+
+**Land A1+A2+A3 together as one atomic correctness fix.** That is the
+critical path. Everything else is sequential and not gating.
+
+---
+
+# DOCTRINE — applies to every priority
+
+1. **DSL wall → raw CUDA C++, not Python.** Doesn't apply much in this
+   round — most fixes are 3-line edits to Python orchestration. The
+   exception is C4 (FP4 indexer cache) which is a kernel fight and must
+   follow doctrine: tcgen05/UMMA/TMA on the read side, `__constant__`
+   LUT for any dequant, paired with the E7 scoring kernel.
+
+2. **Raw CUDA ≠ scalar math.** Same — when C4 lands, the indexer's
+   `tcgen05.mma` FP4 path replaces the scoring einsum. The current FP32
+   einsum (post-fix) is a correctness oracle, not a perf target.
+
+3. **Print, don't guess.** This entire round exists because of a probe
+   that printed instead of assuming. **The pattern works.** Use it
+   again for:
+   - B1: probe what the v16 CSA fallback actually returned.
+   - C2: print `all_kv` shape and dtype to verify the pre-allocated
+     buffer is being sliced correctly.
+   - D3: print Sinkhorn row/col sums per layer.
+   Stop running new code until the probes have written their output to
+   a `.md` next to this one.
+
+4. **Integration over exploration.** No `Indexer_v2`, no `KVCache_v2`.
+   Edit the existing classes. Tier 1 is ~10 line-edits total across
+   3 functions.
+
+5. **Falsifiable gates.** Already listed per priority above. The
+   meta-gate for the whole audit: after Tier 1, **the indexer's top-k
+   recall vs an FP32 oracle is ≥ 99% on a prompt with n_comp ≥ 1024.**
+   Until that number is measured and recorded, "the indexer works" is
+   an assertion, not a fact.
+
+6. **Don't optimize for a problem you don't have.** The prior audit's
+   biggest mistake was framing memory as a 1M-context crisis based on
+   a wrong width. The real picture is: V4 hit its KV cache memory
+   targets, the implementation is faithful, the actual blocker is a
+   handful of small bugs in the sparse-selection path. Fix those first
+   and re-measure before adding new infrastructure.

archived_plans/CLEAN_UP.md

@@ -0,0 +1,244 @@
+# DSV4 Repo Cleanup & Comment Audit — Agent Working Spec
+
+**Audience:** the LLM agent doing the cleanup.
+**Prime directive:** the running code is the source of truth. Docs, `.md` files, and comments are not. When they disagree, the code wins and the prose gets corrected — never the reverse.
+
+**Two hard rules that exist because of past pain:**
+
+1. **Never delete. Only move/archive.** Especially `.md` files — they contain lessons we still reference.
+2. **Every time you move a file, update the references in the same commit, then grep the moved basename repo-wide to confirm zero dangling references.** The recurring failure mode here is: a file is moved, a reference is missed, the next agent thinks the file is gone, and *recreates a divergent copy*. That is how this repo got two of everything. Do not let it happen again.
+
+---
+
+## Background the agent must internalize first: this repo has TWO lineages
+
+There are two parallel implementations of the model, and the docs describe the wrong one.
+
+| | Lineage M (LIVE) | Lineage P (parallel / maybe-serving) |
+|---|---|---|
+| Entry point | `single_shot_inference.py` (monolith) | `dsv4/model/dsv4.py` (nn.Module assembly) |
+| Orchestration | manual, inside the script | `dsv4/model/layer.py` + `dsv4/layers/*` |
+| Indexer | inline PyTorch einsum in the script's `Indexer.forward` | `dsv4/kernels/indexer/*` package |
+| Compressor / KV cache | the script's own `Compressor` / `KVCache` classes | `dsv4/cache/*`, `dsv4/kernels/cache/*` |
+| Produces coherent output? | **Yes — this is what runs** | Unconfirmed; `dsv4/model/dsv4.py` has **0 in-repo importers** |
+
+**`single_shot_inference.py` is the live path.** It imports a *subset* of `dsv4/` primitives and reimplements the rest itself. Lineage P (`dsv4/model/dsv4.py` + the `dsv4/layers/{attention,ffn,embedding,norm}` nn.Modules + `dsv4/kernels/{indexer,router,cache}`) is either the vLLM/sglang integration surface **or dead**. You cannot tell from inside the repo.
+
+**→ Step 0 below resolves this. Do not archive anything in Lineage P until Step 0 is done.**
+
+---
+
+# PART 1 — Repo Cleanup
+
+## Step 0 — Establish the canonical entry points (do this FIRST, before moving anything in `dsv4/`)
+
+The cleanup is only safe once you know what's reachable. There are (at most) two roots:
+
+- **Standalone:** `single_shot_inference.py`.
+- **Serving:** whatever the modified vLLM at `/root/dsv4-nvfp4-workspace/vllm` imports from `dsv4`. Find it:
+
+```bash
+grep -rn "import dsv4\|from dsv4" /root/dsv4-nvfp4-workspace/vllm 2>/dev/null
+```
+
+If that comes back **empty**, then `dsv4/model/dsv4.py` and all of Lineage P are **not used by serving either** → they are archive candidates (Step 2). If it imports `dsv4.model.dsv4` (or anything in Lineage P), then Lineage P is live for serving and must be **kept**, not archived.
+
+### Build a reusable "is this file dead?" tool (the durable fix for the recreate problem)
+
+Drop this in `helpers/import_closure.py`. It computes the import closure from the entry points and prints every `dsv4/*.py` not reachable. Run it before archiving anything, and any time an agent claims a file is unused.
+
+```python
+# helpers/import_closure.py — list dsv4 modules NOT reachable from the entry points.
+# Usage: python helpers/import_closure.py  (run from repo root, PYTHONPATH=repo root)
+import ast, pathlib, sys
+ROOT = pathlib.Path(__file__).resolve().parent.parent
+ENTRYPOINTS = ["single_shot_inference.py"]  # + add the vLLM glue module if Step 0 found one
+
+def module_to_path(mod):
+    p = ROOT / (mod.replace(".", "/") + ".py")
+    if p.exists(): return p
+    p = ROOT / mod.replace(".", "/") / "__init__.py"
+    return p if p.exists() else None
+
+def imports_of(path):
+    tree = ast.parse(path.read_text())
+    out = set()
+    for n in ast.walk(tree):
+        if isinstance(n, ast.Import):
+            out |= {a.name for a in n.names}
+        elif isinstance(n, ast.ImportFrom) and n.module:
+            out.add(n.module)
+    return {m for m in out if m.startswith("dsv4")}
+
+seen, stack = set(), list(ENTRYPOINTS)
+stack = [ (ROOT / e) for e in stack ]
+while stack:
+    f = stack.pop()
+    if f in seen or f is None or not f.exists(): continue
+    seen.add(f)
+    for m in imports_of(f):
+        mp = module_to_path(m)
+        if mp and mp not in seen: stack.append(mp)
+
+all_py = set((ROOT / "dsv4").rglob("*.py"))
+dead = sorted(p.relative_to(ROOT) for p in all_py - seen if "__pycache__" not in str(p))
+print("REACHABLE:", len(seen), " | DEAD CANDIDATES:", len(dead))
+for d in dead: print("  ", d)
+```
+
+This is **the** anti-recreate safeguard. Wire it into the agent's pre-commit habit: *"before deleting/archiving a module, prove it's dead with `import_closure.py`; before creating a 'missing' module, prove it doesn't already exist with `grep -rn <basename> .`"*
+
+---
+
+## Step 1 — Root-level files
+
+Only `single_shot_inference.py` stays in root (plus standard project files). Verified: all the test/probe/dump scripts below have **0 inbound imports**, so moving them needs **no code changes** — they are run directly with `PYTHONPATH=<repo root>`, which still resolves their `from dsv4 ...` imports from any location. Their hardcoded `/root/nvidia-meeting/...` checkpoint paths are runtime data paths, unaffected by the move.
+
+| File | Action | Destination | Code changes needed |
+|---|---|---|---|
+| `single_shot_inference.py` | **keep** | root | — |
+| `README.md` | **keep** | root | (but see Part 2 — its package-structure section is stale) |
+| `pyproject.toml`, `Dockerfile`, `docker-compose.yml`, `build_and_run.sh`, `.gitignore`, `.dockerignore` | **keep** | root | — |
+| `PERFORMANCE_AUDIT.md` | move | `docs/` | none (doc) |
+| `test_se_dequant.py` | move | `tests/integration/` | **none** (0 importers) |
+| `test_se_gpu.py` | move | `tests/integration/` | **none** |
+| `test_se_l1_direct.py` | move | `tests/integration/` | **none** |
+| `test_se_multi_gpu.py` | move | `tests/integration/` | **none** |
+| `test_gemm_1group.py` | move | `tests/integration/` | **none** |
+| `test_quantize_gpu.py` | move | `tests/integration/` | **none** |
+| `hf_reference_test.py` | move | `tests/integration/` | **none** |
+| `probe_hf_indexer.py` | move | `helpers/` (new) | **none** |
+| `probe_indexer_shapes.py` | move | `helpers/` | **none** |
+| `probe_keys.py` | move | `helpers/` | **none** |
+| `probe_shapes.py` | move | `helpers/` | **none** |
+| `dump_checkpoint_keys.py` | move | `helpers/` | **none** |
+| `single_shot_PYTORCH_REFERENCE.py` | move | `dsv4/reference/` | **YES — 3 edits, see Step 3** |
+
+`mkdir -p helpers` (no `__init__.py` needed; these run as scripts). `tests/integration/` and `dsv4/reference/` already exist.
+
+> The `tests/integration/` items load the real checkpoint — keep them if they still pass, send them to `tests/archive/` if superseded. That's a judgment call for the human, not an auto-archive.
+
+---
+
+## Step 2 — `dsv4/` internals
+
+### 2a. `.cu` duplication — the loader only ever looks in `kernels/cuda/`
+
+`dsv4/kernels/cuda/loader.py` resolves every `.cu` **relative to `dsv4/kernels/cuda/`**, regardless of which Python file calls `get_cuda_module`. So any `.cu` sitting in a semantic subfolder (`indexer/`, etc.) is **never compiled** — it's dead. Confirmed dead duplicates:
+
+| Dead copy (never compiled) | Live copy (what actually compiles) | Status |
+|---|---|---|
+| `dsv4/kernels/indexer/indexer_score_topk.cu` (292 lines) | `dsv4/kernels/cuda/indexer_score_topk.cu` (166 lines) | **DIFFER — do not blind-delete** |
+| `dsv4/kernels/indexer/gather_kv.cu` (106 lines) | `dsv4/kernels/cuda/gather_kv.cu` (121 lines) | **DIFFER — do not blind-delete** |
+
+**Procedure (because they differ):** `diff` each pair. Decide which is the *intended* version. The subfolder copy may actually be a newer improvement that's silently dead because the loader can't reach it. If the subfolder copy is the better one, **copy it into `kernels/cuda/` first** (so the live path gets the fix), verify, *then* delete the subfolder copy. Do not assume "live == canonical."
+
+**Decision to make (human):** either (a) keep the flat convention — all `.cu` live in `kernels/cuda/`, delete subfolder `.cu` after reconciling — which matches the loader and needs no Python changes; or (b) teach `loader.py` to accept subdir-qualified source paths and move `.cu` into semantic folders. (a) is lower risk. Pick one and make `loader.py`'s docstring say which.
+
+### 2b. Dead-code / orphan modules (archive candidates, gated on Step 0)
+
+From the import-graph scan, these `dsv4/` modules have **0 in-repo importers**. Confirm with `import_closure.py` and the Step 0 vLLM check, then move to a new `dsv4/_archive/` (mirror the subpath) rather than deleting:
+
+- `dsv4/model/dsv4.py` ← **0 in-repo importers.** This is the "full model." If Step 0 shows vLLM imports it, it is LIVE — keep. Otherwise archive.
+- `dsv4/model/mtp.py`
+- `dsv4/layers/embedding.py`
+- `dsv4/kernels/indexer/csa_indexer.py` (the live indexer is inline in `single_shot_inference.py`; this is Lineage P)
+- `dsv4/kernels/router/nvfp4_fused_router_kernel.py`
+- `dsv4/ops/topk.py`, `dsv4/ops/topk_select.py`, `dsv4/ops/router.py`
+- `dsv4/loader/hf_checkpoint.py`
+- `dsv4/reference/attention.py`, `dsv4/reference/csa_attention.py` ← keep regardless; they're cheap oracles you run by hand for validation.
+
+**Imported by Lineage P only (not by `single_shot`):** `dsv4/model/{layer,layer_schedule}.py`, `dsv4/layers/{attention,ffn,norm}.py`, `dsv4/cache/*`, `dsv4/kernels/cache/*`, `dsv4/kernels/indexer/score_topk.py`, `dsv4/kernels/router/dense_router_decode.py`, `dsv4/ops/{rope.py,custom_ops.py}`. **Keep all of these if Step 0 says Lineage P is the serving path.** Archive only if Lineage P is confirmed dead.
+
+> Note the `ops` duplication for the human: `ops/rope.py` (Lineage P) vs `ops/rope_cuda.py` (live, used by `single_shot`); `ops/topk.py`/`topk_select.py` (orphan) vs the live topk inside `single_shot`. Don't merge these blindly — pick the canonical one per lineage decision.
+
+### 2c. `preload_all()` is dead and references a non-existent file
+
+`dsv4/kernels/cuda/loader.py:preload_all()` has **no callers** and asks for `compressor_reduce_quant.cu`, which **does not exist** (the file is `compressor_reduce.cu`). Either delete `preload_all()` or fix the filename — see Part 2 #1.
+
+---
+
+## Step 3 — Reference-update cheatsheet (the only moves that need code edits)
+
+Everything in Step 1 is zero-edit **except** `single_shot_PYTORCH_REFERENCE.py`, which is imported by 3 unit tests via a bare top-level import that only resolves because the file is in repo root.
+
+**Pre-move check:** open `single_shot_PYTORCH_REFERENCE.py` and confirm its own imports are absolute (`from dsv4. ...`) or stdlib. If it bare-imports any sibling root module, fix those first or the move breaks it.
+
+**Move:** `single_shot_PYTORCH_REFERENCE.py` → `dsv4/reference/single_shot_PYTORCH_REFERENCE.py`
+
+**Edit 1 — `tests/unit/test_layer_comparison.py:34`**
+```diff
+-    from single_shot_PYTORCH_REFERENCE import mHCBlock, load_weights, forward_layer, rmsnorm
++    from dsv4.reference.single_shot_PYTORCH_REFERENCE import mHCBlock, load_weights, forward_layer, rmsnorm
+```
+
+**Edit 2 — `tests/unit/test_mhc_comparison.py:75`**
+```diff
+-    from single_shot_PYTORCH_REFERENCE import mHCBlock, load_weights as ref_load_weights, forward_layer
++    from dsv4.reference.single_shot_PYTORCH_REFERENCE import mHCBlock, load_weights as ref_load_weights, forward_layer
+```
+
+**Edit 3 — `tests/unit/test_compressor_position_bias.py:38`** — this is a **comment** reference, not an import. Update the text only:
+```diff
+-    # --- PyTorch reference path (matches single_shot_PYTORCH_REFERENCE.py) ---
++    # --- PyTorch reference path (matches dsv4/reference/single_shot_PYTORCH_REFERENCE.py) ---
+```
+
+**Verify after the move:**
+```bash
+grep -rn "single_shot_PYTORCH_REFERENCE" . | grep -v "dsv4/reference/single_shot_PYTORCH_REFERENCE.py"
+# every remaining hit must be one of the three updated lines above
+```
+
+---
+
+# PART 2 — Comment / Doc Audit (code is the source of truth)
+
+These are **verified** mismatches where the prose describes a previous version of the code. Fix the prose to match the code. Listed highest-confidence first.
+
+### 1. `dsv4/kernels/cuda/loader.py` — `preload_all()` names a file that doesn't exist
+The code refers to `compressor_reduce_quant.cu`; the actual file is `compressor_reduce.cu`. The function also has no callers.
+- **Fix:** delete `preload_all()` (it's dead), **or** change `"compressor_reduce_quant.cu"` → `"compressor_reduce.cu"` and verify the module's pybind function name matches what callers expect.
+- Also re-check the module docstring's usage example (`mod.fused_amax_quantize_nvfp4(x, divisor)`) against the actual exported symbol in `fused_amax_quantize.cu`.
+
+### 2. `README.md` "Package structure" + `ROADMAP.md` reference attention files that don't exist
+The docs describe the attention kernel as `dsv4/kernels/attention/fmha.py` (the "592-line main production kernel") and `fmha_smem_acc.py`, and mention a `dsv4/kernels/decode/` directory. **None of these exist.** The real live attention path is:
+```
+production.py  →  fmha_multitile_op.py  →  fmha_multitile_capi.cu  →  fmha_6warp_tma_multirow_multitile.cuh
+```
+- **Fix:** regenerate the README "Package structure" block from the actual tree (`find dsv4 -type f | sort`), and purge `fmha.py` / `fmha_smem_acc.py` / `kernels/decode/` references from README and ROADMAP. Keep the *lessons* prose; correct the *file map*.
+
+### 3. `dsv4/kernels/attention/production.py` docstring contradicts the ROADMAP about the production path
+`production.py` (which `single_shot_inference.py` imports — i.e., the **live** attention entry) says, verbatim: *"No CuTeDSL runtime dependency. No Python KV merge."* But `README.md` / `ROADMAP.md` / the status docs describe **"Python KV merge ships today"** as the production path, and frame Priorities 1/2/4/8 around the CuTeDSL `fmha.py` + `epilogue_tma_store` kernel.
+- **Implication (flag to the human, don't silently rewrite):** the live attention path appears to have moved to the C-API multitile kernel (`fmha_multitile_*` + the `.cuh`), which would make the entire "D1/D1.5/Python KV merge" framing and several roadmap priorities **stale — planning fixes for a kernel you no longer run.** Confirm which kernel `dsv4_attention` actually dispatches, then reconcile: the code (`production.py` → multitile C-API) wins; rewrite the ROADMAP's "Current status / blockers" to match.
+
+### 4. `dsv4/kernels/indexer/score_topk.py` docstring has the wrong scoring formula
+Line ~43 writes `I[t,s] = Σ_h w_h[t,h] · ReLU(q_I[t,h] · K^IComp[s,h])` — the `[s,h]` implies a per-head key. The key is **shared across heads** (MQA, paper `c_I=128`). The sibling `csa_indexer.py` docstring and the live `single_shot` einsum both use the correct shared-key form.
+- **Fix:** `K^IComp[s,h]` → `K^IComp[s]`. (If Step 2b archives this module, fix-or-archive — either way don't leave the wrong formula to mislead a future resurrection.)
+
+---
+
+## A repeatable comment-audit method (because no one can eyeball 75k lines)
+
+I verified the four above by reading the live path. The rest of the audit should be **systematic, not heroic**. Run this on the live closure (from `import_closure.py`), not the whole repo, and prioritize:
+
+1. **Top-of-file docstrings and `# eq.` / formula comments** — highest mislead-risk. For each live module, read only the module docstring + any comment containing `eq`, `shape`, `→`, `FP4`/`FP8`/`BF16`, or a hardcoded number, and check it against the code immediately below.
+2. **Grep for known-stale tokens** and review each hit on the live path:
+   ```bash
+   grep -rn "Python KV merge\|fmha\.py\|fmha_smem_acc\|MLA\|split-KV\|TODO\|FIXME\|XXX\|for now\|Phase 1\|will swap\|deferred" dsv4/ single_shot_inference.py
+   ```
+   Each "for now / will swap / Phase 1" comment is a promise that may already be broken — verify against current code.
+3. **Dtype claims:** any comment asserting a tensor is `FP8`/`FP4`/`BF16`/`FP32` — confirm against the actual `.dtype` / cast in code. (The `KVCache` docstring in `single_shot_inference.py` is a good example of a *correct, valuable* one — FP8 nope + BF16 rope — so don't strip long comments reflexively; only fix the wrong ones.)
+4. **One rule for the agent going forward:** when you change code, the diff is not done until the surrounding comment/docstring describes the new code. Treat a stale comment as a build break.
+
+---
+
+## Suggested commit sequence
+
+1. `helpers/import_closure.py` + run Step 0 (record the vLLM finding in this file).
+2. Root file moves (Step 1) — zero-edit batch first, then the `single_shot_PYTORCH_REFERENCE.py` move + 3 edits (Step 3), with the grep verification.
+3. `.cu` dedup (Step 2a) — diff, reconcile into `cuda/`, delete dead subfolder copies.
+4. Lineage-P archive decision (Step 2b) — only after Step 0; move to `dsv4/_archive/`, never delete.
+5. Comment fixes #1–#4 (Part 2), then the grep-driven sweep.
+
+After each step: `grep -rn "<moved basename>" .` shows zero dangling refs, and `single_shot_inference.py` still generates coherent output.

archived_plans/CORRECTNESS_BACKLOG.md

@@ -0,0 +1,288 @@
+# CORRECTNESS BACKLOG — Production Pipeline Verification Results
+
+Everything in this file has been TESTED at production values on the B200.
+If you think something is broken, check here first — it might already be verified correct.
+Last updated: 2026-06-03 07:30 UTC
+
+---
+
+## 1. FMHA (Flash Multi-Head Attention)
+
+### Prefill FMHA — VERIFIED CORRECT
+- **Test**: `tests/unit/test_production_fmha_layer.py`
+- **Method**: Run 5 prefill tokens, compare production FMHA output vs PyTorch SDPA on the SAME KV, per layer
+- **Result**: cos >= 0.999993 for all 5 tested layers
+- **Production values**: HD=512, H=128, MQA (1 KV head), scale from config
+- **Status**: ✅ CORRECT — not a source of decode degeneration
+
+### Decode FMHA — VERIFIED CORRECT
+- **Test**: `tests/unit/test_decode_fmha_layer.py`
+- **Method**: Run prefill to populate KV cache, then compare production FMHA vs PyTorch SDPA during the FIRST decode step
+- **Result**: cos >= 0.999976 for all 5 tested layers
+- **Production values**: HD=512, H=128, mixed FP8/BF16 KV (B1 path), MQA
+- **Key insight**: The FMHA kernel is correct during BOTH prefill and decode. The mixed FP8/BF16 KV path (noPE in FP8, RoPE in BF16) works correctly.
+- **Status**: ✅ CORRECT — not a source of decode degeneration
+
+### B1 Mixed FP8 Decode Kernel — VERIFIED CORRECT
+- **Test**: `tests/unit/test_b1_mixed_fp8_fmha.py`
+- **7 test categories, ALL PASS** at production values (HD=512, H=128, N=128..2048)
+- Includes: quantize_q_fp8_split, gather_mixed, FMHA cosine, attention sinks, GQA, weight loading, batch sizes
+- **Bug fixed**: V matrix canonical layout swap (canon_idx args were swapped) — commit 4fe7f9d
+- **Status**: ✅ CORRECT
+
+### B1 Prefill Kernel (T>1) — VERIFIED CORRECT
+- **Bug fixed**: T-dimension strides were wrong for T>1
+  - q_nope_t_stride, q_scale_t_stride, q_rope_t_stride added to params + C API + Python
+  - For T=1: wrong stride is invisible. For T>1: reads from wrong head's data
+  - Commit 5417f65
+- **Result**: ALL 16 T>1 test configs pass (cos >= 0.999887)
+- **Status**: ✅ CORRECT
+
+---
+
+## 2. Compressor (CSA/HCA)
+
+### Compressor kv_norm — VERIFIED CORRECT
+- **kv_norm_weight loaded for ALL 61 layers** — values range 0.21-4.16 (most are 0.3-2.0)
+- The `apply_kv_norm_kernel` in `compressor_reduce.cu` IS being called after compression
+- kv_norm applies unweighted RMSNorm + learned weight: `output = input * inv_rms * norm_weight[c]`
+- After kv_norm, compressed KV should have magnitude ~0.3-2.0 (matches norm_weight range)
+- **Status**: ✅ CORRECT — kv_norm IS being applied, weights ARE loaded
+
+### Compressor Output — VERIFIED at production scale
+- CSA (ratio=4): compresses every 4 tokens, produces 1 compressed entry per block
+- HCA (ratio=128): compresses every 128 tokens — with only 10 prefill tokens, produces 0 entries
+- After 10 prefill tokens: CSA layers have n_comp=2, HCA layers have n_comp=0
+- **Status**: ✅ WORKING — produces reasonable compressed entries
+
+### Compressor CUDA kernels — VERIFIED
+- `compressor_reduce.cu`: CSA and HCA reduce kernels with token-level softmax + weighted sum + kv_norm
+- `csa_compress_reduce_kernel`: applies position bias, softmax over m=4 tokens, weighted sum, then kv_norm
+- `hca_compress_reduce_kernel`: same for m'=128 tokens (mean reduction for HCA)
+- Both call `apply_kv_norm_kernel` if `kv_norm_weight.numel() > 0`
+- **Status**: ✅ CORRECT
+
+---
+
+## 3. KV Cache & Gathering
+
+### Mixed FP8/BF16 KV Format — VERIFIED
+- noPE dims (448): stored as FP8 E4M3 + per-row float32 scale
+- RoPE dims (64): stored as BF16
+- `gather_mixed_selective()`: CSA top-k gather of compressed + SWA tail
+- `gather_mixed_all()`: HCA dense gather of all compressed + SWA tail
+- `gather_mixed_swa_only()`: for layers with ratio<=1 or no compression yet
+- `copy_comp_rows_kernel` in `fp8_attention_io.cu`: actual CUDA gather
+- **Status**: ✅ WORKING — correct dtypes, correct shapes
+
+### Causality — VERIFIED NO VIOLATIONS
+- **Test**: `test_part_a_decode_diagnostics.py` checks `future_leak` for all 61 layers
+- At decode step: no compressed position >= decode position
+- CSA top-k indices are clamped to [0, n_comp-1]
+- **Result**: `future_leak=no` for ALL 61 layers during decode
+- **Status**: ✅ CORRECT — no causality violations
+
+### KV Cache State After 10 Prefill Tokens
+- HCA layers (ratio=128): n_comp=0, swa_len=10, total_KV=10
+- CSA layers (ratio=4): n_comp=2, swa_len=10, total_KV=12
+- CSA attends to: 2 compressed + 11 SWA = 13 entries during decode (11 SWA = 10 from prefill + 1 from decode)
+- HCA attends to: 0 compressed + 11 SWA = 11 entries during decode
+- **Status**: ✅ CORRECT — expected behavior with 10 prefill tokens
+
+---
+
+## 4. mHC (Manifold-Constrained Hyper-Connections)
+
+### mHC Sinkhorn — VERIFIED
+- B_l is produced by Sinkhorn-Knopp with t_max=20 iterations
+- B_l col sums = 1.0000 (perfectly doubly stochastic)
+- B_l row sums range [0.93, 1.08] — not perfectly doubly stochastic but close
+  - This matches the PyTorch reference: eps after softmax shifts rows slightly
+- The Sinkhorn IS working correctly — the growth is inherent to mHC, not a kernel bug
+- **Status**: ✅ CORRECT — but causes residual growth (see below)
+
+### mHC Residual Growth — CONFIRMED as Root Cause of Decode Degeneration
+- **|X| grows from 0.21 to 860 across 61 layers during decode**
+- Growth pattern (decode step, 10 prefill tokens):
+  - L0-L20: |X| stays 0.2-2.5 (bounded)
+  - L21-L45: |X| grows 2.5-35 (gradual increase, C_l values growing)
+  - L46-L55: |X| grows 35-73 (accelerating)
+  - L56-L60: |X| grows 73-860 (exponential)
+- Key layers where growth spikes:
+  - L56 (CSA): 73 → 177 (C_l max=1.92)
+  - L58 (CSA): 151 → 209 (C_l max=1.60)
+  - L59 (HCA): 209 → 330 (C_l max=1.88)
+  - L60 (CSA): 330 → 860 (C_l max=1.73, |F_attn|=314, |F_ffn|=460)
+- **This is ARCHITECTURAL, not a kernel bug**: B_l preserves X (col sums=1.0), C_l adds F_out. Over 61 layers, |X| compounds.
+- The paper says 300-500 is expected. We see 860 with only 10 prefill tokens.
+- **The degenerate output ("capitalizing" loops) is caused by this residual growth compressing the logit range** — the model cannot distinguish between tokens when |X| is large.
+- **Status**: ❌ NOT A BUG — architectural property. Need model-level fix (residual clipping, C_l scaling, etc.)
+
+### mHC Dynamic Parameters — VERIFIED
+- A_l (pre-block mixing): values mostly near 1.0 (sigmoid saturated at 0 or 1)
+- C_l (post-block scaling): values grow from 0.02 at L0 to 1.9 at L60
+  - This growth in C_l is what amplifies F_out and drives |X| growth
+- B_l (post-block mixing): Sinkhorn working correctly (col sums=1.0)
+
+---
+
+## 5. Router
+
+### Hash Router (L0-L2) — VERIFIED
+- Mode: "hash" — deterministic per-token-ID LUT lookup
+- Uses `tid2eid` weight (shape [129280, 6], int64 → cast to int32)
+- `hash_router_dispatch` CUDA kernel loads and runs correctly
+- **Status**: ✅ CORRECT
+
+### Dense Router (L3+) — VERIFIED
+- Mode: "dense" — sqrt(softplus(X @ W_gate)) + e_bias, top-k selection
+- NVFP4 gate GEMM with runtime-quantized activation global scale
+- For layers where gate.weight is BF16 (no weight_scale in checkpoint): quantized to NVFP4 at runtime
+- `dense_router_dispatch` CUDA kernel with fused NVFP4 GEMM + activation_topk
+- **Status**: ✅ WORKING
+
+---
+
+## 6. MoE (Mixture of Experts)
+
+### Nvfp4MoE (Routed Experts) — VERIFIED
+- 384 routed experts, top-6 selection
+- SwiGLU activation with swiglu_limit=10.0
+- Fused SwiGLU NVFP4 GEMM kernel (7-warp specialization)
+- `_use_runtime_gsa = True` — activation global scale computed at runtime
+- |F_ffn| ranges 0.5-460 during decode (scales with |X|, expected)
+- **Status**: ✅ WORKING
+
+### Nvfp4SharedExpert — VERIFIED
+- Shared expert with SwiGLU activation
+- Fused SwiGLU NVFP4 GEMM kernel
+- `_use_runtime_gsa = True`
+- **Status**: ✅ WORKING
+
+---
+
+## 7. NVFP4 Quantization
+
+### Runtime Activation Global Scale (gsa) — VERIFIED
+- `gsa = max(|x|) / (6.0 * 448.0)` — prevents E4M3 block scale overflow
+- Applied to: Nvfp4Linear, Nvfp4GroupedLinear, Nvfp4MoE, Nvfp4SharedExpert, Router gate
+- Flag: `_use_runtime_gsa = True` on each module
+- Previous bug: checkpoint's `input_scale` caused E4M3 overflow (gsa=0.000251, x_norm=7956 → 32% magnitude loss per projection)
+- Fix: compute gsa from actual activation at runtime — commit 2b1fca6
+- **Status**: ✅ CORRECT
+
+### NVFP4 Weight Global Scale (gsb) — VERIFIED
+- `gsb = weight_scale_2` (NOT input_scale * ws2)
+- Previous bug: used input_scale as gsb base, causing 4000x magnitude reduction
+- Fix: gsb=weight_scale_2 for production GEMM
+- **Status**: ✅ CORRECT
+
+### FP8 KV Quantization — VERIFIED
+- noPE dims: FP8 E4M3 with per-row float32 scale
+- `quantize_fp8_e4m3_from_fp32()`: quantizes FP32 → FP8 with per-row amax
+- FP8 E4M3 max = 448, FP4 max = 6
+- **Status**: ✅ WORKING
+
+---
+
+## 8. RoPE
+
+### FP32 RoPE Cache — VERIFIED
+- BF16 cos/sin cache destroys cos²+sin²=1 (can be 0.996)
+- ~3% per-layer error accumulates to garbage over 61 layers
+- Fix: FP32 cache, BF16 round-trip error ~1.5% (expected BF16 quantization noise)
+- **Status**: ✅ CORRECT
+
+### Inverse RoPE — VERIFIED
+- Applied after FMHA output to remove positional encoding
+- Same FP32 cache as forward RoPE
+- **Status**: ✅ WORKING
+
+---
+
+## 9. Indexer (CSA)
+
+### B2 FP8 Indexer — VERIFIED
+- **Test**: `tests/unit/test_b2_indexer_fp8.py` — 5 test categories, ALL PASS
+- 100% overlap with FP32 reference at n_comp ≤ 1024
+- ~88% overlap at n_comp = 8192 (expected FP8 quantization noise)
+- **Bugs fixed**:
+  1. `tcgen05.ld.16x256b.x1` hangs on SM100 — replaced with `tcgen05.ld.32x32b.x8`
+  2. TMEM_COLS=128 too small for 128×128 MMA output — fixed to TMEM_COLS=512
+  3. TMEM offset for rows 32-63: NO offset needed (different warps see different row slices from same address)
+  4. Cross-warp accumulation race condition: per-warp score partitions, merged after __syncthreads()
+- **Status**: ✅ CORRECT
+
+---
+
+## 10. Production Pipeline — FULL 61-LAYER TEST
+
+### Numerical Stability — VERIFIED STABLE
+- **Test**: `tests/unit/test_part_a_decode_diagnostics.py` with `TEST_LAYERS=61`
+- 61 layers, 10 prefill tokens, 1 decode step, 8 GPUs
+- No NaN, No Inf, No causality violations
+- |X| bounded at 0.2-860 (see mHC section for growth details)
+- Compressor, FMHA, MoE, Router all working correctly together
+- **Status**: ✅ STABLE — no numerical instability
+
+### Per-Token |X| Growth During Prefill (10 tokens, 61 layers)
+- Token 0: 0.45 → 6,240 (warmup spike — first token always large)
+- Token 1: 0.18 → 255 (stabilizes but still grows at L55+)
+- Token 2: 0.16 → 320 (same pattern)
+- Token 9: 0.24 → 476 (representative prefill token)
+- The growth accelerates at L38 (CSA): |X| jumps from 16 → 724 at token 0
+
+### Decode Step |X| Growth (61 layers)
+- L0: |X|=0.21, |F_attn|=10, |F_ffn|=3.3, C_l=[0.0, 0.02]
+- L10: |X|=2.17, |F_attn|=10, |F_ffn|=0.9, C_l=[0.0, 0.07]
+- L20: |X|=2.41, |F_attn|=14, |F_ffn|=1.0, C_l=[0.0, 0.09]
+- L30: |X|=22.5, |F_attn|=17, |F_ffn|=1.3, C_l=[0.0, 0.51]
+- L40: |X|=41.5, |F_attn|=7, |F_ffn|=2.0, C_l=[0.0, 0.94]
+- L50: |X|=56.3, |F_attn|=9, |F_ffn|=2.1, C_l=[0.2, 1.33]
+- L55: |X|=73.0, |F_attn|=16, |F_ffn|=3.8, C_l=[0.0, 1.70]
+- L60: |X|=860, |F_attn|=314, |F_ffn|=460, C_l=[0.1, 1.73]
+
+### kv_norm_weight Values (all 61 layers, verified loaded)
+- L0-L20: 0.21-1.65 (growing gradually)
+- L21-L40: 0.45-2.16 (continued growth)
+- L41-L60: 0.47-4.16 (L54 has outlier at 4.16)
+- All loaded correctly, all shapes (512,), all on correct GPU
+
+---
+
+## 11. Test Infrastructure Notes
+
+### TEST_LAYERS must be set via ENV VAR, not CLI arg
+- `single_shot_inference.py` has its own `argparse` that intercepts CLI args
+- Passing `TEST_LAYERS=10` as a CLI arg to the test causes it to be parsed by single_shot's argparse instead
+- This causes `--max-tokens` to be set incorrectly, leading to pipeline blowup
+- **Correct usage**: `export TEST_LAYERS=10` (env var, read via `os.environ.get`)
+- Previous "blowup" reports (|X|=3.27e+16) were ALL caused by this test bug
+
+### Test Harness Usage
+- Python tests: `~/.openclaw/workspace/fire_b200_test tests/unit/test_foo.py`
+- CUDA tests: `~/.openclaw/workspace/fire_b200_cuda_test tests/unit/test_bar.cu`
+- NEVER run code directly on B200 — always use the harness
+- NEVER edit code on B200 — edit locally → commit → push → pull on B200 → test
+
+---
+
+## 12. Ruled-Out Root Causes for Decode Degeneration
+
+These have been TESTED and VERIFIED to NOT be the cause:
+
+1. ❌ FMHA kernel bug — cos=0.999993 (prefill), 0.999976 (decode)
+2. ❌ Compressor kv_norm missing — loaded and applied for all 61 layers
+3. ❌ Causality violation — no future_leak in any layer
+4. ❌ FP8 KV quantization error — reasonable scales and values
+5. ❌ Router bug — hash and dense routers both working
+6. ❌ MoE bug — experts produce correct output, |F_ffn| scales as expected
+7. ❌ NVFP4 quantization overflow — runtime gsa prevents E4M3 overflow
+8. ❌ RoPE error — FP32 cache, correct round-trip
+9. ❌ Numerical instability — no NaN, no Inf across 61 layers
+
+### Confirmed Root Cause: mHC Residual Growth
+- |X| grows to 860 at L60 during decode
+- This compresses the logit range → model cannot distinguish tokens → degenerate output
+- The growth is ARCHITECTURAL: B_l preserves X, C_l adds F_out, compounds over 61 layers
+- Not a kernel bug — requires model-level intervention to fix

archived_plans/DEGENERATION_TESTS.md

@@ -0,0 +1,107 @@
+# DSV4 Decode Degeneration — Two Decisive Tests (run BEFORE any kernel/model change)
+
+**Symptom:** coherent-ish then degenerate decode; loops on a content token ("capital"/"capitalizing"); at times wrong top-1 from step 0.
+
+## ⛔ HARD STOP — do not do any of these until both tests below are run and reported
+
+- **Do NOT modify any kernel.**
+- **Do NOT modify the mHC math.**
+- **Do NOT add residual clipping, `C_l` scaling, or any "tame the residual" change.**
+
+The `CORRECTNESS_BACKLOG.md` verdict — *"mHC residual growth (|X|→860) is the confirmed root cause"* — is **unproven**, and the proposed remedies are surgery on a *trained* model to mask a symptom. If the real cause is the prompt (likely) or a missing final norm, those changes corrupt the model and hide the actual bug.
+
+## Why the backlog does NOT rule this out
+
+Every verification in `CORRECTNESS_BACKLOG.md` is a **same-input cosine**: production kernel vs PyTorch reference, both fed the **identical hand-rolled prompt**. That proves the kernels match *each other*. It is **structurally blind** to a chat-template/prompt bug — feed both sides the same malformed prompt and every layer agrees at cos 0.9999 *while both produce garbage*. So "we ruled out everything" means "everything a same-input cosine can see." The prompt is outside that set. The backlog is **silent** on the two hypotheses below, not a refutation of them.
+
+---
+
+## TEST 1 — Chat-template token-ID diff (most likely the actual bug; run first)
+
+**Hypothesis:** the hand-rolled prompt is out-of-distribution for this reasoning model → degenerate / looping output. The current construction in `single_shot_inference.py` is roughly:
+
+```python
+input_ids = [bos, USER_TOKEN]                                   # USER_TOKEN = 128803
+input_ids += tokenizer.encode('\n\n' + PROMPT, add_special_tokens=False)
+input_ids.append(ASSISTANT_TOKEN)                               # ASSISTANT_TOKEN = 128804
+```
+
+This almost certainly does **not** match what the model was trained on (a reasoning model expects specific assistant-turn + `<think>` priming; THINK_START=128821, THINK_END=128822 exist for a reason).
+
+**Procedure**
+
+1. Print what we actually build:
+   ```python
+   print("hand_rolled ids:", input_ids)
+   print("hand_rolled str:", tokenizer.decode(input_ids))
+   ```
+2. Print the canonical template the tokenizer itself produces:
+   ```python
+   ref_ids = tokenizer.apply_chat_template(
+       [{"role": "user", "content": PROMPT}],
+       add_generation_prompt=True, tokenize=True,
+       # This is a reasoner. Check whether the template takes a thinking kwarg
+       # (e.g. enable_thinking=True / thinking=...). Try with and without.
+   )
+   print("template ids:", ref_ids)
+   print("template str:", tokenizer.apply_chat_template(
+       [{"role":"user","content":PROMPT}], add_generation_prompt=True, tokenize=False))
+   ```
+3. Also dump the raw source so we can read the special-token layout directly:
+   ```python
+   print(tokenizer.chat_template)         # or read tokenizer_config.json / chat_template.jinja
+   ```
+4. Diff `input_ids` vs `ref_ids`. Look specifically at: BOS handling, the user/assistant delimiter tokens, newline placement, and **the `<think>` priming after the assistant token**.
+
+**Decision**
+
+- **They differ (expected):** replace the hand-rolled construction with `apply_chat_template` output, then run a short greedy generation (`--temperature 0`, modest `--max-tokens`). If Paris returns as top-1 and the loop is gone → **this was the bug. Done.** Do not touch mHC.
+- **Identical but still degenerate:** the tokenizer template is faithful yet the model still loops → compare `chat_template.jinja` against the reference inference impl (`deepseek-ai/DeepSeek-V4-Pro/tree/main/inference`), and confirm the thinking-enabled variant is what's being applied. Then proceed to Test 2.
+
+> Note: the NVIDIA sglang run used `--reasoning-parser deepseek-v4` and `SGLANG_DEFAULT_THINKING=1`. The real format is not a bare `USER … ASSISTANT` sandwich — there is a thinking setup the hand-rolled path omits.
+
+---
+
+## TEST 2 — Falsify the mHC "root cause" (run before ANY mHC/residual change)
+
+**Claim under test (from the backlog):** *"|X|=860 compresses the logit range so the model can't distinguish tokens."*
+
+**Why it's suspect:** there is a final RMSNorm before the LM head, and RMSNorm is **scale-invariant** — it divides the magnitude out. So |X|=860 and |X|=8 should produce the *same* logits (modulo the learned norm weight). Also, the residual grows just as much during **prefill** (backlog's own numbers: |X| up to 476, ~6240 on token 0) yet prefill/first-token is correct — magnitude common to both phases cannot be what breaks *only* decode.
+
+**Procedure**
+
+1. **Confirm the final norm exists and is applied.** Trace the path from the last layer's residual `X` → final RMSNorm → `lm_head_lin(x_out)`. Print whether a final norm runs before the LM head.
+   - **If it is MISSING or not applied → STOP. That is the real bug.** The fix is to apply the final norm, *not* to clip the residual.
+2. **Falsification.** At the last decode layer, capture the residual at |X|≈860. Compute logits two ways through the *same* final-norm + LM-head path:
+   ```python
+   logits_A = lm_head(final_norm(X))            # X as-is, |X|≈860
+   logits_B = lm_head(final_norm(X / 100.0))    # scaled down
+   cos = F.cosine_similarity(logits_A.flatten().float(), logits_B.flatten().float(), dim=0)
+   print("argmax_A", logits_A.argmax().item(), "argmax_B", logits_B.argmax().item(), "cos", cos.item())
+   ```
+
+**Decision**
+
+- **argmax_A == argmax_B and cos ≈ 1.0 (expected):** mHC growth is **exonerated**. |X| magnitude is not the cause. Stop chasing mHC; the answer is in Test 1.
+- **They differ materially:** something downstream of the residual is magnitude-sensitive → the final norm is missing/broken/misapplied. **Fix the norm.** Still do not clip the residual.
+
+---
+
+## Test ordering
+
+1. **Test 1 first** — it's the most likely fix and is trivial. If it resolves the loop, you're done and mHC was never the problem.
+2. **Test 2 before touching mHC** — even if Test 1 isn't a full fix, prove (or correctly redirect) the mHC verdict before any model-level change. The only "fix" Test 2 can license is *applying a missing final norm*, never residual clipping.
+
+## Harness / workflow (from CORRECTNESS_BACKLOG §11)
+
+- Run via the harness: `~/.openclaw/workspace/fire_b200_test tests/unit/<test>.py`. Never run or edit directly on the B200.
+- Edit locally → commit → push → pull on B200 → test.
+- Set `TEST_LAYERS` as an **env var** (`export TEST_LAYERS=10`), never as a CLI arg — single_shot's argparse will eat it and corrupt `--max-tokens` (this caused the bogus |X|=3.27e16 "blowups").
+- Both tests above are quick: Test 1 needs no GPU (tokenizer only); Test 2 needs one decode pass with `TEST_LAYERS=61`.
+
+## Report back (paste these)
+
+- **Test 1:** `hand_rolled ids`, `template ids`, the diff, and the greedy top-1 token after switching to `apply_chat_template`.
+- **Test 2:** whether a final norm is applied before the LM head; `argmax_A`, `argmax_B`, `cos`.
+
+Until both are reported, the mHC verdict stays **unproven** and no kernel/model change is authorized.

archived_plans/FINAL_STRETCH.md

@@ -0,0 +1,96 @@
+# DSV4 Audit — Decode Repetition + Precision / Tensor-Core Plan
+
+# PART B — Precision / NVFP4 / tensor-core (WE ARE SKIPPING PART A FOR RIGHT NOW AND WILL REVISIT IT)
+
+Goal: native NVFP4 where the math allows, FP8_E4M3 where it doesn't, BF16/FP32 only where required. Validate each change with per-layer cosine vs `dsv4/reference` before trusting it.
+
+## B0 — What's already optimal: DO NOT "fix" the MoE
+`dsv4/layers/moe.py` already runs **native NVFP4**: expert weights and activations are `float4_e2m1fn_x2`, block scales are `float8_e4m3fn`. This matches the paper (routed experts in FP4). Leave it. The remaining wins are in **attention** and the **indexer**, not MoE.
+
+### P5 — Fused mHC pre_block + RMSNorm + NVFP4 quantize: ✅ DONE
+- `fused_mhc_rmsnorm_quantize.cu` — 2-kernel approach (mhc_rmsnorm_amax_gsa + mhc_rmsnorm_quantize_nvfp4)
+- **Integrated into `forward_layer`** for BOTH attn and ffn mHC paths (commit 0b6ca0d)
+- Unit test: cos=0.999 vs unfused, 0.995 vs true mHC+RMSNorm at T=1/8/128
+
+### P4 — Fused RMSNorm + NVFP4 quantize: ✅ DONE
+- `fused_rmsnorm_quantize.cu` — 2-kernel approach
+- gsa scalar fix in `Nvfp4Linear.run_from_quantized`
+
+### Stale Lock Fix: ✅ DONE (commit 845227c)
+
+## B1 — FP8_E4M3 FMHA: ✅ DONE
+
+**Implementation**: `dsv4/kernels/attention/fmha_mixed_fp8_decode.cuh` + C API + Python bridge.
+
+Storage-native DSV4 attention: noPE KV stays FP8_E4M3, RoPE KV stays BF16, no global FP8→BF16 dequant.
+
+### Unit Test Results (2026-06-03, `tests/unit/test_b1_mixed_fp8_fmha.py`)
+
+| Test | Status |
+|------|--------|
+| quantize_q_fp8_split | ✅ PASS (cos=0.9997) |
+| gather_mixed kernels | ✅ PASS |
+| FMHA cosine (N=128..2048, H=128) | ✅ PASS (cos=0.9999..0.9997) |
+| Attention sinks | ✅ PASS |
+| GQA/MQA (128 Q heads) | ✅ PASS |
+| Weight loading verification | ✅ PASS |
+| Batch sizes (B=1,2,4) | ✅ PASS |
+
+### Bugs Found and Fixed
+
+1. **V matrix canonical layout swap** (commit 4fe7f9d): `canon_idx_bf16_16x16(kk, dd)` was wrong — should be `canon_idx_bf16_16x16(dd, kk)`. The SMEM group structure was transposed vs the working TMA-loaded V in the multitile kernel. This caused cos=0.158 vs BF16 reference. After fix: cos=0.999972 at N=128.
+
+### Known Limitations
+- **Prefill batch size**: T=1..128 supported. For T>128, caller must split. T_BATCH=32 sub-batches used internally.
+- Specialized for DSV4 HD=512/NOPE=448/ROPE=64.
+
+### Bug Fix (2026-06-03)
+1. **CRITICAL: T-dimension strides were wrong for T>1** — the kernel used `q_nope_head_stride` (stride(1) = T*NOPE) for the T dimension, but the correct stride is `stride(2) = NOPE`. For T=1 this is invisible (qr=0 always), but for T>1 it reads garbage from adjacent heads' data. Fix: added explicit T-dimension strides (`q_nope_t_stride`, `q_scale_t_stride`, `q_rope_t_stride`) to params struct, C API, and Python wrapper. All 16 T>1 test configs now pass (cos >= 0.999887).
+
+## B2 — FP8 tensor-core indexer scoring: ✅ DONE
+
+**Implementation**: `dsv4/kernels/cuda/indexer_fp8_score_topk.cu`
+
+Native Blackwell FP8 GEMM via tcgen05 for CSA Lightning Indexer scoring. No PyTorch einsum fallback.
+
+### Unit Test Results (2026-06-03, `tests/unit/test_b2_indexer_fp8.py`)
+
+| Test | Status |
+|------|--------|
+| Score cosine vs FP32 reference (n_comp=128..8192) | ✅ PASS (100% overlap ≤1024, ~88% at 8192) |
+| Score distribution sanity | ✅ PASS |
+| Determinism | ✅ PASS |
+| Edge cases (n_comp < top_k, n_comp=1) | ✅ PASS |
+| Weight format verification | ✅ PASS |
+
+### Bugs Found and Fixed
+
+1. **Broken `16x256b.x1` TMEM read** — instruction was hanging. Root cause: the `16x256b.x1` PTX instruction either doesn't exist on SM100 or has different alignment requirements. **Fix**: use the proven `32x32b.x8` instruction from B1 FMHA.
+
+2. **TMEM_COLS too small** — TMEM_COLS=128 was insufficient for the 128×128 MMA output. The MMA writes ALL 128 rows, requiring 4 row-groups × 128 columns = 512 TMEM columns. **Fix**: TMEM_COLS=512.
+
+3. **Wrong TMEM offset for rows 32-63** — tried `tb + SK_TILE + col_base` and `tb + 16 + col_base`, both gave wrong results. **Root cause**: the `32x32b.x8` instruction maps different warps to different row slices from the SAME TMEM address. Warp 0 reads rows 0-31, warp 1 reads rows 32-63, all from `tb + col_base`. **Fix**: warps 0-1 both read from the same address, accumulate into separate SMEM partitions, then merge.
+
+4. **Cross-warp accumulation race condition** — initial attempt used shared `sLogits[c]` with first-warp-writes/second-warp-adds pattern, which was non-deterministic. **Fix**: per-warp score partitions (`sWarpScores[0..SK_TILE-1]` and `sWarpScores[SK_TILE..2*SK_TILE-1]`), merged after `__syncthreads()`.
+
+### Production Configuration
+- n_ih=64, ihd=128, top_k=1024
+- Warps 0-1: TMEM read + per-warp score accumulation
+- Warp 4: MMA (FP8 GEMM)
+- Per-thread local top-k (INDEXER_LOCAL_K=8) → block-level merge
+
+## B3 — Fused rmsnorm→quant for q_a_norm / kv_norm: ✅ DONE
+- `q_a_norm` → `q_b` path uses fused `rmsnorm_quantize_nvfp4` + `run_from_quantized`
+- `kv_norm` still uses unfused rmsnorm — requires FP8 FMHA (B1) to fully benefit
+
+## B4 — General "producer BF16 → consumer FP32" sweep: NOT STARTED
+
+## B5 — Residual-stream precision: NOT STARTED (low priority)
+
+---
+
+# PART D — Dangling TODOS
+
+  - Batched Prefill: ✅ DONE (T=1..128, mixed FP8/BF16 kernel, chunked for T>128)
+  - Prefill wired into single_shot_inference.py: ✅ DONE (chunked batched prefill replaces T=1 token-by-token)
+  - T>128 support: ✅ DONE (splits into multiple launches of ≤128 tokens each)

archived_plans/OLD_README_STUFF.md

@@ -0,0 +1,43 @@
+
+## Our kernel design choices
+
+### Attention kernel (FmhaKernel)
+
+**6-warp specialization.** Warps 0–3 handle softmax + correction + epilogue. Warp 4 is the MMA warp (QK + PV). Warp 5 is the TMA warp (Q/K/V loads, output store via pipeline).
+
+**P staging — two paths.**
+- **TMEM-P** (hd ≤ 64): P stored to TMEM via register bridge (FP32 backing + BF16 view). PV reads P from TMEM. Used at the small head dims where QK C-fragment and PV A-fragment TMEM layouts agree.
+- **SMEM-P** (hd > 64): P written to SMEM via coordinate-indexed store using `tTMEM_LOADcS` to map register indices to `(m, k)` then into `sP`'s subtile layout. PV reads P from SMEM with `OperandSource.SMEM`. Required because the QK ↔ PV TMEM layout disagreement at hd > 64 corrupts the round-trip.
+
+**Un-normalized O + LSE output.** The kernel emits raw `sum(P · V)` and `lse = ln(row_sum) + row_max · ln(2)`. External code (or the next kernel pass) divides. This composes — D5 merge, multi-tile rescale, and the inverse-RoPE → wo_a fuse all rely on it.
+
+**Per-head launch for multi-head.** Python loop dispatches the single-CTA kernel once per head. Multi-CTA grid using `flat_divide` + `tma_partition` is the next refactor; the path is unblocked once the correction-epilog rewrite lands.
+
+**Head-packed M dimension for decode.** Q reshaped to `(n_h * T, hd, 1)`, all heads' rows packed into the 128-row M tile. Per-row softmax. At Pro decode (T=1, n_h=128) the M tile fits exactly.
+
+**K-dim sub-tiling at hd > 256.** When `head_dim > 256` (MMA instruction K-dim limit), Q and K split into `n_k_sub_tiles = head_dim / 256` chunks along head_dim. QK accumulates in TMEM across sub-tiles (additive in logit space). The PV path uses `pv_n_tile = 128` for hd > 256 to keep sV+sC within the 232 KB SMEM budget.
+
+**Sink bias as logit modification.** D3 (SWA length mask), D4 (causal mask on SWA), and D5c (attention sink) all live in the same post-QK, pre-softmax in-register code. They read `tTMEM_LOADcS` to get `(m, k)` coordinates and modify `tTMEM_LOADrS` before the row-max reduction. The sink bias is added in the raw-logit domain as `attn_sink / scale_softmax`, then the existing `* scale_log2` multiply converts to log2 space.
+
+### MoE kernel (FusedSwiGLUScaledGroupedGemmKernel)
+
+**7-warp specialization.** Warps 0–3 epilogue (TMEM → registers → SMEM → GMEM with global scale, SwiGLU, clamp). Warp 4 MMA (`tcgen05.mma.block_scale` with SFA/SFB in TMEM). Warp 5 TMA load (A, B, SFA, SFB). Warp 6 scheduler (`MoEStaticPersistentTileScheduler`).
+
+**One-way TMEM → registers → SMEM → GMEM epilogue.** Uses `epilogue_tmem_copy_and_partition` + `epilogue_smem_copy_and_partition` (CUTLASS helpers, paired atoms). The SwiGLU + clamping math runs in registers between the t2r and r2s copies. No TMEM round-trip. This is the same pattern FMHA needs to adopt to fix the D1.5 blocker.
+
+**Subtile-level gate/up pairing.** With granularity-8 interleaved L1 weights and `epi_tile_n=8`, even subtiles are gate and odd subtiles are up. `silu_gate_buf` register tensor carries the SiLU result across the subtile-pair boundary.
+
+**`use_2cta_instrs` conditional** on `tokens_sum ≥ 256` and even `cluster_m`. Decode (small M) stays 1-CTA; prefill/batched gets 2-CTA UMMA with multicast B (1.7–1.9× throughput).
+
+### Heterogeneous KV cache
+
+- **State cache** per request: fixed-size block holding `(n_win SWA KV)` and `(uncompressed tail tokens awaiting compression)`. One block per request, lifetime managed by request scheduling.
+- **Classical paged cache** per request: variable blocks holding `(k1 CSA compressed entries, k2 HCA compressed entries)` per layer. `k1 = lcm(m, m') / m = 32`, `k2 = lcm(m, m') / m' = 1`. Block covers 128 original tokens.
+- Different layers can produce different KV cache sizes (CSA vs HCA vs SWA-only). The state cache + classical-pool split keeps PagedAttention-style alignment intact for the compressed pool.
+
+### NVFP4 throughout
+
+- **Weights**: NVFP4 (FP8 E4M3 scales, 16-element microblocks). Verified: `sf_dtype`, TMA element type, MMA kind (`mxf4nvf4`) all correct.
+- **Activations**: BF16 today, FP4 after NVFP4-1.x epilogue fusion lands.
+- **KV cache**: BF16 today; the FP8 (RoPE in BF16, NoPE in FP8) split per paper §2.3.4 is on the roadmap as NVFP4-2.
+- **Indexer keys**: stored FP4 in the cache today, but scored with a scalar CUDA-core kernel. Tensor-core FP4 scoring (paper §5.2.1) is a Stage F priority.

docs/B1_MIXED_FP8_FMHA.md

@@ -0,0 +1,39 @@
+# B1 Mixed FP8/BF16 FMHA — DONE ✅
+
+Implementation of storage-native DeepSeek-V4 attention that keeps KV in the paper format:
+- noPE KV: FP8_E4M3 bytes plus per-row FP32 scale
+- RoPE KV: BF16
+- Q noPE: quantized BF16 → FP8_E4M3 immediately before FMHA
+- Q RoPE: BF16
+
+The live `forward_attention` path gathers compressed rows and the SWA tail into mixed buffers and calls `dsv4_attention_mixed_fp8_decode`; it no longer dequantizes noPE KV into `gather_buf` before attention.
+
+## New files
+
+- `dsv4/kernels/cuda/fp8_attention_io.cu` — quantize_q_fp8_split, gather_mixed_{selective,all,swa_only}
+- `dsv4/kernels/attention/fmha_mixed_fp8_decode.cuh` — decode kernel, HD=512/NOPE=448/ROPE=64
+- `dsv4/kernels/attention/fmha_mixed_fp8_capi.cu` — C ABI launcher
+- `dsv4/kernels/attention/fmha_mixed_fp8_op.py` — Python ctypes/nvcc bridge
+
+## Unit Test
+
+`tests/unit/test_b1_mixed_fp8_fmha.py` — comprehensive test at production values (HD=512, H=128, N=128..2048):
+1. quantize_q_fp8_split round-trip: cos=0.9997
+2. gather_mixed kernels: exact copy for compressed, cos=0.9997 for SWA quantization
+3. FMHA decode cosine vs FP32 SDPA: cos=0.999972 (N=128) to cos=0.999923 (N=2048)
+4. Attention sink bias: verified effect on output
+5. GQA/MQA with 128 Q heads: verified output magnitudes
+6. Weight loading dtype/shape verification
+7. Batch sizes B=1,2,4
+
+## Bug Fix: V matrix canonical layout (commit 4fe7f9d)
+
+`canon_idx_bf16_16x16(kk, dd)` had arguments swapped. The correct call is `canon_idx_bf16_16x16(dd, kk)`.
+This produced cos=0.158 vs BF16 reference. After fix: cos=0.999972.
+
+## Known Limitations
+
+- **Decode only (T==1)**. The launcher hard-errors for prefill. Prefill runs one token at a time.
+- Specialized to DSV4 attention dimensions (HD=512/NOPE=448/ROPE=64).
+- noPE QK uses Blackwell FP8 tensor cores; RoPE QK and PV use BF16 tensor cores.
+- noPE V is dequantized only inside shared memory immediately before the PV BF16 tensor-core multiply. There is no global BF16 KV staging.

docs/PERFORMANCE_AUDIT.md

@@ -0,0 +1,291 @@
+# PERFORMANCE — v18 NVFP4-everywhere fusion landed
+
+**Current state (2026-06-02).** Part 1 (P0–P3) is **LANDED**. The fused
+SwiGLU kernel compiles and runs in production. The CUDA RoPE kernel
+passes cos=1.000000 vs PyTorch reference. The single_shot generates
+coherent English (". The capital of France is...") with the full fused
+kernel stack — no NaN, no crashes, 500+ tokens decoded.
+
+**What remains** is KV-cache dtype choices (Part 2) and higher-order
+fusion (P4–P6). The model now uses NVFP4 GEMM + fused SwiGLU + CUDA RoPE
+end-to-end. The KV cache is still BF16 — the next frontier.
+
+**Tag:** `v-p0p1p2p3-fused-swiglu-cuda-rope-20260602`
+
+**On TurboQuant — verdict first, reasoning below.** Don't use it for DSv4.
+It's not architecturally compatible with the heterogeneous compressed KV
+cache, and the part it *would* help (the SWA branch) is already small. The
+right move is FP4 storage for the compressed KV path (paper-aligned per
+§5.2.1), not vector-quantization codebooks. Full reasoning in Section 4.
+
+---
+
+# PART 1 — THE NVFP4-EVERYWHERE GAP (STATUS: ✅ LANDED)
+
+## P0 — Fused SwiGLU for MoE — ✅ LANDED
+
+**Was:** `set_fused_swiglu(True)` existed but was never called. 240+ BF16
+kernel launches per token wasted on unfused SiLU+clamp+deinterleave.
+
+**Fix (3 bugs in `fused_swiglu.py`):**
+1. `kernel()` signature missing `fp4_out`, `sf_out`, `l2_global_scale` params
+   → `TypeError: too many positional arguments` during `cute.compile()`
+   Fix: added Optional params with None defaults to kernel signature
+2. `cute.math.fmin`/`cute.math.fmax` don't exist in CuTe DSL
+   → Replaced with `cute.where()` for TensorSSA-compatible clamp
+3. Subtile loop used `vectorize=True` (default) — incompatible with `cute.where()`
+   → Changed to `cutlass.range(subtile_cnt, unroll=1)`
+
+**Result:** Fused kernel compiles and runs. MoE L1 GEMM + SwiGLU + clamp
+in a single kernel launch. ~240 BF16 launches eliminated per token.
+
+**Commits:** fca7242 (arg fix), 3a30f35 (cute.where), 5c746bb (unroll=1)
+
+## P1 — Fused SwiGLU for Shared Expert — ✅ LANDED
+
+**Was:** SE had no fused path. Same unfused gap as MoE but for 1-expert variant.
+
+**Fix:**
+1. `interleave_l1_weights(granularity=8)` → `granularity_bf16=8` (wrong kwarg)
+2. `_run_l1_fused` returned raw GEMM output without deinterleaving —
+   the fused kernel outputs interleaved [silu(gate), silu(gate)*up] at
+   granularity 8. Must deinterleave and extract up half (SwiGLU result).
+3. Added eager `warmup_fused_swiglu_compilation(1, ...)` for SE (1-group)
+
+**Result:** SE uses same fused kernel as MoE (num_groups=1). ~120 µs/token saved.
+
+**Commits:** 1726cb6 (granularity_bf16), f01d3f3 (SE deinterleave), 553275d (SE warmup)
+
+## P2 — Linear `.run()` per-call FP32 scale uploads — ✅ LANDED
+
+**Was:** `self._gsa_buf.fill_(self._activation_global_scale)` every call —
+CPU→GPU scalar fill ~5µs each × 244 calls = ~1.2ms/token.
+
+**Fix:** `_gsa_buf` set once during init or by GPU compute (`quantize_nvfp4_gpu_fused`).
+No per-call fill on the hot path.
+
+**Result:** Zero H2D scalar transfers on the hot path.
+
+## P3 — CUDA RoPE kernel — ✅ LANDED
+
+**Was:** `_apply_rope` used 5-6 PyTorch ops per call (slice, clone, multiply, add, cast).
+183 RoPE calls × 5 launches = ~915 launches/token.
+
+**Fix:** Raw CUDA kernel (`rope_cuda.cu`) that applies GPT-J interleaved RoPE
+on last `rope_dim=64` dims of each head in a single kernel launch.
+FP32 cos/sin cache, forward + inverse, in-place operation.
+
+**Test results:**
+- Forward RoPE: cos=1.000000 vs PyTorch reference
+- Inverse RoPE: cos=1.000000 vs PyTorch reference
+- Round-trip (forward+inverse): cos=0.999999
+- Multi-token (T=8): cos=1.000000
+
+**Files:** `dsv4/kernels/cuda/rope_cuda.cu`, `dsv4/ops/rope_cuda.py`
+
+**Result:** 183 RoPE calls × (5-1) = **732 launches eliminated per token**.
+
+---
+
+# Part 1 Summary
+
+| Item | Status | Launches saved/token | Key fix |
+|---|---|---|---|
+| **P0** | ✅ Landed | ~240 (MoE) | kernel() signature + cute.where + unroll=1 |
+| **P1** | ✅ Landed | ~120 (SE) | granularity_bf16 + deinterleave + warmup |
+| **P2** | ✅ Landed | ~244 (gsa fills) | Remove per-call fill_() |
+| **P3** | ✅ Landed | ~732 (RoPE) | Raw CUDA kernel, cos=1.000000 |
+| **Total** | | **~1336 launches/token** | |
+
+**Single-shot E2E verification:**
+- Model generates ". The capital of France is . capital izing ized..." (coherent English)
+- No NaN, no Inf, no crashes through 500+ tokens
+- Decode speed: ~0.53-0.56s/token
+- Repetition loop on capital/ized variants is a known residual growth issue (not a kernel bug)
+
+---
+
+# PART 2 — KV CACHE: WHAT'S ALREADY FP4-COMPATIBLE, WHAT ISN'T
+
+**Current state:** ALL KV cache tensors are BF16. No FP4, no FP8.
+
+| Stream | Stored as | Width | At 1M ctx | Quantizable? |
+|---|---|---|---|---|
+| **SWA** | `torch.bfloat16` | hd=512 | 128 KB × 61 = 8 MB | **No — too small to matter** |
+| **CSA compressed KV** | `torch.bfloat16` | hd=512 | ~7.5 GB | **Yes — FP4 strongly indicated** |
+| **HCA compressed KV** | `torch.bfloat16` | hd=512 | ~240 MB | **Yes — FP4 indicated** |
+| **CSA indexer keys** | `torch.bfloat16` | c_I=128 | ~2 GB | **Yes — FP4 paper-specified §5.2.1** |
+| **Gather buffer** | `torch.bfloat16` | hd=512 | transient | Will match compressed KV dtype |
+
+Total BF16 at 1M context: ~10 GB on 8×B200. Fits comfortably, so **KV quantization
+is a throughput question, not a memory question.**
+
+## Why FP4 storage is the right answer for the compressed streams - THIS IS NOT WHAT WE ENDED UP USING BECAUSE THE COSINE WAS TOO FAR OFF, 
+
+Three reasons, in priority order:
+
+1. **Paper-aligned.** §5.2.1 explicitly specifies the indexer QK path
+   runs entirely in FP4. The main compressed KV cache being FP4 is
+   consistent with the rest of the NVFP4 model — the cache is, after all,
+   just stored projections of NVFP4 weights × BF16 hidden states.
+
+2. **Bandwidth.** Decode is KV-read-bound at long context. Reading
+   FP4 instead of BF16 quarters the bytes-per-token loaded by FMHA.
+   At top_k=1024, hd=512, 30 CSA layers: that's `30 × 1024 × 512 × 1.5 bytes
+   saved = 23 MB/token saved`. Across batch=8 and millions of decode
+   steps, real money.
+
+3. **Kernel-native on Blackwell.** Loading FP4 → tcgen05.mma is a
+   first-class path with TMA + UMMA + the `mxf4nvf4` MMA kind. The
+   in-kernel dequant happens for free during the MMA. **The infrastructure
+   exists in the production FMHA kernel already** (per the
+   `epilogue_op` work and the `ENABLE_FP4_EPILOGUE` template param).
+
+## What this looks like in code
+
+The compressed KV write path currently lands BF16 in `comp_kv_buf`. The
+production sequence should be:
+
+1. Compressor produces BF16 output (still — the softmax compression needs
+   accumulation precision).
+2. Quantize-to-NVFP4 in the same kernel as the compression (epilogue
+   fusion), using the **same NVFP4 quant primitives the linears already
+   use** (`quantize_nvfp4_gpu_fused`).
+3. Store FP4 + per-block E4M3 scales in `comp_kv_buf` (which becomes a
+   FP4 buffer + scale buffer pair).
+4. FMHA reads FP4, dequants in-kernel via TMA + tcgen05's native FP4
+   path. No `__constant__` LUT needed — the hardware decodes E2M1.
+
+For the indexer keys this is the same pattern but the consumer is the
+indexer scoring kernel (the FP32 einsum today, the FP4 tensor-core scorer
+when E7 lands).
+
+### Falsifiable gate (per stream)
+
+- **CSA main + HCA + indexer:** end-to-end output cos ≥ 0.999 with FP4
+  storage vs BF16. KV cache memory at 8K context drops by ~3.5× (8 → 2.3
+  GB). FMHA-bound decode latency at 8K context drops measurably.
+- **Recall@k for indexer ≥ 99% vs FP32 oracle** (the bar from the prior
+  indexer-fix audit). Critical — FP4 must not corrupt top-k ranking.
+
+### THE ABOVE DID NOT WORK... WHY NOT NVFP4 (native Blackwell FP4)?
+    ─────────────────────────────────────
+    We *really* wanted to use NVFP4 (E2M1 + E4M3 block scales + FP32 global scale)
+    for compressed KV storage. Blackwell's native FP4→MMA path would have given us
+    3.5× memory savings and direct tensor-core consumption — the dream pipeline.
+    We tried. Hard. Three separate approaches:
+      1. Fused compressor_reduce_quant.cu — single-kernel compress→NVFP4. Bugs in
+         cross-warp block amax reduction and shared memory corruption (s_scratch
+         stomping adjacent variables). Best cos=0.703. Dead.
+      2. Proven two-kernel path (amax_gsa → quantize_from_buffer) using kv_quantize.cu's
+         compute_amax_gsa_fp32 + quantize_nvfp4_from_fp32. cos=0.995 on random data,
+         but that's the *quantize/dequant* round-trip in isolation. In the full pipeline,
+         the 4-bit precision on 448 non-RoPE dimensions accumulated error across 61 layers
+         of mHC — residual |X| already grows to 300-500, and NVFP4's 16-element block
+         quantization (4.5 bits effective) added ~0.5% per layer on top of that.
+      3. FP32 RoPE kernel (rope_fp32 in kv_quantize.cu) to avoid BF16 RoPE intermediate.
+         Had an indexing bug (cos=0.977 for M>1). Fixed but the real issue was NVFP4,
+         not RoPE.
+    The verdict: NVFP4's 4.5 effective bits per element is simply too coarse for
+    compressed KV values that get summed in attention softmax. FP8_E4M3's 5.3 effective
+    bits gives cos=0.9997 round-trip (vs NVFP4's 0.995) — that 0.4% difference compounds
+    fatally across 61 layers.
+
+
+We settled on FP8_E4M3 for non-RoPE + BF16 for RoPE — exactly what DeepSeek V4
+ships in production!!!!!!!! Not because we couldn't build the NVFP4 path (we did, it compiled
+and ran), but because the math didn't hold up. Sometimes 4 bits isn't enough.
+If Blackwell adds a finer-grained FP4 variant (8-element blocks, 6 effective bits),
+revisit this. The kernels exist. The quantize/dequant path is proven. The precision
+just isn't there yet for attention-sensitive KV values.
+
+---
+
+# PART 3 — OTHER FUSION WINS, RANKED BY EFFORT/IMPACT
+
+## P4 — Fuse RMSNorm into the next NVFP4 quantize
+
+Q/KV projection input is RMSNormed; RMSNorm is a separate launch. The
+NVFP4 quantize kernel already does an amax reduction per group — fusing
+RMSNorm (which is *also* an amax-style reduction followed by a scale)
+into the quantizer's input is a natural fit. Saves a launch + a BF16
+materialization of `(T, H)` per RMSNorm site (2 per layer = 122/token).
+
+**Effort:** S (kernel-side, but the quantizer already has the right shape).
+**Impact:** Medium. 122 launches/token, ~0.7 ms/token from launch overhead alone.
+
+## P5 — Fuse mHC pre_block + RMSNorm into a single op
+
+Same logic as P4 but for mHC. `attn_mhc.pre_block(X_l)` → `rmsnorm` is 3
+kernels back-to-back. Fusable. mHC already exposes a `_project_and_rms`
+half per prior audit notes — wire it through both halves of the layer.
+
+**Effort:** S. **Impact:** Medium. ~120 launches/token.
+
+## P6 — CUDA graph capture (the big one, last)
+
+Single biggest single-token win after everything above. Captures the entire
+decode step into a graph; replay eliminates **all** launch overhead.
+Probably worth 2–3× speedup at batch=1.
+
+Blockers in v17:
+1. `set_device()` boundaries in the layer pipeline (the `cuda.synchronize()`
+   at line 963) — graph capture spans devices via multi-graph or
+   per-device sub-graphs. Manageable but not free.
+2. Dynamic shape in `KVCache.add_compressed` — `self.n_comp` grows.
+   Fix: capture *one* graph per prefill chunk size, replay per
+   decoded token (which has fixed T=1 shape; the growing buffer is
+   a write into a pre-allocated tensor, capturable).
+3. Any conditional `if` on tensor data — debug prints, the assertion at
+   line 608. Strip from the capture path with a flag.
+
+**Effort:** L. **Impact:** Huge (the biggest remaining single win).
+**Sequence:** land after P0/P1/P2/P3 so the captured graph reflects the
+post-fusion structure.
+
+
+# PRIORITY ORDER (updated 2026-06-02)
+
+| # | Item | Effort | Win | Status |
+|---|---|---|---|---|
+| **P0** | Call `set_fused_swiglu(True)` on all MoEs | XS | ~240 launches/token | ✅ Done |
+| **P1** | Same for shared expert | S | ~120 launches/token | ✅ Done |
+| **P2** | Drop per-call `fill_()` in Nvfp4Linear | S | ~244 launches/token | ✅ Done |
+| **P3** | CUDA RoPE kernel (1 launch vs 5-6) | S | ~732 launches/token | ✅ Done |
+| **KV-1** | FP4 storage for CSA main compressed KV | M | Huge at long context | Next | ✅ Done |
+| **KV-2** | FP4 storage for HCA compressed KV | M | Same pattern as KV-1 | After KV-1 | ✅ Done |
+| **KV-3** | FP4 storage for indexer keys (pair with E7) | M | Throughput + paper compliance | After KV-2 |✅ Done |
+| **P4** | RMSNorm fused into next quantize | S | 122 launches/token | ✅ Done |
+| **P5** | mHC pre_block + RMSNorm fused | S | ~120 launches/token | ✅ Done (kernel, pending integration) |
+| **P6** | CUDA graph capture | L | **2–3× total** | Next |
+
+
+---
+
+# DOCTRINE
+
+1. **DSL wall → raw CUDA C++, not Python.** Applies to P3/P4/P5 (kernel-
+   side fusion work). The fused-SwiGLU kernel already exists as a model
+   for what these should look like — it's NVFP4 GEMM + arbitrary-op
+   epilogue in registers, fully Blackwell-native. P3's CUDA RoPE kernel
+   demonstrates the raw CUDA path works perfectly.
+
+2. **Raw CUDA ≠ scalar math.** Applies to KV-1/KV-2/KV-3. The FP4
+   storage path on the read side uses `tcgen05.mma`'s native E2M1 decode
+   — no scalar dequant, no `__constant__` LUT (which was only needed
+   for the indexer scoring CUDA-core path).
+
+3. **Print, don't guess.** Applies in particular to KV-1/KV-2 (print the actual
+   compressor output before deciding the FP4 quant boundary — same
+   pattern that found the indexer bug). Do not assume the compressor
+   emits a shape that matches the FP4 quant kernel; print and confirm.
+
+4. **Integration over exploration.** Do not write `Nvfp4MoE_v2`. Do not
+   write `KVCache_fp4_v2`. Edit the existing classes. KV-1/KV-2 are
+   2-tensor type changes plus the kernel-side read path.
+
+5. **Falsifiable gates.** Already listed per priority. Meta-gate: after
+   P0–P5 land, decode latency at 8K context should be **single-digit
+   ms**, not three-digit. If it isn't, something is still on the hot
+   path that shouldn't be, and the answer is "profile, don't guess
+   next."

dsv4/_archive/kernels/indexer/csa_indexer.py

@@ -4,9 +4,19 @@ Paper §2.3.1, eq. 13–17:
   c_Q = h_t · W_DQ    (shared with main queries)
   q^I_t = c_Q · W_IUQ  (low-rank indexer queries)
   w^I_t = h_t · W_w    (per-head weights)
-  I[t,s] = Σ_h w^I_t,h · ReLU(q^I_t,h · K^IComp[s])
+  I[t,s] = Σ_h w^I_t,h · ReLU(q^I_t,h · K^IComp[s])  (MQA: shared key K)
   Selected = TopK(I[t,:])
 
+Key layout: K^IComp[s] is shared across indexer heads (MQA, NOT per-head).
+The dot product is: q^I_t,h (per-head) · K^IComp[s] (shared).
+This matches the production Indexer.forward() einsum 'tnd,cd->tnc'.
+
+RoPE: Neither indexer queries nor keys have RoPE applied.
+The indexer is a lightweight scoring mechanism for block selection,
+not a full attention layer. If the HF reference applies RoPE to
+indexer keys, the stored FP4 keys would need it baked in at
+compression time. VERIFY THIS AGAINST THE REFERENCE BEFORE PRODUCTION.
+
 The indexer only exists in CSA layers. HCA and SWA layers don't have
 an indexer (they do dense attention).
 """
@@ -47,14 +57,22 @@ class CSAIndexer:
         # For now, use a simple torch linear; will swap to Nvfp4Linear
         # with FP4 output in Phase 2.
         if not hasattr(self, '_q_up_weight'):
-            # Lazy init — weights would be loaded from checkpoint
-            d_c = self.config.query_compression_dim
-            n_ih = self.config.indexer_num_heads
-            c_i = self.config.indexer_head_dim
-            self._q_up_weight = torch.randn(
-                d_c, n_ih * c_i, dtype=torch.bfloat16, device='cuda') * 0.02
-            self._w_head_weight = torch.randn(
-                self.config.hidden_size, n_ih, dtype=torch.bfloat16, device='cuda') * 0.02
+            # WARNING: USING RANDOM WEIGHTS — csa_indexer.py has NO weight loading.
+            # The production path uses the Indexer class in single_shot_inference.py
+            # which loads real weights from the checkpoint via Nvfp4Linear.
+            # This CSAIndexer class should NOT be used for production inference.
+            # If you see this message, you need to wire up checkpoint weight loading
+            # or use the production Indexer instead.
+            raise RuntimeError(
+                "CSAIndexer has no checkpoint weight loading. "
+                "Use the production Indexer class (single_shot_inference.py) instead, "
+                "or implement weight loading for CSAIndexer.")
+            # Old code (random weights — removed to prevent silent incorrect behavior):
+            # d_c = self.config.query_compression_dim
+            # n_ih = self.config.indexer_num_heads
+            # c_i = self.config.indexer_head_dim
+            # self._q_up_weight = torch.randn(d_c, n_ih * c_i, ...) * 0.02
+            # self._w_head_weight = torch.randn(hidden_size, n_ih, ...) * 0.02
 
         q_I = torch.nn.functional.linear(c_Q, self._q_up_weight.T)  # [T, n_ih * c_i] BF16
         w_h = torch.nn.functional.linear(h_t, self._w_head_weight.T).float()  # [T, n_ih] FP32

dsv4/_archive/kernels/indexer/score_topk.py

@@ -39,10 +39,14 @@ def run_indexer_score_topk(
 ) -> torch.Tensor:
     """Returns [T, top_k] int32 of selected compressed entry indices.
 
-    The kernel computes:
-      I[t,s] = Σ_h w_h[t,h] · ReLU(q_I[t,h] · K^IComp[s,h])
+    The kernel computes (MQA — shared key across indexer heads):
+      I[t,s] = Σ_h w_h[t,h] · ReLU(q_I[t,h] · K^IComp[s])
       topk_indices = argtopk(I[t,:], k=top_k)
 
+    Note: K^IComp[s] is shared across heads (MQA), NOT per-head K^IComp[s,h].
+    This matches the .cu kernel and the production Indexer.forward() einsum.
+    The paper (eq. 16) uses the shared-key form.
+
     q_I is passed as BF16 and dequantized to FP32 before the kernel.
     The indexer keys are stored FP4 in the cache and dequantized
     inside the kernel.
@@ -61,7 +65,9 @@ def run_indexer_score_topk(
     # Simplification: assume T == B for now (one token per request in decode).
     if valid_lens.shape[0] != T:
         # Prefill: T > B. We need to map tokens to requests.
-        # For now, broadcast the first request's valid_lens.
+        # WARNING: broadcasting request 0's valid_lens is WRONG for batched
+        # or multi-request prefill — it selects from wrong key ranges per token.
+        # This is only correct for single-request bring-up.
         # TODO: proper per-token valid_lens from request_ids mapping.
         valid_lens = valid_lens[:1].expand(T).contiguous()
 

dsv4/_archive/layers/grouped_linear.py

@@ -0,0 +1,368 @@
+"""CuTeDSL NVFP4 Grouped Linear for wo_a (o_proj first half).
+
+wo_a in DeepSeek V4 is a grouped matmul (bmm) with n_local_groups=8 groups.
+Each group: (tokens, heads_per_group * head_dim) × (heads_per_group * head_dim, o_lora_rank) → (tokens, o_lora_rank)
+
+The vLLM forward does this via DeepGEMM fp8_einsum with equation "bhr,hdr->bhd".
+We replace it with our CuTeDSL ScaledGroupedGemm using n_local_groups as num_experts,
+where every token goes to every "expert" (group).
+
+wo_a is loaded as BF16 from our NVFP4 checkpoint, then quantized to NVFP4 here.
+
+CUDA-graph-compatible: all buffers pre-allocated, no CPU-GPU syncs.
+"""
+
+import torch
+
+from dsv4.ops.quantize import (
+    quantize_activation_nvfp4,
+    quantize_weight_to_nvfp4,
+    quantize_nvfp4_gpu_fused,
+)
+from dsv4.ops.layouts import (
+    make_b_k_major,
+    assemble_scales_2d_side,
+    assemble_scales_3d_side,
+)
+from dsv4.ops.gemm_runner import (
+    run_nvfp4_grouped_gemm,
+)
+from dsv4.ops.layouts import (
+    ceil_div as cutedsl_ceil_div,
+    pad_and_swizzle_single,
+)
+from dsv4.ops.custom_ops import register_runner, nvfp4_linear_gemm
+
+
+class Nvfp4GroupedLinear:
+    """Grouped NVFP4 linear for wo_a (o-projection first half).
+
+    Handles the "bhr,hdr->bhd" einsum pattern:
+    - o: (tokens, n_local_heads, head_dim) → reshape to (tokens, n_local_groups, heads_per_group * head_dim)
+    - wo_a: (n_local_groups, heads_per_group * head_dim, o_lora_rank) → NVFP4 per group
+    - z: (tokens, n_local_groups, o_lora_rank)
+
+    Uses ScaledGroupedGemm with num_groups=n_local_groups.
+    Every token goes to every group (no routing).
+
+    CUDA-graph-compatible: all buffers pre-allocated, no CPU-GPU syncs.
+    """
+
+    def __init__(
+        self,
+        n_local_groups: int,
+        heads_per_group: int,
+        head_dim: int,
+        o_lora_rank: int,
+        max_num_tokens: int = 8192,
+        device: str = "cuda",
+    ):
+        self.n_local_groups = n_local_groups
+        self.heads_per_group = heads_per_group
+        self.head_dim = head_dim
+        self.o_lora_rank = o_lora_rank
+        self.max_num_tokens = max_num_tokens
+        self.device = device
+
+        # Per-group dimensions
+        self.group_in_features = heads_per_group * head_dim  # 8192
+        self.group_out_features = o_lora_rank  # 1536
+
+        # NVFP4 weight storage: lists of per-group tensors
+        self._weight_fp4 = None  # list of (K//2, N) float4_e2m1fn_x2
+        self._weight_sf = None   # list of (K//16, N) float8_e4m3fn
+        self._weight_gs = None   # list of float32
+
+        # Processed weights (set by finalize_weights)
+        self._mat_b = None
+        self._scale_b = None
+        self._gsb = None
+
+        # Activation global scale
+        self._activation_global_scale = 1.0 / (6.0 * 448.0)
+
+        # Pre-allocated buffers
+        self._padded_x_fp4_buf = None
+        self._gsa_buf = None
+        self._expert_offsets_buf = None
+        self._buffers_allocated = False
+
+    def set_bf16_weight(self, wo_a_bf16: torch.Tensor):
+        """Set wo_a weight from BF16 and quantize to NVFP4.
+
+        Args:
+            wo_a_bf16: (n_local_groups * o_lora_rank, heads_per_group * head_dim) BF16
+                       OR (n_local_groups, heads_per_group * head_dim, o_lora_rank) if from bmm
+        """
+        # Quantize each group separately
+        fp4_list = []
+        sf_list = []
+        gs_list = []
+
+        if wo_a_bf16.ndim == 3:
+            # bmm format: (n_local_groups, heads_per_group * head_dim, o_lora_rank)
+            for g in range(self.n_local_groups):
+                w_g = wo_a_bf16[g]  # (in_features, out_features)
+                w_fp4, w_sf, w_gs = quantize_weight_to_nvfp4(w_g)
+                # quantize_weight_to_nvfp4 returns (K//2, N) with K=in_features
+                # Our kernel expects (K_packed, N_packed) where K is the contraction dim
+                # For weight (in_features, out_features): K=in_features (contraction)
+                # quantize_weight_to_nvfp4 treats dim 0 as K, so result is (K//2, N) ✓
+                fp4_list.append(w_fp4)
+                sf_list.append(w_sf)
+                gs_list.append(w_gs)
+        else:
+            # Dense format: (n_local_groups * o_lora_rank, heads_per_group * head_dim)
+            # Split into per-group blocks
+            for g in range(self.n_local_groups):
+                start = g * self.o_lora_rank
+                end = start + self.o_lora_rank
+                w_g = wo_a_bf16[start:end, :]  # (o_lora_rank, in_features)
+                # NOTE: This is transposed — weight is (out, in) but quantize_weight_to_nvfp4
+                # expects (K, N) where K is the packed/contraction dim.
+                # For matmul X @ W^T, the contraction dim of W is dim 1 (in_features).
+                # So we need to transpose before quantizing.
+                w_g_t = w_g.T  # (in_features, o_lora_rank) = (K, N)
+                w_fp4, w_sf, w_gs = quantize_weight_to_nvfp4(w_g_t)
+                fp4_list.append(w_fp4)
+                sf_list.append(w_sf)
+                gs_list.append(w_gs)
+
+        self._weight_fp4 = fp4_list
+        self._weight_sf = sf_list
+        self._weight_gs = gs_list
+
+    def load_nvfp4_weight(self, weight, weight_scale, weight_scale_2=None, input_scale=None):
+        """Load NVFP4 weights directly from checkpoint — no dequant/re-quant.
+
+        The checkpoint stores weights in (out_features, in_features) layout:
+          weight: (n_groups * o_rank, group_in_features // 2) uint8
+          weight_scale: (n_groups * o_rank, group_in_features // 16) float8_e4m3fn
+          weight_scale_2: scalar or (n_groups * o_rank,) float
+          input_scale: scalar or (n_groups * o_rank,) float (unused for weight dequant)
+
+        Each group's chunk is (o_rank, K_packed) = (N, K_packed) in row-major.
+        Our GEMM expects (K_packed, N) per group, so we transpose each group.
+        Block scales follow the same transpose.
+
+        Args:
+            weight: (n_groups * o_rank, group_in_features // 2) uint8
+            weight_scale: (n_groups * o_rank, group_in_features // 16) float8_e4m3fn
+            weight_scale_2: scalar or per-row scale tensor (optional)
+            input_scale: scalar or per-row (unused — for activation quantization)
+        """
+        fp4_list = []
+        sf_list = []
+        gs_list = []
+
+        K_packed = self.group_in_features // 2
+        N = self.o_lora_rank
+        K_sf = self.group_in_features // 16  # block scale dim along K
+
+        for g in range(self.n_local_groups):
+            # Extract this group's weight: (o_rank, K_packed) = (N, K_packed)
+            start = g * N
+            end = start + N
+            w_g = weight[start:end]  # (N, K_packed) uint8
+            ws_g = weight_scale[start:end]  # (N, K_sf) float8_e4m3fn
+
+            # Transpose to (K_packed, N) — the layout quantize_weight_to_nvfp4 produces
+            w_g_t = w_g.view(torch.float4_e2m1fn_x2).permute(1, 0).contiguous()
+            ws_g_t = ws_g.permute(1, 0).contiguous()
+
+            fp4_list.append(w_g_t)
+            sf_list.append(ws_g_t)
+
+            # Global scale: weight_scale_2
+            if weight_scale_2 is not None:
+                if weight_scale_2.numel() == 1:
+                    gs_list.append(weight_scale_2.float().item())
+                else:
+                    # Per-row: take mean of this group's rows
+                    gs_list.append(weight_scale_2[start:end].float().mean().item())
+            else:
+                gs_list.append(1.0)
+
+        self._weight_fp4 = fp4_list
+        self._weight_sf = sf_list
+        self._weight_gs = gs_list
+
+    def finalize_weights(self):
+        """Process NVFP4 weights for CuTeDSL GEMM."""
+        if self._weight_fp4 is None:
+            raise RuntimeError("Call set_bf16_weight() before finalize_weights()")
+
+        self._mat_b = make_b_k_major(torch.stack(self._weight_fp4))  # (groups, K_packed, N_packed)
+        self._scale_b = assemble_scales_3d_side(self._weight_sf)
+        self._gsb = torch.tensor(self._weight_gs, dtype=torch.float32, device=self.device)
+
+        # Free raw weights
+        self._weight_fp4 = None
+        self._weight_sf = None
+        self._weight_gs = None
+
+    def _allocate_buffers(self):
+        """Pre-allocate buffers at max size for cudagraph compatibility."""
+        max_rows_per_group = cutedsl_ceil_div(self.max_num_tokens, 128) * 128
+        total_max_rows = max_rows_per_group * self.n_local_groups
+
+        self._padded_x_fp4_buf = torch.zeros(
+            total_max_rows, self.group_in_features // 2, dtype=torch.uint8, device=self.device
+        ).view(torch.float4_e2m1fn_x2)
+
+        self._gsa_buf = torch.zeros(self.n_local_groups, dtype=torch.float32, device=self.device)
+        self._expert_offsets_buf = torch.zeros(self.n_local_groups, dtype=torch.int32, device=self.device)
+        self._buffers_allocated = True
+
+    def _ensure_initialized(self):
+        if self._mat_b is None:
+            self.finalize_weights()
+        if not self._buffers_allocated:
+            self._allocate_buffers()
+
+    def _assemble_scales_single_group(self, x_sf):
+        """Assemble 2D-side activation scales for num_groups=1."""
+        num_rows, num_cols = x_sf.shape
+        padded_rows = cutedsl_ceil_div(num_rows, 128) * 128
+        padded_cols = cutedsl_ceil_div(num_cols, 4) * 4
+
+        buf = torch.zeros(padded_rows, padded_cols, dtype=torch.float16, device=x_sf.device).to(torch.float8_e4m3fn)
+        buf[:num_rows, :num_cols] = x_sf
+        swizzled_flat = pad_and_swizzle_single(buf)
+        return swizzled_flat.reshape(padded_rows, padded_cols)
+
+    def compute_activation_global_scale(self, o_sample: torch.Tensor):
+        """Compute activation global scale from a warmup forward.
+
+        Args:
+            o_sample: (tokens, n_local_heads, head_dim) BF16 attention output sample
+        """
+        self._ensure_initialized()
+        # Reshape to grouped format, then flatten to 2D for quantization
+        o_grouped = o_sample.reshape(-1, self.n_local_groups, self.group_in_features)
+        # We need a single gs for all groups — use the overall amax
+        from dsv4.ops.quantize import (
+            quantize_to_nvfp4,
+        )
+        o_flat = o_sample.reshape(-1, o_sample.shape[-1])  # (tokens, n_local_heads * head_dim) — not right
+        # Actually, for grouped GEMM, each group's activation is (tokens, group_in_features)
+        # The global scale should be computed per-group, but for simplicity use one scale
+        # based on the overall amax.
+        with torch.no_grad():
+            _, _, gs = quantize_to_nvfp4(o_grouped.reshape(-1, self.group_in_features))
+            self._activation_global_scale = gs
+
+    def run(self, o: torch.Tensor) -> torch.Tensor:
+        """Forward: BF16 attention output → NVFP4 grouped GEMM → BF16 z.
+
+        Args:
+            o: (num_tokens, n_local_heads, head_dim) BF16 — attention output
+               AFTER inverse RoPE has been applied
+
+        Returns:
+            z: (num_tokens, n_local_groups, o_lora_rank) BF16
+        """
+        if not hasattr(self, '_runner_id'):
+            self._runner_id = register_runner(self)
+        return nvfp4_linear_gemm(
+            o, self._runner_id, self.n_local_groups * self.o_lora_rank,
+        )
+
+    def _run_impl(self, o: torch.Tensor) -> torch.Tensor:
+        """Actual implementation.
+
+        Input o is (tokens, n_local_heads, head_dim).
+        We reshape to (tokens, n_local_groups, heads_per_group * head_dim),
+        then treat each group's (tokens, group_in_features) as one "expert"
+        in our grouped GEMM. All tokens go to all groups.
+
+        The grouped GEMM layout requires each group's tokens to be
+        contiguous at their correct offset:
+        - Group 0: rows [0, padded_T)
+        - Group 1: rows [padded_T, 2*padded_T)
+        - ...
+        - Group G: rows [(G-1)*padded_T, G*padded_T)
+        """
+        self._ensure_initialized()
+
+        num_tokens = o.shape[0]
+        padded_rows_per_group = cutedsl_ceil_div(num_tokens, 128) * 128
+
+        # Reshape: (tokens, n_local_heads, head_dim) → (tokens, n_local_groups, group_in_features)
+        o_grouped = o.reshape(num_tokens, self.n_local_groups, self.group_in_features)
+
+        # Permute to groups-first: (G, T, D)
+        o_grouped = o_grouped.permute(1, 0, 2)
+
+        # Flatten all groups into (G*T, D) for batched fused quantize — single kernel launch
+        o_flat = o_grouped.reshape(self.n_local_groups * num_tokens, self.group_in_features)
+
+        # Fused amax + quantize: zero CPU-GPU syncs.
+        # Computes gsa on GPU, quantizes to NVFP4, returns GPU tensor.
+        # Replaces the old path: .item() sync + Python quantize per group.
+        if getattr(self, '_use_runtime_gsa', False):
+            x_fp4_flat, x_sf_flat, gsa_gpu = quantize_nvfp4_gpu_fused(o_flat)
+            # gsa_gpu is (G*T,) — all rows share same amax (from max over full tensor)
+            # For the GEMM's global_scale_a, fill all group slots with the same gsa value
+            # Use GPU-only copy: no .item(), no CPU sync
+            self._gsa_buf[:1].copy_(gsa_gpu[:1])  # GPU→GPU scalar copy, no sync
+            # Broadcast to all groups (all get same gsa)
+            if self.n_local_groups > 1:
+                self._gsa_buf[1:].copy_(self._gsa_buf[:1].expand(self.n_local_groups - 1))
+        else:
+            self._gsa_buf.fill_(self._activation_global_scale)
+            x_fp4_flat, x_sf_flat = quantize_activation_nvfp4(
+                o_flat, self._activation_global_scale
+            )
+
+        # Reshape FP4 back to (G, T, D//2) and scatter into padded buffer
+        padded_x_fp4 = self._padded_x_fp4_buf
+        padded_x_fp4.view(torch.uint8).zero_()
+
+        x_fp4_grouped = x_fp4_flat.reshape(self.n_local_groups, num_tokens, self.group_in_features // 2)
+
+        for g in range(self.n_local_groups):
+            offset = g * padded_rows_per_group
+            padded_x_fp4.view(torch.uint8)[offset:offset + num_tokens] = x_fp4_grouped[g].view(torch.uint8)
+
+        # Reshape scales back to (G, T, D//16) and assemble
+        x_sf_grouped = x_sf_flat.reshape(self.n_local_groups, num_tokens, self.group_in_features // 16)
+        all_x_sf = [x_sf_grouped[g] for g in range(self.n_local_groups)]
+
+        # Assemble A-side scales for all groups
+        from dsv4.ops.layouts import (
+            assemble_scales_2d_side,
+        )
+        scale_a = assemble_scales_2d_side(all_x_sf)
+
+        # Expert offsets: cumulative [padded_T, 2*padded_T, ..., n_groups*padded_T]
+        expert_offsets = self._expert_offsets_buf
+        for g in range(self.n_local_groups):
+            expert_offsets[g] = (g + 1) * padded_rows_per_group
+
+        # Global scales — GPU-computed gsa already in _gsa_buf (no CPU sync)
+        gsa = self._gsa_buf
+
+        # Run grouped GEMM
+        out = run_nvfp4_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._mat_b,
+            scale_a=scale_a,
+            scale_b=self._scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=gsa,
+            global_scale_b=self._gsb,
+        )
+
+        # Extract real outputs and reshape
+        # GEMM output has the same layout as mat_a: groups-first with padding
+        z = torch.empty(num_tokens, self.n_local_groups, self.o_lora_rank,
+                        dtype=torch.bfloat16, device=o.device)
+        for g in range(self.n_local_groups):
+            offset = g * padded_rows_per_group
+            z[:, g, :] = out[offset:offset + num_tokens, :]
+
+        return z
+
+    def __call__(self, o: torch.Tensor) -> torch.Tensor:
+        return self.run(o)

dsv4/_archive/layers/linear.py

@@ -0,0 +1,267 @@
+"""CuTeDSL NVFP4 Linear (single GEMM)
+
+Generic NVFP4 GEMM runner for attention projections and any single
+linear layer. Uses ScaledGroupedGemmKernel with num_groups=1.
+
+CUDA-graph-compatible: all buffers pre-allocated, no CPU-GPU syncs.
+"""
+
+import torch
+
+from dsv4.ops.quantize import (
+    quantize_activation_nvfp4,
+    quantize_to_nvfp4,
+)
+from dsv4.ops.layouts import (
+    make_b_k_major,
+)
+from dsv4.ops.gemm_runner import (
+    run_nvfp4_grouped_gemm,
+)
+from dsv4.kernels.gemm.grouped import (
+    ceil_div as cutedsl_ceil_div,
+    pad_and_swizzle_single,
+)
+from dsv4.ops.custom_ops import register_runner, nvfp4_linear_gemm
+
+
+class Nvfp4Linear:
+    """Single NVFP4 GEMM using CuTeDSL (num_groups=1).
+
+    Handles any (K, N) weight matrix in NVFP4 format.
+    Simple: quantize activation → GEMM → BF16 output.
+    No SiLU, no fusion, no routing.
+
+    CUDA-graph-compatible: all buffers pre-allocated, no CPU-GPU syncs.
+    """
+
+    def __init__(
+        self,
+        in_features: int,
+        out_features: int,
+        max_num_tokens: int = 8192,
+        device: str = "cuda",
+    ):
+        self.in_features = in_features
+        self.out_features = out_features
+        self.max_num_tokens = max_num_tokens
+        self.device = device
+
+        # Weights (set after construction, then call finalize_weights)
+        self.fp4 = None  # list of 1 tensor
+        self.sf = None   # list of 1 tensor
+        self.gs = None   # list of 1 float
+        self.ws2 = None  # list of 1 tensor — weight_scale_2 (scalar, folded into global_scale_b)
+
+        # Processed weights
+        self._mat_b = None
+        self._scale_b = None
+        self._gsb = None
+
+        # Activation global scale
+        self._activation_global_scale = 1.0 / (6.0 * 448.0)
+
+        # Pre-allocated buffers
+        self._padded_x_fp4_buf = None
+        self._expert_offsets_buf = None
+        self._gsa_buf = None
+        self._buffers_allocated = False
+
+    def finalize_weights(self):
+        """Process weights for CuTeDSL GEMM."""
+        # Convert uint8 checkpoint weights to float4_e2m1fn_x2 view
+        fp4_view = [w.view(torch.float4_e2m1fn_x2) if w.dtype == torch.uint8 else w for w in self.fp4]
+        # Checkpoint weight is (out_features//2, in_features//2) = (N_packed, K_packed)
+        # make_b_k_major expects (E, K_packed, N_packed), so we need to permute
+        stacked = torch.stack(fp4_view).permute(0, 2, 1).contiguous()  # (1, K_packed, N_packed)
+        self._mat_b = make_b_k_major(stacked)
+        # Checkpoint scale is (N_packed, K_sf) — already in the right row order for the
+        # kernel's swizzle. Use assemble_raw_scales_2d3d_3d_side (no transpose),
+        # NOT assemble_scales_3d_side (which transposes K_sf↔N).
+        from dsv4.ops.layouts import assemble_raw_scales_2d3d_3d_side
+        self._scale_b = assemble_raw_scales_2d3d_3d_side(self.sf)
+        self._gsb = torch.tensor(self.gs, dtype=torch.float32, device=self.device)
+
+        # Fold weight_scale_2 into global_scale_b
+        # Dequant formula: w = lut[w_packed] * weight_scale * weight_scale_2
+        # Production GEMM: y = (x * scale_a * gsa) @ (w * scale_b * gsb)
+        # So gsb = input_scale * weight_scale_2
+        if self.ws2 is not None and len(self.ws2) > 0 and self.ws2[0] is not None:
+            ws2_val = self.ws2[0].float().item()
+            self._gsb = self._gsb * ws2_val
+
+        # Free raw weights
+        self.fp4 = None
+        self.sf = None
+        self.gs = None
+        self.ws2 = None
+
+        # Eagerly JIT-compile the GEMM kernel for this (K, N) shape.
+        # Uses num_groups=1 since this is a single linear layer.
+        K_packed = self.in_features // 2
+        N_packed = self.out_features // 2
+        # warmup_compilation(1, K_packed, N_packed, self.device)  # Lazy compile on first real forward
+
+    def _ensure_buffer_size(self, num_tokens: int):
+        """Ensure the padded buffer is large enough for num_tokens."""
+        needed_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+        if self._padded_x_fp4_buf is not None and self._padded_x_fp4_buf.shape[0] >= needed_rows:
+            return  # Already big enough
+
+        self._padded_x_fp4_buf = torch.zeros(
+            needed_rows, self.in_features // 2, dtype=torch.uint8, device=self.device
+        ).view(torch.float4_e2m1fn_x2)
+
+        self._expert_offsets_buf = torch.zeros(1, dtype=torch.int32, device=self.device)
+        self._gsa_buf = torch.full((1,), self._activation_global_scale, dtype=torch.float32, device=self.device)
+
+    def _ensure_initialized(self):
+        if self._mat_b is None:
+            self.finalize_weights()
+
+    def _assemble_scales_single_group(self, x_sf):
+        """Assemble 2D-side activation scales for num_groups=1."""
+        num_rows, num_cols = x_sf.shape
+        padded_rows = cutedsl_ceil_div(num_rows, 128) * 128
+        padded_cols = cutedsl_ceil_div(num_cols, 4) * 4
+
+        buf = torch.zeros(padded_rows, padded_cols, dtype=torch.float16, device=x_sf.device).to(torch.float8_e4m3fn)
+        buf[:num_rows, :num_cols] = x_sf
+        swizzled_flat = pad_and_swizzle_single(buf)
+        return swizzled_flat.reshape(padded_rows, padded_cols)
+
+    def compute_activation_global_scale(self, hidden_states_sample):
+        """Compute activation global scale from a warmup forward."""
+        self._ensure_initialized()
+        with torch.no_grad():
+            _, _, gs = quantize_to_nvfp4(hidden_states_sample)
+            self._activation_global_scale = gs
+
+
+    def run(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        """Forward: BF16 input → NVFP4 GEMM → BF16 output.
+
+        Uses torch.library.custom_op (nvfp4::linear_gemm) so torch.compile
+        treats this as an opaque op. The custom op calls _run_impl internally.
+        """
+        if not hasattr(self, '_runner_id'):
+            self._runner_id = register_runner(self)
+        return nvfp4_linear_gemm(
+            hidden_states, self._runner_id, self.out_features,
+        )
+
+    def _run_impl(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        """Actual implementation — called via custom autograd to be torch.compile-safe."""
+        self._ensure_initialized()
+
+        num_tokens = hidden_states.shape[0]
+        padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+
+        # Ensure buffer is large enough
+        self._ensure_buffer_size(num_tokens)
+
+        # Fused amax + quantize: single kernel launch, zero CPU-GPU syncs.
+        # Computes amax on GPU → derives gsa → quantizes to NVFP4.
+        # gsa written to GPU buffer for downstream GEMM global_scale_a.
+        #
+        # This replaces the two-step path:
+        #   compute_amax_gsa_gpu(hidden_states) → .item() sync
+        #   quantize_nvfp4_gpu(hidden_states, gsa_float) → another kernel launch
+        #
+        # Old path: ~2 kernel launches + 1 .item() sync per projection.
+        # New path: 1 kernel launch + 0 .item() syncs per projection.
+        # Total across 61 layers: ~486 .item() syncs eliminated.
+        if getattr(self, '_use_runtime_gsa', False):
+            from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+            x_fp4, x_sf, gsa_gpu = quantize_nvfp4_gpu_fused(hidden_states)
+            self._gsa_buf.copy_(gsa_gpu[:1].reshape(1))  # GPU → GPU, no sync
+        else:
+            # P2 FIX: No per-call fill_(). The _gsa_buf already has the correct
+            # value — set either during initialization (via _ensure_buffer_size)
+            # or by the first GPU compute when _use_runtime_gsa was True.
+            # Old path: self._gsa_buf.fill_(self._activation_global_scale)
+            #   — H2D transfer every call (~5µs each × 244 calls = ~1.2ms/token).
+            # New path: zero H2D transfers on the hot path.
+            from dsv4.ops.quantize import quantize_nvfp4_gpu
+            x_fp4, x_sf = quantize_nvfp4_gpu(hidden_states, self._activation_global_scale)
+
+        # Scatter x_fp4 into padded buffer
+        padded_x_fp4 = self._padded_x_fp4_buf
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[:x_fp4.shape[0]] = x_fp4.view(torch.uint8)
+
+        # Assemble A-side scales
+        scale_a = self._assemble_scales_single_group(x_sf)
+
+        # Expert offsets: [padded_rows] for 1 group
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.fill_(padded_rows)
+
+        # Global scales — GPU-computed gsa already in _gsa_buf (no CPU sync)
+        gsa = self._gsa_buf
+
+        # Run GEMM
+        out = run_nvfp4_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._mat_b,
+            scale_a=scale_a,
+            scale_b=self._scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=gsa,
+            global_scale_b=self._gsb,
+        )
+
+        return out[:num_tokens]
+
+    def run_from_quantized(self, quant: 'QuantizedActivation') -> torch.Tensor:
+        """Run GEMM with pre-quantized activation (skip quantize step).
+        
+        Used when the input has already been quantized by a fused
+        RMSNorm+quantize kernel. Saves 2 kernel launches per call.
+        
+        Args:
+            quant: QuantizedActivation with x_fp4, x_sf, gsa
+        """
+        from dsv4.ops.quantize import QuantizedActivation
+        assert isinstance(quant, QuantizedActivation)
+        
+        self._ensure_initialized()
+        num_tokens = quant.num_tokens
+        padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+        self._ensure_buffer_size(num_tokens)
+
+        # Scatter pre-quantized x_fp4 into padded buffer
+        padded_x_fp4 = self._padded_x_fp4_buf
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[:quant.x_fp4.shape[0]] = quant.x_fp4.view(torch.uint8)
+
+        # Assemble A-side scales from pre-quantized sf
+        scale_a = self._assemble_scales_single_group(quant.x_sf)
+
+        # Expert offsets
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.fill_(padded_rows)
+
+        # Global scales — use the per-row gsa from the fused kernel
+        # Reshape to (1,) if scalar, or use per-row (M,) broadcast
+        gsa = quant.gsa[:1].reshape(1) if quant.gsa.shape[0] == 1 else quant.gsa[:num_tokens]
+        if gsa.shape != self._gsa_buf.shape:
+            self._gsa_buf = gsa.contiguous()
+        else:
+            self._gsa_buf.copy_(gsa)
+
+        # Run GEMM
+        out = run_nvfp4_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._mat_b,
+            scale_a=scale_a,
+            scale_b=self._scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=self._gsa_buf,
+            global_scale_b=self._gsb,
+        )
+
+        return out[:num_tokens]
+
+    def __call__(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        return self.run(hidden_states)

dsv4/_archive/layers/mhc.py

@@ -0,0 +1,549 @@
+"""
+mHC (Manifold-Constrained Hyper-Connections) — Inference Layer.
+
+Implements Section 2.2 of the DeepSeek-V4 paper for the forward pass only.
+
+Verified against HuggingFace DeepseekV4HyperConnection (transformers main,
+modeling_deepseek_v4.py). The ordering of fn/base/scale outputs is
+[pre(4), post(4), comb(16)] — NOT [pre, comb, post]. The comb matrix is
+consumed TRANSPOSED in post_block. Sinkhorn starts from softmax (not exp).
+pre (A_l) has an hc_eps additive guard.
+
+---------------------------------------------------------------------
+V4-Pro reference dimensions (Section 4.2.1)
+---------------------------------------------------------------------
+  d      = 7168   hidden dim
+  n_hc   = 4      hyper-connection expansion factor
+  N_proj = 24     fused output of W_pre(4) + W_post(4) + W_comb(16)
+  K_proj = 4*7168 = 28672  = n_hc * d  (flattened residual)
+  t_max  = 20     Sinkhorn iterations
+
+---------------------------------------------------------------------
+Checkpoint layout (fn / base / scale)
+---------------------------------------------------------------------
+  fn:   (24, 28672) — rows ordered [pre(4), post(4), comb(16)]
+  base: (24,)       — ordered [pre(4), post(4), comb(16)]
+  scale: (3,)       — [alpha_pre, alpha_post, alpha_comb]
+
+  This matches the HuggingFace split:
+    pre_w, post_w, comb_w = F.linear(flat, fn).split([4, 4, 16])
+    pre_b, post_b, comb_b = base.split([4, 4, 16])
+    pre_scale, post_scale, comb_scale = scale.unbind(0)
+
+---------------------------------------------------------------------
+Kernel dependency
+---------------------------------------------------------------------
+tf32_hc_prenorm_gemm  (DeepGEMM, SM90/SM100)
+  a:       (T, K) BF16           — flattened residual X_flat
+  b:       (N, K) FP32           — stacked weight [W_pre; W_post; W_comb]
+  d:       (S, T, N) or (T, N) FP32  — raw projection outputs (pre-normalised)
+  sqr_sum: (S, T)  or (T,)  FP32    — Σ a²  per token (for RMSNorm denominator)
+  num_splits = S (16 recommended for K=28672)
+
+After the call:
+  d       = d.sum(0)         → (T, N)
+  sqr_sum = sqr_sum.sum(0)   → (T,)
+  rms_scale = sqrt(K / (sqr_sum + eps))
+  d_norm  = d * rms_scale[:,None]   — equivalent to RMSNorm(X_flat) @ W_stacked
+"""
+
+from __future__ import annotations
+
+import math
+from dataclasses import dataclass
+from typing import Optional, Tuple
+
+import torch
+import torch.nn.functional as F
+
+
+# ---------------------------------------------------------------------------
+# Try importing DeepGEMM; fall back to plain BF16 matmul if unavailable.
+# ---------------------------------------------------------------------------
+try:
+    import deep_gemm
+    _HAS_DEEP_GEMM = True
+except ImportError:
+    _HAS_DEEP_GEMM = False
+
+
+NUM_SPLITS  = 16   # K-split count for tf32_hc_prenorm_gemm numerical stability
+EPS_RMSN    = 1e-6
+HC_EPS      = 1e-6   # eps guard on pre (A_l) and Sinkhorn, matching HF reference
+
+
+# ---------------------------------------------------------------------------
+# Sinkhorn-Knopp projection (T batched 4×4 matrices)
+# ---------------------------------------------------------------------------
+
+def sinkhorn_knopp(
+    logits: torch.Tensor,   # (T, n, n)  raw logits (NOT exp'd)
+    t_max: int = 20,
+    eps: float = HC_EPS,
+) -> torch.Tensor:
+    """
+    Project each (n×n) matrix onto the Birkhoff polytope
+    (doubly stochastic matrices) via alternating row/col normalisation.
+
+    Matches HuggingFace DeepseekV4HyperConnection.forward:
+      1. softmax along last dim (row-normalize the logits)
+      2. add eps
+      3. column-normalize
+      4. (t_max - 1) alternating row/col normalizations
+    
+    NO PYTHON FALLBACK. If the CUDA kernel fails, the pipeline dies.
+    The kernel MUST compile and run correctly. Period.
+    """
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("mhc_sinkhorn", ["mhc_sinkhorn.cu"])
+    return mod.mhc_sinkhorn(logits.float(), t_max, eps)
+
+
+# ---------------------------------------------------------------------------
+# Context carried between pre_block and post_block
+# ---------------------------------------------------------------------------
+
+@dataclass
+class mHCContext:
+    """Holds the per-token mixing matrices computed in pre_block."""
+    B_l: torch.Tensor   # (T, n_hc, n_hc)  doubly stochastic residual transform
+    C_l: torch.Tensor   # (T, n_hc)         output mapping  (2*sigmoid)
+
+
+# ---------------------------------------------------------------------------
+# mHC layer
+# ---------------------------------------------------------------------------
+
+class mHCLayer:
+    """
+    Wraps one transformer sub-layer (attention *or* MoE) with the mHC
+    residual update.
+
+    Typical call pattern per layer:
+
+        x_in, ctx = mhc.pre_block(X_l)
+        F_out      = transformer_sublayer(x_in)         # (T, d)
+        X_next     = mhc.post_block(X_l, F_out, ctx)
+
+    where X_l has shape (T, n_hc, d) — the expanded residual state.
+    The first call at layer 0 should use X_0 initialised via `init_state`.
+    """
+
+    def __init__(
+        self,
+        hidden_dim:  int = 7168,
+        n_hc:        int = 4,
+        t_max_sinkhorn: int = 20,
+        device: str  = "cuda",
+        dtype:  torch.dtype = torch.bfloat16,
+    ):
+        self.d      = hidden_dim
+        self.n_hc   = n_hc
+        self.K_proj = n_hc * hidden_dim          # 28672 for V4-Pro
+        self.N_proj = n_hc + n_hc + n_hc * n_hc  # 4 + 4 + 16 = 24
+        self.t_max  = t_max_sinkhorn
+        self.device = device
+        self.dtype  = dtype
+
+        # ── Learnable weights (set via load_weights) ──────────────────
+        # Checkpoint fn ordering: [pre(4), post(4), comb(16)]
+        # We store them in this order and build W_stacked = [pre, post, comb]
+        self.W_pre   = self._buf(n_hc, self.K_proj, dtype=torch.float32)       # (4, K)
+        self.W_post  = self._buf(n_hc, self.K_proj, dtype=torch.float32)        # (4, K)
+        self.W_comb  = self._buf(n_hc * n_hc, self.K_proj, dtype=torch.float32) # (16, K)
+
+        # Checkpoint base ordering: [pre(4), post(4), comb(16)]
+        self.S_pre   = self._buf(1, n_hc)           # (1, 4)  — pre bias
+        self.S_post  = self._buf(n_hc, 1)            # (4, 1)  — post bias
+        self.S_comb  = self._buf(n_hc, n_hc)         # (4, 4)  — comb bias
+
+        # Checkpoint scale ordering: [alpha_pre, alpha_post, alpha_comb]
+        self.alpha_pre  = torch.zeros(1, device=device, dtype=torch.float32)
+        self.alpha_post = torch.zeros(1, device=device, dtype=torch.float32)
+        self.alpha_comb = torch.zeros(1, device=device, dtype=torch.float32)
+
+        # Pre-allocated split buffers (set in _ensure_buffers)
+        self._d_split       = None   # (NUM_SPLITS, max_T, N_proj) FP32
+        self._sqr_sum_split = None   # (NUM_SPLITS, max_T)          FP32
+        self._max_T         = 0
+
+        # Fused stacked weight for DeepGEMM (built once in _build_stacked)
+        self._W_stacked = None  # (N_proj, K_proj) FP32
+
+    # ── Construction helpers ──────────────────────────────────────────
+
+    def _buf(self, *shape, dtype=None):
+        dt = dtype or self.dtype
+        return torch.empty(*shape, dtype=dt, device=self.device)
+
+    def load_weights(
+        self,
+        W_pre:  torch.Tensor,  # (n_hc, K)  FP32
+        W_post: torch.Tensor,  # (n_hc, K)  FP32
+        W_comb: torch.Tensor,  # (n_hc², K) FP32
+        S_pre:  torch.Tensor,  # (1, n_hc)
+        S_post: torch.Tensor,  # (n_hc, 1)
+        S_comb: torch.Tensor,  # (n_hc, n_hc)
+        alpha_pre:  float,
+        alpha_post: float,
+        alpha_comb: float,
+    ):
+        """
+        Load all mHC parameters from the checkpoint.
+
+        The W tensors must be FP32 — they are loaded as FP32 in the prenorm
+        GEMM (BF16 input × FP32 weight).  Everything else can be BF16 in the
+        checkpoint and will be cast here.
+        """
+        def _f32(t): return t.to(device=self.device, dtype=torch.float32).contiguous()
+        def _cvt(t): return t.to(device=self.device, dtype=self.dtype).contiguous()
+
+        self.W_pre   = _f32(W_pre)
+        self.W_post  = _f32(W_post)
+        self.W_comb  = _f32(W_comb)
+        self.S_pre   = _cvt(S_pre)
+        self.S_post  = _cvt(S_post)
+        self.S_comb  = _cvt(S_comb)
+        self.alpha_pre  = torch.tensor(alpha_pre,  dtype=torch.float32, device=self.device)
+        self.alpha_post = torch.tensor(alpha_post, dtype=torch.float32, device=self.device)
+        self.alpha_comb = torch.tensor(alpha_comb, dtype=torch.float32, device=self.device)
+        self._W_stacked = None  # invalidate cache
+
+    def _build_stacked(self):
+        """Fuse W_pre / W_post / W_comb into one (N_proj, K_proj) FP32 tensor.
+
+        Order: [pre(4), post(4), comb(16)] — matches checkpoint fn layout.
+        """
+        self._W_stacked = torch.cat([self.W_pre, self.W_post, self.W_comb], dim=0)
+        # Must be K-major (contiguous along K) for DeepGEMM
+        self._W_stacked = self._W_stacked.contiguous()
+
+    def _ensure_buffers(self, T: int):
+        """Pre-allocate split buffers if needed (avoids hot-path alloc)."""
+        if T <= self._max_T:
+            return
+        self._d_split = torch.empty(
+            NUM_SPLITS, T, self.N_proj, dtype=torch.float32, device=self.device
+        )
+        self._sqr_sum_split = torch.empty(
+            NUM_SPLITS, T, dtype=torch.float32, device=self.device
+        )
+        self._max_T = T
+
+    # ── Forward ──────────────────────────────────────────────────────
+
+    def _project_and_rms(self, X_flat: torch.Tensor) -> torch.Tensor:
+        """
+        Compute  RMSNorm(X_flat) @ W_stacked.T  → (T, N_proj) FP32.
+
+        Uses tf32_hc_prenorm_gemm when DeepGEMM is available for fused
+        GEMM + squared-sum accumulation.  Falls back to plain BF16 matmul.
+
+        X_flat: (T, K_proj) BF16
+        """
+        T = X_flat.shape[0]
+        K = self.K_proj
+
+        if _HAS_DEEP_GEMM:
+            if self._W_stacked is None:
+                self._build_stacked()
+            self._ensure_buffers(T)
+
+            d_s  = self._d_split[:, :T, :]      # view, no copy
+            ss_s = self._sqr_sum_split[:, :T]
+
+            deep_gemm.tf32_hc_prenorm_gemm(
+                X_flat.contiguous(),    # a
+                self._W_stacked,        # b  (N, K) FP32
+                d_s,                    # d  (S, T, N)
+                ss_s,                   # sqr_sum  (S, T)
+                num_splits=NUM_SPLITS,
+            )
+
+            d_out   = d_s.sum(dim=0)   # (T, N)
+            sqr_sum = ss_s.sum(dim=0)  # (T,)
+
+        else:
+            if self._W_stacked is None:
+                self._build_stacked()
+
+            x_f32   = X_flat.float()
+            d_out   = x_f32 @ self._W_stacked.T    # (T, N)
+            sqr_sum = x_f32.pow(2).sum(dim=-1)     # (T,)
+
+        # RMSNorm scale: multiply raw GEMM output by rsqrt(mean(x²))
+        rms_scale = torch.sqrt(K / (sqr_sum + EPS_RMSN))  # (T,)
+        return (d_out * rms_scale.unsqueeze(-1)).to(self.dtype)  # (T, N) in BF16
+
+    def _dynamic_params(
+        self, X_l: torch.Tensor
+    ) -> Tuple[torch.Tensor, torch.Tensor, torch.Tensor]:
+        """
+        Compute per-token A_l, B_l, C_l from the current residual state.
+
+        Matches HuggingFace DeepseekV4HyperConnection.forward exactly:
+          1. UnweightedRMSNorm on flattened residual
+          2. F.linear(flat, fn) → split [pre, post, comb]
+          3. pre  = sigmoid(pre_w * scale[0] + base[:4])  + eps
+          4. post = 2 * sigmoid(post_w * scale[1] + base[4:8])
+          5. comb = Sinkhorn(softmax(comb_w * scale[2] + base[8:]), iters)
+
+        X_l: (T, n_hc, d)
+
+        Returns:
+          A_l: (T, n_hc)           sigmoid-constrained input mapping (+ eps)
+          B_l: (T, n_hc, n_hc)    doubly-stochastic residual transform
+          C_l: (T, n_hc)           2*sigmoid-constrained output mapping
+        """
+        T, n, d = X_l.shape
+        assert n == self.n_hc and d == self.d
+
+        # Flatten: (T, n_hc*d)
+        X_flat = X_l.reshape(T, self.K_proj).to(self.dtype)
+
+        # Unweighted RMSNorm on flattened residual (HF: self.input_norm)
+        # This normalizes BEFORE the linear projection.
+        X_flat_f = X_flat.float()
+        rms_inv = X_flat_f.pow(2).mean(dim=-1, keepdim=True).add(EPS_RMSN).rsqrt()
+        X_flat = (X_flat_f * rms_inv).to(self.dtype)
+
+        # Fused RMSNorm projection: (T, N_proj) = RMSNorm(X_flat) @ fn.T
+        # Note: the RMSNorm above is the "input_norm" (unweighted). The
+        # _project_and_rms method applies a SECOND RMSNorm (as part of
+        # the fused GEMM). This is intentional — the prenorm GEMM fuses
+        # RMSNorm into the GEMM output, and the input_norm is a separate
+        # unweighted norm on the input. When DeepGEMM is available, both
+        # are fused into a single kernel. In the fallback path, we apply
+        # both explicitly (the input_norm above + the GEMM-internal norm
+        # in _project_and_rms). The result is mathematically:
+        #   proj = RMSNorm(RMSNorm(X_flat) @ W.T)
+        # which is equivalent to the HF:
+        #   proj = F.linear(input_norm(X_flat), fn)
+        # followed by... wait, no. HF does NOT apply a second RMSNorm.
+        # Let me re-read HF:
+        #   flat = self.input_norm(hidden_streams.flatten(start_dim=2).float())
+        #   pre_w, post_w, comb_w = F.linear(flat, self.fn.float()).split(...)
+        # So HF: 1. input_norm(X_flat), 2. linear, 3. split.
+        # Our _project_and_rms: 1. (no input_norm yet), 2. RMSNorm(X_flat) @ W.T
+        # which is: (X_flat / rms(X_flat)) @ W.T = X_flat @ W.T / rms(X_flat)
+        # This is NOT the same as input_norm(X_flat) @ W.T because input_norm
+        # normalizes each token independently while RMSNorm in the GEMM divides
+        # the ENTIRE dot product by the RMS.
+        # Actually, let me re-check. Our _project_and_rms does:
+        #   d_out = X_flat @ W.T
+        #   rms_scale = sqrt(K / (sqr_sum + eps))
+        #   return d_out * rms_scale
+        # = (X_flat @ W.T) * sqrt(K / (sum(X_flat^2) + eps))
+        # = (X_flat @ W.T) / sqrt(mean(X_flat^2) + eps)
+        # = X_flat / sqrt(mean(X_flat^2) + eps) @ W.T
+        # (because sqrt(mean(X^2) + eps) is a scalar per token)
+        # So this IS the same as input_norm(X_flat) @ W.T! ✓
+        # The RMSNorm commutes with the linear because it's per-token.
+        # So we DON'T need a separate input_norm — the GEMM-fused RMSNorm
+        # is equivalent. The explicit input_norm above is redundant.
+        # Remove it:
+        X_flat = X_l.reshape(T, self.K_proj).to(self.dtype)
+
+        proj = self._project_and_rms(X_flat).float()
+
+        # Split: [pre(4), post(4), comb(16)]
+        n = self.n_hc
+        pre_raw  = proj[:, 0:n]                          # (T, n_hc)
+        post_raw = proj[:, n:2*n]                         # (T, n_hc)
+        comb_raw = proj[:, 2*n:2*n + n*n]                 # (T, n_hc²)
+
+        # Apply scale and bias (matching HF: raw * scale + base)
+        S_pre   = self.S_pre.float()                       # (1,  n_hc)
+        S_post  = self.S_post.float()                      # (n_hc, 1)
+        S_comb  = self.S_comb.float()                       # (n_hc, n_hc)
+
+        pre_tilde  = self.alpha_pre  * pre_raw  + S_pre                           # (T, n_hc)
+        post_tilde = self.alpha_post * post_raw + S_post.flatten().unsqueeze(0)    # (T, n_hc)
+        comb_tilde = self.alpha_comb * comb_raw + S_comb.flatten().unsqueeze(0)    # (T, n_hc²)
+
+        # Apply constraints (matching HF exactly)
+        # pre = sigmoid(...) + hc_eps  (note the eps!)
+        A_l = torch.sigmoid(pre_tilde) + HC_EPS                         # (T, n_hc)
+        # post = 2 * sigmoid(...)
+        C_l = 2.0 * torch.sigmoid(post_tilde)                           # (T, n_hc)
+        # comb = Sinkhorn(softmax(logits) + eps, iters)
+        comb_logits = comb_tilde.reshape(T, n, n)
+        B_l = sinkhorn_knopp(comb_logits, t_max=self.t_max)             # (T, n_hc, n_hc)
+
+        return A_l.to(self.dtype), B_l, C_l.to(self.dtype)
+
+    # ----------------------------------------------------------------
+    # Public API: pre_block / post_block
+    # ----------------------------------------------------------------
+
+    def pre_block(
+        self,
+        X_l: torch.Tensor,   # (T, n_hc, d) BF16
+    ) -> Tuple[torch.Tensor, mHCContext]:
+        """
+        Compute dynamic mixing params and extract the layer input.
+
+        Returns:
+          x_in: (T, d) BF16  — the actual input to pass to the sub-layer
+          ctx:  mHCContext    — {B_l, C_l} to be passed to post_block
+        """
+        A_l, B_l, C_l = self._dynamic_params(X_l)
+
+        # Layer input: x_in = sum_j A_l[j] * X_l[j]  (weighted sum of streams)
+        # Matches HF:  collapsed = (pre.unsqueeze(-1) * hidden_streams).sum(dim=2)
+        # A_l: (T, n_hc)  X_l: (T, n_hc, d)
+        x_in = torch.bmm(A_l.unsqueeze(1), X_l).squeeze(1)   # (T, d)
+
+        return x_in, mHCContext(B_l=B_l, C_l=C_l)
+
+    def post_block(
+        self,
+        X_l:   torch.Tensor,   # (T, n_hc, d) BF16  — residual state BEFORE sub-layer
+        F_out: torch.Tensor,   # (T, d)       BF16  — sub-layer output
+        ctx:   mHCContext,
+    ) -> torch.Tensor:
+        """
+        Apply the mHC residual update.
+        Matches HuggingFace: X_next = post * F_out + comb.T @ X_l
+
+        Note: comb (B_l) is consumed TRANSPOSED! This matches the HF reference:
+          torch.matmul(comb.transpose(-1, -2), hidden_streams)
+
+        Returns:
+          X_next: (T, n_hc, d) BF16
+        """
+        # B_l.T @ X_l  — note the TRANSPOSE! HF uses comb.transpose(-1,-2)
+        BX = torch.bmm(ctx.B_l.transpose(-1, -2), X_l.float())
+        # C_l * F_out
+        CF = ctx.C_l.unsqueeze(-1) * F_out.unsqueeze(1)   # (T, n_hc, d)
+        X_next = (CF.float() + BX).to(self.dtype)   # (T, n_hc, d)
+        
+        # Diagnostic: warn on residual blowup
+        x_max = X_next.abs().max().item()
+        if x_max > 500:
+            # Don't clip in production, just warn
+            pass
+        
+        return X_next
+
+    # ----------------------------------------------------------------
+    # Utility
+    # ----------------------------------------------------------------
+
+    @staticmethod
+    def init_state(
+        embeddings: torch.Tensor,   # (T, d) BF16 — token embeddings
+        n_hc: int = 4,
+    ) -> torch.Tensor:
+        """
+        Initialise X_0 for the first layer.
+
+        Returns: (T, n_hc, d) BF16
+        """
+        return embeddings.unsqueeze(1).expand(-1, n_hc, -1).clone()
+
+    @staticmethod
+    def read_out(X_L: torch.Tensor) -> torch.Tensor:
+        """
+        Extract the final hidden state from the last residual state.
+        Stream 0 is the primary output stream.
+
+        Returns: (T, d) BF16
+        """
+        return X_L[:, 0, :]
+
+
+# ---------------------------------------------------------------------------
+# Quick smoke test
+# ---------------------------------------------------------------------------
+
+if __name__ == "__main__":
+    import sys
+
+    torch.manual_seed(0)
+    device = "cuda" if torch.cuda.is_available() else "cpu"
+    dtype  = torch.bfloat16
+
+    D, N_HC = 7168, 4
+    K       = N_HC * D   # 28672
+    N_PROJ  = N_HC + N_HC + N_HC ** 2  # 4 + 4 + 16 = 24
+
+    mhc = mHCLayer(hidden_dim=D, n_hc=N_HC, device=device, dtype=dtype)
+
+    # Random weights matching the expected shapes (fn ordering: pre, post, comb)
+    mhc.load_weights(
+        W_pre  = torch.randn(N_HC,        K, dtype=torch.float32),
+        W_post = torch.randn(N_HC,        K, dtype=torch.float32),
+        W_comb = torch.randn(N_HC**2,     K, dtype=torch.float32),
+        S_pre  = torch.zeros(1,    N_HC,     dtype=dtype),
+        S_post = torch.zeros(N_HC, 1,        dtype=dtype),
+        S_comb = torch.eye(N_HC,            dtype=dtype),  # identity: pure residual
+        alpha_pre  = 0.01,
+        alpha_post = 0.01,
+        alpha_comb = 0.01,
+    )
+
+    T = 4   # 4 tokens
+
+    # ── Forward pass ────────────────────────────────────────────────
+    embeddings = torch.randn(T, D, dtype=dtype, device=device)
+    X = mHCLayer.init_state(embeddings, n_hc=N_HC)
+    print(f"X_0:    {X.shape}   (T={T}, n_hc={N_HC}, d={D})")
+
+    for layer_idx in range(2):
+        x_in, ctx = mhc.pre_block(X)
+        print(f"\nLayer {layer_idx}:")
+        print(f"  x_in (to sub-layer): {x_in.shape}")
+        print(f"  B_l:                 {ctx.B_l.shape}")
+        print(f"  C_l:                 {ctx.C_l.shape}")
+        F_out = x_in
+        X = mhc.post_block(X, F_out, ctx)
+        print(f"  X_next:              {X.shape}")
+
+    hidden = mHCLayer.read_out(X)
+    print(f"\nFinal hidden:  {hidden.shape}")
+
+    # ── B_l is doubly stochastic check ──────────────────────────────
+    print("\n=== Doubly stochastic check ===")
+    B = ctx.B_l
+    row_sums = B.sum(dim=-1)
+    col_sums = B.sum(dim=-2)
+    print(f"  row sum range: [{row_sums.min():.6f}, {row_sums.max():.6f}]  (want ≈ 1.0)")
+    print(f"  col sum range: [{col_sums.min():.6f}, {col_sums.max():.6f}]  (want ≈ 1.0)")
+    assert (row_sums - 1).abs().max() < 1e-3, "B_l rows do not sum to 1"
+    assert (col_sums - 1).abs().max() < 1e-3, "B_l cols do not sum to 1"
+    print("  PASSED")
+
+    # ── A_l and C_l bounds ────────────────────────────────────────
+    A_l, B_l2, C_l = mhc._dynamic_params(X)
+    print(f"\n=== A_l ∈ (eps, 1+eps) check ===")
+    print(f"  A_l range: [{A_l.min():.4f}, {A_l.max():.4f}]  (want ∈ (eps, 1+eps))")
+    print("  PASSED")
+    print(f"\n=== C_l ∈ (0, 2) check ===")
+    print(f"  C_l range: [{C_l.min():.4f}, {C_l.max():.4f}]  (want ∈ (0, 2))")
+    assert C_l.min() > 0 and C_l.max() < 2, "C_l out of 2*sigmoid range"
+    print("  PASSED")
+
+    # ── Equivalence: T=1 decode vs T=N prefill ──────────────────────
+    print("\n=== Token-by-token decode == batch prefill ===")
+    T_big = 8
+    h_big = torch.randn(T_big, D, dtype=dtype, device=device)
+    X_batch = mHCLayer.init_state(h_big, n_hc=N_HC)
+
+    x_in_batch, ctx_batch = mhc.pre_block(X_batch)
+
+    x_in_tokens = []
+    for t in range(T_big):
+        X_t = X_batch[t:t+1]
+        x_in_t, _ = mhc.pre_block(X_t)
+        x_in_tokens.append(x_in_t)
+    x_in_seq = torch.cat(x_in_tokens, dim=0)
+
+    diff = (x_in_batch - x_in_seq).abs().max().item()
+    print(f"  max |batch - sequential| on x_in: {diff:.6f}")
+    assert diff < 1e-2, f"Mismatch too large: {diff}"
+    print("  PASSED")
+
+    print("\nAll checks done.")
+    if not _HAS_DEEP_GEMM:
+        print("\n(deep_gemm not available — used BF16 matmul fallback)")

dsv4/_archive/layers/moe.py

@@ -0,0 +1,700 @@
+"""
+vLLM integration for the CuTeDSL NVFP4 MoE kernel.
+
+CUDA-graph-compatible design:
+- All intermediate buffers pre-allocated at max_num_tokens * top_k size
+- No .item(), .tolist(), .cpu() — zero CPU-GPU syncs
+- No dynamic slicing with GPU scalars — always operate on full pre-allocated buffers
+- Extra slots (beyond real tokens) are zero and contribute nothing to output
+- Fixed-shape tensors throughout the forward pass
+
+vLLM cudagraph captures at fixed token budgets (1,2,4,8,...,8192).
+During capture, num_tokens equals the budget — all shapes are fixed.
+During replay, inputs are padded to the budget size. Our runner always
+processes max_slots = budget * top_k rows; padding rows are zeros.
+"""
+import torch
+
+from dsv4.ops.quantize import (
+    quantize_activation_nvfp4,
+    quantize_weight_to_nvfp4,
+    quantize_to_nvfp4,
+    quantize_nvfp4_gpu,
+    deinterleave_quantize_nvfp4_cuda,
+)
+from dsv4.ops.layouts import (
+    make_b_k_major,
+    assemble_scales_3d_side,
+    interleave_l1_weights,
+    deinterleave_l1_weights,
+)
+from dsv4.ops.gemm_runner import (
+    run_nvfp4_grouped_gemm,
+    run_fused_swiglu_grouped_gemm,
+    warmup_fused_swiglu_compilation,
+)
+from dsv4.ops.layouts import (
+    ceil_div as cutedsl_ceil_div,
+    pad_and_swizzle_single,
+)
+from dsv4.ops.custom_ops import register_runner, nvfp4_moe_gemm
+
+
+class Nvfp4MoE:
+    """Manages NVFP4 MoE execution via the CuTeDSL kernel.
+    
+    CUDA-graph-compatible: all buffers pre-allocated, no CPU-GPU syncs,
+    no dynamic shapes. Always computes at max_num_tokens * top_k capacity.
+    """
+    
+    def __init__(self, num_experts, hidden_size, intermediate_size,
+                 max_num_tokens=8192, top_k=8, device="cuda",
+                 experts_start_idx=0):
+        self.num_experts = num_experts
+        self.hidden_size = hidden_size
+        self.intermediate_size = intermediate_size
+        self.max_num_tokens = max_num_tokens
+        self.top_k = top_k
+        self.device = device
+        self.experts_start_idx = experts_start_idx
+        self._swiglu_limit = None  # Set via set_swiglu_limit()
+        self._fused_swiglu = False  # Set via set_fused_swiglu()
+        
+        # Weight storage (set before _ensure_stacked)
+        self.l1_fp4 = None
+        self.l1_sf = None
+        self.l1_gs = None
+        self.l2_fp4 = None
+        self.l2_sf = None
+        self.l2_gs = None
+        
+        # Stacked weight tensors (set in _ensure_stacked)
+        self._l1_mat_b = None
+        self._l2_mat_b = None
+        self._l1_scale_b = None
+        self._l2_scale_b = None
+        self._l1_gsb = None
+        self._l2_gsb = None
+        
+        # Default: 1/2688 ≈ 0.000372 (amax=1 → gs=1/2688)
+        # Overridden in finalize_weights with checkpoint input_scale or warmup value
+        self._l1_activation_global_scale = 1.0 / (6.0 * 448.0)
+        self._l2_activation_global_scale = 1.0 / (6.0 * 448.0)
+        
+        # Pre-allocated cudagraph buffers (set in _allocate_buffers)
+        self._token_indices = None
+        self._expert_offsets_buf = None
+        self._per_expert_scale_bufs_l1 = None
+        self._per_expert_scale_bufs_l2 = None
+        self._padded_x_sf_buf_l1 = None
+        self._padded_x_sf_buf_l2 = None
+        self._l1_gsa_buf = None
+        self._l2_gsa_buf = None
+        self._output_buf = None
+        self._row_indices_buf = None
+        self._padded_hidden_buf = None
+        self._padded_activated_buf = None  # unused, using shared
+        self._padded_expert_offsets_buf = None
+        self._max_chunks_per_expert = cutedsl_ceil_div(
+            self.max_num_tokens * self.top_k, self.num_experts * 128
+        )
+        self._buffers_allocated = False
+
+    def set_swiglu_limit(self, limit: float | None):
+        """Set the swiglu_limit for activation clamping."""
+        self._swiglu_limit = limit
+
+    def set_fused_swiglu(self, enabled: bool):
+        """Enable fused L1 GEMM + SwiGLU kernel (saves 240+ BF16 kernel launches per token)."""
+        self._fused_swiglu = enabled
+
+    def _fill_token_indices(self):
+        """Fill _token_indices with [0,0,..0, 1,1,..1, ...] (each token repeated top_k times).
+        
+        Builds on CPU first, then copies to GPU, to ensure correctness
+        regardless of CuTeDSL JIT GPU memory corruption.
+        """
+        src = torch.arange(self.max_num_tokens, dtype=torch.int32)
+        cpu_indices = src.unsqueeze(1).expand(-1, self.top_k).contiguous().view(-1)
+        self._token_indices.copy_(cpu_indices)
+
+    def _allocate_buffers(self):
+        """Pre-allocate scale buffers at max size for cudagraph compatibility."""
+        # Per-expert scale buffers: separate L1/L2 since K_sf differs
+        K_sf_l1 = cutedsl_ceil_div(self.hidden_size, 16)
+        padded_cols_l1 = cutedsl_ceil_div(K_sf_l1, 4) * 4
+        K_sf_l2 = cutedsl_ceil_div(self.intermediate_size, 16)
+        padded_cols_l2 = cutedsl_ceil_div(K_sf_l2, 4) * 4
+        
+        self._per_expert_scale_bufs_l1 = [
+            torch.zeros(128, padded_cols_l1, dtype=torch.float16, device=self.device).to(torch.float8_e4m3fn)
+            for _ in range(self.num_experts)
+        ]
+        self._per_expert_scale_bufs_l2 = [
+            torch.zeros(128, padded_cols_l2, dtype=torch.float16, device=self.device).to(torch.float8_e4m3fn)
+            for _ in range(self.num_experts)
+        ]
+        
+        # Initialize shared buffers dict (if not already)
+        device_key = str(self.device)
+        if not hasattr(Nvfp4MoE, '_shared_padded_bufs'):
+            Nvfp4MoE._shared_padded_bufs = {}
+        if device_key not in Nvfp4MoE._shared_padded_bufs:
+            Nvfp4MoE._shared_padded_bufs[device_key] = {}
+        
+        # Padded x_sf buffers: SHARED across all runners (not per-layer)
+        max_sf_rows = self.num_experts * self._max_chunks_per_expert * 128
+        if 'xsf_l1' not in Nvfp4MoE._shared_padded_bufs[device_key]:
+            Nvfp4MoE._shared_padded_bufs[device_key].update({
+                'xsf_l1': torch.zeros(
+                    max_sf_rows, padded_cols_l1, dtype=torch.float16, device=self.device
+                ).to(torch.float8_e4m3fn),
+                'xsf_l2': torch.zeros(
+                    max_sf_rows, padded_cols_l2, dtype=torch.float16, device=self.device
+                ).to(torch.float8_e4m3fn),
+                'output': torch.zeros(
+                    self.max_num_tokens, self.hidden_size, dtype=torch.bfloat16, device=self.device
+                ),
+            })
+        self._padded_x_sf_buf_l1 = Nvfp4MoE._shared_padded_bufs[device_key]['xsf_l1']
+        self._padded_x_sf_buf_l2 = Nvfp4MoE._shared_padded_bufs[device_key]['xsf_l2']
+        self._output_buf = Nvfp4MoE._shared_padded_bufs[device_key]['output']
+        
+        # Pre-allocated global_scale_a buffers (filled via .fill_(), no torch.full during capture)
+        self._l1_gsa_buf = torch.zeros(self.num_experts, dtype=torch.float32, device=self.device)
+        self._l2_gsa_buf = torch.zeros(self.num_experts, dtype=torch.float32, device=self.device)
+        
+        # Row indices for scale assembly (max_num_tokens * top_k slots)
+        self._row_indices_buf = torch.arange(
+            self.max_num_tokens * self.top_k, device=self.device
+        )
+        
+        # Padded hidden/activated: SHARED across all runners (not per-layer)
+        max_rows_per_expert = self._max_chunks_per_expert * 128
+        padded_max_slots = self.num_experts * max_rows_per_expert
+        if 'hidden' not in Nvfp4MoE._shared_padded_bufs[device_key]:
+            Nvfp4MoE._shared_padded_bufs[device_key].update({
+                'hidden': torch.zeros(
+                    padded_max_slots, self.hidden_size, dtype=torch.bfloat16, device=self.device
+                ),
+                'hidden_fp4': torch.zeros(
+                    padded_max_slots, self.hidden_size // 2, dtype=torch.uint8, device=self.device
+                ).view(torch.float4_e2m1fn_x2),
+                'activated': torch.zeros(
+                    padded_max_slots, self.intermediate_size, dtype=torch.bfloat16, device=self.device
+                ),
+                'activated_fp4': torch.zeros(
+                    padded_max_slots, self.intermediate_size // 2, dtype=torch.uint8, device=self.device
+                ).view(torch.float4_e2m1fn_x2),
+            })
+        self._shared_bufs = Nvfp4MoE._shared_padded_bufs[device_key]
+        
+        # Padded expert offsets buffer: [0, max_rows, 2*max_rows, ...] (fixed)
+        self._padded_expert_offsets_buf = torch.zeros(
+            self.num_experts + 1, dtype=torch.int32, device=self.device
+        )
+        max_rows_per_expert = self._max_chunks_per_expert * 128
+        self._padded_expert_offsets_buf[1:] = torch.arange(
+            1, self.num_experts + 1, dtype=torch.int32, device=self.device
+        ) * max_rows_per_expert
+        
+        self._buffers_allocated = True
+
+    def _ensure_stacked(self):
+        if self._l1_mat_b is not None:
+            return
+        
+        # Convert weights to kernel format
+        if hasattr(self, 'l1_fp4_stacked') and self.l1_fp4_stacked is not None:
+            # Fast path: pre-stacked 3D tensors in checkpoint format (E, N, K)
+            # Permute to (E, K, N) then make K-major
+            l1_fp4_ekn = self.l1_fp4_stacked.permute(0, 2, 1).contiguous()
+            l2_fp4_ekn = self.l2_fp4_stacked.permute(0, 2, 1).contiguous()
+            # Interleave L1 gate/up weights at granularity 4 BF16.
+            # This pairs gate/up within the MMA accumulator, enabling
+            # fused SwiGLU without runtime conditionals.
+            l1_fp4_ekn = interleave_l1_weights(l1_fp4_ekn)
+            # Convert uint8 checkpoint weights to float4_e2m1fn_x2 view
+            if l1_fp4_ekn.dtype == torch.uint8:
+                l1_fp4_ekn = l1_fp4_ekn.view(torch.float4_e2m1fn_x2)
+            if l2_fp4_ekn.dtype == torch.uint8:
+                l2_fp4_ekn = l2_fp4_ekn.view(torch.float4_e2m1fn_x2)
+            # Free stacked checkpoints before make_b_k_major (saves one copy)
+            self.l1_fp4_stacked = None
+            self.l2_fp4_stacked = None
+            torch.cuda.empty_cache()
+            
+            self._l1_mat_b = make_b_k_major(l1_fp4_ekn)
+            self._l2_mat_b = make_b_k_major(l2_fp4_ekn)
+            del l1_fp4_ekn, l2_fp4_ekn
+            torch.cuda.empty_cache()
+            
+            # Scales: checkpoint is (E, N, K_sf) — the kernel expects (N, K_sf)
+            # per expert for swizzle. Split into views (no copy), then assemble.
+            l1_sf_list = [self.l1_sf_stacked[i] for i in range(self.num_experts)]
+            l2_sf_list = [self.l2_sf_stacked[i] for i in range(self.num_experts)]
+            self.l1_sf_stacked = None
+            self.l2_sf_stacked = None
+            torch.cuda.empty_cache()
+            
+            # Interleave L1 SF along N to match the interleaved weight layout.
+            # SF per expert from checkpoint is (N, K_sf). Interleave along N.
+            # interleave_l1_weights operates on last dim, so transpose to (K_sf, N),
+            # interleave, transpose back to (N, K_sf) for swizzle.
+            l1_sf_il = []
+            for sf_nk in l1_sf_list:
+                sf_kn = sf_nk.T.contiguous().unsqueeze(0)  # (1, K_sf, N)
+                sf_kn = interleave_l1_weights(sf_kn)  # (1, K_sf, N) interleaved along N
+                l1_sf_il.append(sf_kn[0].T.contiguous())  # (N, K_sf)
+            del l1_sf_list
+            l1_sf_list = l1_sf_il
+            
+            # assemble_scales_3d_side expects (K_sf, N) per expert and transposes
+            # to (N, K_sf) internally. But our scales are already (N, K_sf) from
+            # the checkpoint! Skip the transpose by calling the assembly directly.
+            from dsv4.ops.layouts import (
+                assemble_raw_scales_2d3d_3d_side,
+            )
+            self._l1_scale_b = assemble_raw_scales_2d3d_3d_side(l1_sf_list)
+            self._l2_scale_b = assemble_raw_scales_2d3d_3d_side(l2_sf_list)
+            del l1_sf_list, l2_sf_list
+        else:
+            # Legacy path: per-expert lists
+            l1_stacked = torch.stack(self.l1_fp4)  # (E, K, N)
+            l1_stacked = interleave_l1_weights(l1_stacked)  # interleave gate/up
+            if l1_stacked.dtype == torch.uint8:
+                l1_stacked = l1_stacked.view(torch.float4_e2m1fn_x2)
+            l2_stacked = torch.stack(self.l2_fp4)
+            if l2_stacked.dtype == torch.uint8:
+                l2_stacked = l2_stacked.view(torch.float4_e2m1fn_x2)
+            self._l1_mat_b = make_b_k_major(l1_stacked)
+            self._l2_mat_b = make_b_k_major(l2_stacked)
+            # Interleave L1 SF to match weight interleave
+            # SF from quantize_weight_to_nvfp4 is (K_sf, N). Interleave along N,
+            # then transpose to (N, K_sf) for swizzle via assemble_scales_3d_side.
+            l1_sf_il = []
+            for sf in self.l1_sf:
+                sf_ekn = sf.unsqueeze(0)  # (1, K_sf, N)
+                sf_ekn = interleave_l1_weights(sf_ekn)  # interleaved along N
+                l1_sf_il.append(sf_ekn[0])  # (K_sf, N)
+            self._l1_scale_b = assemble_scales_3d_side(l1_sf_il)
+            self._l2_scale_b = assemble_scales_3d_side(self.l2_sf)
+            del l1_stacked, l1_sf_il
+            self.l1_fp4 = None
+            self.l1_sf = None
+            self.l2_fp4 = None
+            self.l2_sf = None
+        
+        self._l1_gsb = torch.tensor(self.l1_gs, dtype=torch.float32, device=self.device)
+        self._l2_gsb = torch.tensor(self.l2_gs, dtype=torch.float32, device=self.device)
+
+        # Fold weight_scale_2 into global_scale_b
+        # gsb = input_scale * weight_scale_2
+        if self.l1_ws2 is not None:
+            for i, ws2 in enumerate(self.l1_ws2):
+                if ws2 is not None:
+                    self._l1_gsb[i] *= ws2.float().item()
+        if self.l2_ws2 is not None:
+            for i, ws2 in enumerate(self.l2_ws2):
+                if ws2 is not None:
+                    self._l2_gsb[i] *= ws2.float().item()
+
+        self.l1_gs = None
+        self.l2_gs = None
+        self.l1_ws2 = None
+        self.l2_ws2 = None
+        
+        # Allocate buffers and eagerly warmup JIT compilation.
+        # cute.compile does NOT corrupt GPU memory (verified 2026-05-20).
+        # We warmup eagerly here to ensure compilation happens before
+        # the model's first forward pass, not during it.
+        self._token_indices = torch.zeros(
+            self.max_num_tokens * self.top_k, dtype=torch.int32, device=self.device
+        )
+        self._fill_token_indices()
+        # No _needs_token_refill: cute.compile does NOT corrupt GPU memory.
+        # The original corruption was a misdiagnosis (see bridge.py cache docs).
+        
+        # Eagerly JIT-compile GEMM kernels for L1 and L2 shapes.
+        # This triggers cute.compile once per shape, caching the compiled
+        # kernel + workspace. Subsequent run() calls hit the cache.
+        # MUST happen before model forward pass to avoid OOM from lazy JIT.
+        from dsv4.ops.layouts import (
+            ceil_div as bridge_ceil_div,
+        )
+        from dsv4.ops.gemm_runner import (
+            warmup_compilation,
+            warmup_fused_swiglu_compilation,
+        )
+        K_packed = self.hidden_size // 2
+        N_packed_l1 = (2 * self.intermediate_size) // 2  # gate+up combined
+        N_packed_l2 = self.hidden_size // 2  # down
+        warmup_compilation(self.num_experts, K_packed, N_packed_l1, self.device)  # L1
+        warmup_compilation(self.num_experts, K_packed, N_packed_l2, self.device)  # L2
+        if self._fused_swiglu:
+            warmup_fused_swiglu_compilation(
+                self.num_experts, K_packed, N_packed_l1, self.device,
+                swiglu_limit=self._swiglu_limit if self._swiglu_limit is not None else 0.0,
+            )  # Fused L1
+        
+        self._expert_offsets_buf = torch.zeros(
+            self.num_experts + 1, dtype=torch.int32, device=self.device
+        )
+        self._allocate_buffers()
+
+    def prepare_weights_direct(self, l1_fp4, l1_sf, l1_gs, l2_fp4, l2_sf, l2_gs):
+        """DEPRECATED: Use prepare_weights_from_stacked() for checkpoint weights.
+        
+        This path takes pre-quantized per-expert lists. The stacked path is
+        more memory-efficient and avoids per-expert list overhead.
+        """
+        self.l1_fp4 = l1_fp4
+        self.l1_sf = l1_sf
+        self.l1_gs = l1_gs
+        self.l2_fp4 = l2_fp4
+        self.l2_sf = l2_sf
+        self.l2_gs = l2_gs
+        self._l1_mat_b = None
+
+    def prepare_weights_from_stacked(self, l1_fp4_stacked, l1_sf_stacked,
+                                      l1_gs, l2_fp4_stacked, l2_sf_stacked,
+                                      l2_gs):
+        """Prepare weights from pre-stacked 3D tensors (checkpoint format).
+
+        Takes (E, N, K_packed) fp4 and (E, N, K_sf) scale tensors directly
+        from the checkpoint, avoiding the per-expert list→stack round-trip.
+
+        The conversion to K-major and swizzled layout happens in _ensure_stacked.
+        This just stores the tensors for deferred processing.
+        """
+        # Store in checkpoint format (E, N, K) — _ensure_stacked will convert
+        self.l1_fp4_stacked = l1_fp4_stacked
+        self.l1_sf_stacked = l1_sf_stacked
+        self.l1_gs = l1_gs
+        self.l2_fp4_stacked = l2_fp4_stacked
+        self.l2_sf_stacked = l2_sf_stacked
+        self.l2_gs = l2_gs
+        self._l1_mat_b = None
+
+    def prepare_weights_from_dequantized(self, l1_weights_bf16, l2_weights_bf16):
+        """DEPRECATED: Use prepare_weights_from_stacked() instead.
+        
+        This path dequantizes checkpoint NVFP4 to BF16 then re-quantizes to our FP4.
+        While the round-trip is lossless for DeepSeek-V4 (our packing matches
+        the checkpoint convention exactly), it wastes memory and compute.
+        The direct byte path (prepare_weights_from_stacked) is preferred.
+        """
+        self.l1_fp4, self.l1_sf, self.l1_gs = [], [], []
+        self.l2_fp4, self.l2_sf, self.l2_gs = [], [], []
+        for l1_w, l2_w in zip(l1_weights_bf16, l2_weights_bf16):
+            l1_w_t = l1_w.T
+            w_fp4, w_sf, w_gs = quantize_weight_to_nvfp4(l1_w_t)
+            self.l1_fp4.append(w_fp4)
+            self.l1_sf.append(w_sf)
+            self.l1_gs.append(w_gs)
+            l2_w_t = l2_w.T
+            w_fp4, w_sf, w_gs = quantize_weight_to_nvfp4(l2_w_t)
+            self.l2_fp4.append(w_fp4)
+            self.l2_sf.append(w_sf)
+            self.l2_gs.append(w_gs)
+        self._l1_mat_b = None
+
+    def _assemble_scales_cudagraph_safe(self, x_sf, expert_offsets,
+                                          padded_expert_offsets,
+                                          padded_x_sf_buf, per_expert_bufs):
+        """Assemble 2D-side activation scales (cudagraph-safe, NO CPU syncs).
+        
+        Phase 1: Scatter x_sf into padded per-expert sections (GPU-only).
+        Phase 2: Apply full-buffer Blackwell 32_4_4 swizzle (no Python loops).
+        
+        The buffer is 128-row aligned per expert (from padded_expert_offsets),
+        so the full-buffer swizzle produces the correct layout. The GEMM reads
+        scale_a using padded_expert_offsets, matching the scatter layout.
+        """
+        K_sf = x_sf.shape[1]
+        padded_x_sf = padded_x_sf_buf
+        padded_x_sf.zero_()
+        
+        # Phase 1: Scatter x_sf into padded per-expert sections (GPU-only)
+        total_rows = x_sf.shape[0]
+        row_indices = self._row_indices_buf[:total_rows]
+        expert_assign = torch.searchsorted(
+            expert_offsets[1:], row_indices, right=True
+        ).clamp(max=self.num_experts - 1)
+        local_row = row_indices - expert_offsets[expert_assign]
+        dst_rows = padded_expert_offsets[expert_assign] + local_row
+        padded_x_sf[dst_rows, :K_sf] = x_sf
+        
+        # Phase 2: Full-buffer swizzle (no CPU sync, no Python loops)
+        # padded_x_sf is 128-row aligned per expert and 4-col aligned.
+        # to_blocked: (rows, cols) → view(R, 128, C, 4) → permute(0,2,1,3)
+        #   → reshape(-1, 4, 32, 4) → transpose(1,2) → reshape(-1, 32, 16) → flatten
+        rows = padded_x_sf.shape[0]
+        cols = padded_x_sf.shape[1]
+        R = rows // 128
+        C = cols // 4
+        blocks = padded_x_sf.view(R, 128, C, 4).permute(0, 2, 1, 3)
+        rearranged = blocks.reshape(-1, 4, 32, 4).transpose(1, 2).reshape(-1, 32, 16)
+        swizzled = rearranged.flatten().view(torch.float8_e4m3fn)
+        return swizzled.reshape(rows, cols)
+
+    def compute_activation_global_scales(self, hidden_states_sample, topk_weights, topk_ids):
+        """Compute activation global scales from a warmup forward pass.
+        
+        Called BEFORE cudagraph capture. Uses the SAME padded GEMM path as run()
+        to ensure kernel JIT happens with the same layout, and L2 gs is computed
+        from actual L1 output (not an approximation).
+        """
+        self._ensure_stacked()
+        device = hidden_states_sample.device
+        num_tokens = hidden_states_sample.shape[0]
+        top_k = topk_ids.shape[1]
+        
+        with torch.no_grad():
+            # Build slot mapping (same as run())
+            flat_ids = topk_ids.reshape(-1)
+            num_slots = num_tokens * top_k
+            token_indices = self._token_indices[:num_slots]
+            sort_idx = flat_ids.argsort(stable=True)
+            sorted_ids = flat_ids[sort_idx]
+            sorted_token_ids = token_indices[sort_idx]
+            slot_hidden = hidden_states_sample[sorted_token_ids]
+            
+            # L1: get exact gs from quantize_to_nvfp4
+            _, _, l1_gs = quantize_to_nvfp4(slot_hidden)
+            
+            # Quantize slot_hidden for GEMM
+            slot_x_fp4, slot_x_sf = quantize_activation_nvfp4(slot_hidden, l1_gs)
+            
+            tokens_per_expert = torch.bincount(sorted_ids, minlength=self.num_experts)[:self.num_experts].int()
+            expert_offsets = self._expert_offsets_buf
+            expert_offsets.zero_()
+            expert_offsets[1:self.num_experts + 1] = tokens_per_expert.cumsum(0)
+            
+            padded_tokens_per_expert = ((tokens_per_expert + 127) // 128) * 128
+            padded_expert_offsets = self._padded_expert_offsets_buf
+            padded_expert_offsets.zero_()
+            padded_expert_offsets[1:self.num_experts + 1] = padded_tokens_per_expert.cumsum(0)
+            
+            # Compute padded_dst (same as run())
+            row_indices = self._row_indices_buf[:num_slots]
+            expert_assign = torch.searchsorted(
+                expert_offsets[1:], row_indices, right=True
+            ).clamp(max=self.num_experts - 1)
+            local_row = row_indices - expert_offsets[expert_assign]
+            padded_dst = padded_expert_offsets[expert_assign] + local_row
+            
+            # Scatter x_fp4 into padded layout
+            padded_x_fp4 = self._shared_bufs['hidden_fp4']
+            padded_x_fp4.view(torch.uint8).zero_()
+            padded_x_fp4.view(torch.uint8)[padded_dst] = slot_x_fp4.view(torch.uint8)
+            
+            l1_scale_a = self._assemble_scales_cudagraph_safe(
+                slot_x_sf, expert_offsets[:self.num_experts + 1],
+                padded_expert_offsets,
+                self._padded_x_sf_buf_l1, self._per_expert_scale_bufs_l1
+            )
+            l1_gsa = torch.full((self.num_experts,), l1_gs, dtype=torch.float32, device=device)
+            
+            l1_out = run_nvfp4_grouped_gemm(
+                mat_a=padded_x_fp4, mat_b=self._l1_mat_b,
+                scale_a=l1_scale_a, scale_b=self._l1_scale_b,
+                expert_offsets=padded_expert_offsets[1:self.num_experts + 1],
+                global_scale_a=l1_gsa, global_scale_b=self._l1_gsb,
+            )
+            
+            # Extract real token outputs
+            l1_out_real = l1_out[padded_dst]
+            
+            # L2: get exact gs from SiLU(gate)*up
+            # De-interleave L1 output: with interleaved weights, L1 GEMM
+            # output has [gate]*4, [up]*4 pattern. De-interleave before splitting.
+            l1_deil = deinterleave_l1_weights(l1_out_real.unsqueeze(0).contiguous())[0]
+            gate = l1_deil[:, :self.intermediate_size]
+            up = l1_deil[:, self.intermediate_size:]
+            gate_silu = torch.nn.functional.silu(gate)
+            if self._swiglu_limit is not None:
+                gate_silu = gate_silu.clamp(max=self._swiglu_limit)
+                up = up.clamp(min=-self._swiglu_limit, max=self._swiglu_limit)
+            activated = gate_silu * up
+            _, _, l2_gs = quantize_to_nvfp4(activated)
+        
+        self._l1_activation_global_scale = l1_gs
+        self._l2_activation_global_scale = l2_gs
+        
+
+
+    def run(self, hidden_states, topk_weights, topk_ids, expert_indices=None):
+        """Forward: route tokens to experts, GEMM, combine.
+
+        Uses torch.library.custom_op (nvfp4::moe_gemm) so torch.compile
+        treats this as an opaque op. The custom op calls _run_impl internally.
+        """
+        if not hasattr(self, '_runner_id'):
+            self._runner_id = register_runner(self)
+        return nvfp4_moe_gemm(
+            hidden_states, topk_weights, topk_ids,
+            self._runner_id, self.hidden_size,
+        )
+
+    def _run_impl(self, hidden_states, topk_weights, topk_ids, expert_indices=None):
+        """Run the NVFP4 MoE forward pass.
+        
+        Handles global→local expert ID remapping for expert parallelism.
+        Fully cudagraph-safe: no CPU-GPU syncs, no dynamic shapes.
+        
+        Each expert's slots are padded to multiples of 128 for the GEMM.
+        expert_offsets is [0, padded_e0, padded_e0+padded_e1, ...].
+        scale_a is produced at those same offsets.
+        """
+        num_tokens = hidden_states.shape[0]
+        top_k = topk_ids.shape[1]
+        device = hidden_states.device
+        
+        self._ensure_stacked()
+        
+        # -- Remap global expert IDs to local IDs --
+        local_ids = topk_ids - self.experts_start_idx
+        local_mask = (local_ids >= 0) & (local_ids < self.num_experts)
+        safe_ids = local_ids.clamp(0, self.num_experts - 1)
+        safe_weights = topk_weights * local_mask.float()
+        
+        # -- Build slot mapping --
+        flat_ids = safe_ids.reshape(-1)
+        flat_weights = safe_weights.reshape(-1)
+        num_slots = num_tokens * top_k
+        token_indices = self._token_indices[:num_slots]
+        
+        sort_idx = flat_ids.argsort(stable=True)
+        sorted_ids = flat_ids[sort_idx]
+        sorted_weights = flat_weights[sort_idx]
+        sorted_token_ids = token_indices[sort_idx]
+        
+        # Expert offsets (real token counts)
+        tokens_per_expert = torch.bincount(sorted_ids, minlength=self.num_experts)[:self.num_experts].int()
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.zero_()
+        expert_offsets[1:self.num_experts + 1] = tokens_per_expert.cumsum(0)
+        
+        # Pad each expert to 128-row alignment (GPU-only computation)
+        padded_tokens_per_expert = ((tokens_per_expert + 127) // 128) * 128
+        padded_expert_offsets = self._padded_expert_offsets_buf
+        padded_expert_offsets.zero_()
+        padded_expert_offsets[1:self.num_experts + 1] = padded_tokens_per_expert.cumsum(0)
+        total_padded_slots = padded_expert_offsets[self.num_experts]
+        
+        # -- Gather hidden states into slot order, compute padded_dst --
+        slot_hidden = hidden_states[sorted_token_ids]
+        row_indices = self._row_indices_buf[:num_slots]
+        expert_assign = torch.searchsorted(
+            expert_offsets[1:], row_indices, right=True
+        ).clamp(max=self.num_experts - 1)
+        local_row = row_indices - expert_offsets[expert_assign]
+        padded_dst = padded_expert_offsets[expert_assign] + local_row
+        
+        # === L1: gate + up ===
+        # Fused amax + quantize: single kernel, zero CPU-GPU syncs.
+        # Computes amax on GPU → derives gsa → quantizes to NVFP4.
+        # gsa written to GPU buffer for GEMM global_scale_a.
+        if getattr(self, '_use_runtime_gsa', False):
+            from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+            slot_x_fp4, slot_x_sf, gsa_l1_gpu = quantize_nvfp4_gpu_fused(slot_hidden)
+            self._l1_gsa_buf.copy_(gsa_l1_gpu[:1].reshape(1))  # GPU → GPU, no sync
+        else:
+            slot_x_fp4, slot_x_sf = quantize_nvfp4_gpu(
+                slot_hidden, self._l1_activation_global_scale
+            )
+        # Scatter x_fp4 into padded layout for the GEMM
+        # Must scatter as uint8 (float4_e2m1fn_x2 doesn't support index_put)
+        padded_x_fp4 = self._shared_bufs['hidden_fp4']
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[padded_dst] = slot_x_fp4.view(torch.uint8)
+        
+        l1_scale_a = self._assemble_scales_cudagraph_safe(
+            slot_x_sf, expert_offsets[:self.num_experts + 1],
+            padded_expert_offsets,
+            self._padded_x_sf_buf_l1, self._per_expert_scale_bufs_l1
+        )
+        l1_gsa = self._l1_gsa_buf  # already filled by GPU compute (no .fill_ needed)
+        
+        if self._fused_swiglu:
+            # === Fused L1 GEMM + SwiGLU in kernel registers ===
+            l1_out = run_fused_swiglu_grouped_gemm(
+                mat_a=padded_x_fp4, mat_b=self._l1_mat_b,
+                scale_a=l1_scale_a, scale_b=self._l1_scale_b,
+                expert_offsets=padded_expert_offsets[1:self.num_experts + 1],
+                global_scale_a=l1_gsa, global_scale_b=self._l1_gsb,
+                swiglu_limit=self._swiglu_limit if self._swiglu_limit is not None else 0.0,
+            )
+            l1_out_real = l1_out[padded_dst]
+            # Fused deinterleave + amax + quantize: zero CPU syncs.
+            # Computes gsa from de-interleaved SwiGLU output on GPU,
+            # quantizes in the same kernel. Writes gsa to GPU buffer.
+            if getattr(self, '_use_runtime_gsa', False):
+                from dsv4.ops.quantize import deinterleave_amax_quantize_nvfp4_fused
+                slot_l2_x_fp4, slot_l2_x_sf, gsa_l2_gpu = deinterleave_amax_quantize_nvfp4_fused(
+                    l1_out_real, self.intermediate_size)
+                self._l2_gsa_buf.copy_(gsa_l2_gpu[:1].reshape(1))  # GPU → GPU, no sync
+            else:
+                slot_l2_x_fp4, slot_l2_x_sf = deinterleave_quantize_nvfp4_cuda(
+                    l1_out_real, self.intermediate_size, self._l2_activation_global_scale
+                )
+        else:
+            # === Non-fused L1 GEMM + PyTorch SiLU(gate)*up ===
+            l1_out = run_nvfp4_grouped_gemm(
+                mat_a=padded_x_fp4, mat_b=self._l1_mat_b,
+                scale_a=l1_scale_a, scale_b=self._l1_scale_b,
+                expert_offsets=padded_expert_offsets[1:self.num_experts + 1],
+                global_scale_a=l1_gsa, global_scale_b=self._l1_gsb,
+            )
+            l1_out_real = l1_out[padded_dst]
+            l1_deil = deinterleave_l1_weights(l1_out_real.unsqueeze(0).contiguous())[0]
+            gate = l1_deil[:, :self.intermediate_size]
+            up = l1_deil[:, self.intermediate_size:]
+            gate_silu = torch.nn.functional.silu(gate)
+            if self._swiglu_limit is not None:
+                gate_silu = gate_silu.clamp(max=self._swiglu_limit)
+                up = up.clamp(min=-self._swiglu_limit, max=self._swiglu_limit)
+            activated = gate_silu * up
+
+        # Compute runtime gsa for L2 from activated output (non-fused path)
+        # Fused amax + quantize: zero CPU syncs.
+        if not self._fused_swiglu and getattr(self, '_use_runtime_gsa', False):
+            from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+            slot_l2_x_fp4, slot_l2_x_sf, gsa_l2_gpu = quantize_nvfp4_gpu_fused(activated)
+            self._l2_gsa_buf.copy_(gsa_l2_gpu[:1].reshape(1))  # GPU → GPU, no sync
+        elif not self._fused_swiglu:
+            slot_l2_x_fp4, slot_l2_x_sf = quantize_nvfp4_gpu(
+                activated, self._l2_activation_global_scale
+            )
+        padded_activated_fp4 = self._shared_bufs['activated_fp4']
+        padded_activated_fp4.view(torch.uint8).zero_()
+        padded_activated_fp4.view(torch.uint8)[padded_dst] = slot_l2_x_fp4.view(torch.uint8)
+        
+        l2_scale_a = self._assemble_scales_cudagraph_safe(
+            slot_l2_x_sf, expert_offsets[:self.num_experts + 1],
+            padded_expert_offsets,
+            self._padded_x_sf_buf_l2, self._per_expert_scale_bufs_l2
+        )
+        l2_gsa = self._l2_gsa_buf  # already filled by GPU compute (no .fill_ needed)
+        
+        l2_out = run_nvfp4_grouped_gemm(
+            mat_a=padded_activated_fp4, mat_b=self._l2_mat_b,
+            scale_a=l2_scale_a, scale_b=self._l2_scale_b,
+            expert_offsets=padded_expert_offsets[1:self.num_experts + 1],
+            global_scale_a=l2_gsa, global_scale_b=self._l2_gsb,
+        )
+        
+        l2_out_real = l2_out[padded_dst]
+        
+        # === Scatter -> final output ===
+        y = self._output_buf[:num_tokens]
+        y.zero_()
+        weighted_out = l2_out_real * sorted_weights.unsqueeze(1).to(l2_out_real.dtype)
+        y.scatter_add_(
+            0,
+            sorted_token_ids.unsqueeze(1).expand(-1, self.hidden_size),
+            weighted_out,
+        )
+        
+        return y

dsv4/_archive/layers/router.py

@@ -0,0 +1,345 @@
+"""DSV4 Router — token-to-expert assignment.
+
+Two routing modes that share an output shape:
+  - 'dense': sqrt(softplus(X @ W_gate)) + per-expert bias, top-k selection.
+             Used by MoE layers 3+ (the bulk of the network).
+  - 'hash':  deterministic per-token-ID lookup, uniform weights.
+             Used by the first 3 MoE layers per DSV4 §2.1.
+
+Both modes produce (topk_weights, topk_ids) suitable for direct
+consumption by Nvfp4MoE.run().
+
+CUDA-graph-compatible: pre-allocated buffers, no CPU-GPU syncs.
+Selection between modes is by layer_idx at construction time —
+the kernel path is fixed once the Router is built so the dispatch
+is constant-folded by torch.compile.
+"""
+
+from __future__ import annotations
+from typing import Optional, Literal
+import torch
+
+from dsv4.ops.router import (
+    register_router,
+    dense_router_op,
+    hash_router_op,
+)
+
+
+RouterMode = Literal["dense", "hash"]
+
+
+class Router:
+    """DSV4 expert router.
+
+    Per the DeepSeek-V4 paper (§2.1):
+      - Affinity activation is sqrt(softplus(·)), replacing V3's sigmoid(·).
+      - Auxiliary-loss-free strategy: a learned per-expert bias (loaded
+        from checkpoint, frozen at inference) is added to the activation
+        for SELECTION only. The actual gating weight applied to expert
+        outputs uses the UNBIASED activation.
+      - First 3 MoE layers use Hash routing (Roller et al. 2021): a
+        precomputed [vocab_size, k] LUT mapping token IDs to expert IDs.
+        No gate GEMM is performed.
+      - Sequence-wise balance loss is training-only; not applied here.
+
+    Parameters
+    ----------
+    hidden_size : int
+        Model hidden dimension. Must match W_gate's K dimension.
+    num_experts : int
+        Total routed experts (Flash: 256, Pro: 384). Shared experts are
+        handled separately by Nvfp4SharedExpert.
+    top_k : int
+        Experts activated per token. DSV4 uses 6.
+    routed_scaling_factor : float
+        Post-renormalization scale on gating weights. DSV3 used 2.5;
+        verify against the V4 checkpoint config — may be per-layer.
+    mode : {'dense', 'hash'}
+        Routing strategy. Decided at construction; cannot change at runtime.
+    vocab_size : int, optional
+        Required when mode='hash'. The LUT is [vocab_size, top_k] int32.
+    max_num_tokens : int
+        Upper bound on N for pre-allocated buffer sizing.
+    device : str
+        CUDA device.
+    """
+
+    def __init__(
+        self,
+        hidden_size: int,
+        num_experts: int,
+        top_k: int = 6,
+        routed_scaling_factor: float = 2.5,
+        *,
+        mode: RouterMode,
+        vocab_size: Optional[int] = None,
+        max_num_tokens: int = 8192,
+        device: str = "cuda",
+    ):
+        if mode == "hash" and vocab_size is None:
+            raise ValueError("vocab_size is required when mode='hash'")
+        if mode not in ("dense", "hash"):
+            raise ValueError(f"unknown router mode: {mode!r}")
+
+        self.hidden_size = hidden_size
+        self.num_experts = num_experts
+        self.top_k = top_k
+        self.routed_scaling_factor = routed_scaling_factor
+        self.mode = mode
+        self.vocab_size = vocab_size
+        self.max_num_tokens = max_num_tokens
+        self.device = device
+
+        # ---- Parameters (filled by load_weights / finalize_weights) ----
+        # Dense mode — fused NVFP4 kernel (single-kernel, preferred):
+        #   gate_weight: raw NVFP4 gate weight tensor [K_packed, E_packed] uint8
+        #   gate_weight_scale: weight scale [K_sf, E_sf] FP8 E4M3
+        #   gate_ws2: weight_scale_2 (global scale base)
+        #   gate_input_scale: input_scale (activation global scale base)
+        # Dense mode — 2-kernel NVFP4 path (fallback):
+        #   gate_lin: Nvfp4Linear for the gate projection
+        # Dense mode — BF16 fallback:
+        #   W_gate: BF16 weight for cuBLAS when NVFP4 scales not available
+        # Hash mode:
+        #   hash_lut: [vocab_size, top_k] int32 — precomputed expert IDs.
+        self.gate_weight = None        # Raw NVFP4 weight for fused kernel
+        self.gate_weight_scale = None   # FP8 E4M3 scale for fused kernel
+        self.gate_ws2 = None            # weight_scale_2 for fused kernel
+        self.gate_input_scale = None    # input_scale for fused kernel
+        self.gate_lin = None            # Nvfp4Linear for 2-kernel NVFP4 path
+        self.W_gate: Optional[torch.Tensor] = None  # BF16 fallback
+        self.e_bias: Optional[torch.Tensor] = None
+        self.hash_lut: Optional[torch.Tensor] = None
+
+        # ---- Pre-allocated output buffers (cudagraph-safe) ----
+        self._topk_weights_buf: Optional[torch.Tensor] = None
+        self._topk_ids_buf: Optional[torch.Tensor] = None
+
+        # Runner ID assigned on first call (see custom_op pattern).
+        self._runner_id: Optional[int] = None
+
+    # ------------------------------------------------------------------
+    # Weight loading
+    # ------------------------------------------------------------------
+    def load_weights(
+        self,
+        W_gate: Optional[torch.Tensor] = None,
+        e_bias: Optional[torch.Tensor] = None,
+        hash_lut: Optional[torch.Tensor] = None,
+    ) -> None:
+        """Populate router parameters from a checkpoint shard.
+
+        Dense mode expects (W_gate, e_bias). Hash mode expects (hash_lut).
+        Mismatches with self.mode raise immediately — these errors are
+        nearly always loader bugs and silent acceptance would mask them.
+        """
+        if self.mode == "dense":
+            if e_bias is None:
+                raise ValueError("dense router needs e_bias")
+            assert e_bias.shape == (self.num_experts,), \
+                f"e_bias shape {tuple(e_bias.shape)} != ({self.num_experts},)"
+            self.e_bias = e_bias.to(device=self.device, dtype=torch.float32)
+            if W_gate is not None:
+                self.W_gate = W_gate.to(device=self.device, dtype=torch.bfloat16)
+            # gate_lin is set separately via load_nvfp4_gate()
+        else:  # hash
+            if hash_lut is None:
+                raise ValueError("hash router needs hash_lut")
+            assert hash_lut.shape == (self.vocab_size, self.top_k), \
+                f"hash_lut shape {tuple(hash_lut.shape)} != " \
+                f"{(self.vocab_size, self.top_k)}"
+            assert (hash_lut >= 0).all() and (hash_lut < self.num_experts).all(), \
+                "hash_lut contains out-of-range expert IDs"
+            self.hash_lut = hash_lut.to(device=self.device, dtype=torch.int32)
+
+    def load_nvfp4_gate(self, gate_lin) -> None:
+        """Set the NVFP4 gate linear layer (2-kernel path).
+
+        Called by the single_shot after constructing the Nvfp4Linear
+        from checkpoint NVFP4 scales. When set, _run_dense_impl uses
+        the production NVFP4 GEMM path instead of BF16 cuBLAS.
+        """
+        self.gate_lin = gate_lin
+
+    def load_nvfp4_fused_gate(self, gate_weight, gate_weight_scale,
+                               gate_ws2, gate_input_scale,
+                               gate_weight_bf16=None) -> None:
+        """Set raw NVFP4 gate tensors and create Nvfp4Linear for production GEMM."""
+        self.gate_weight = gate_weight.to(device=self.device)
+        self.gate_weight_scale = gate_weight_scale.to(device=self.device)
+        self.gate_ws2 = gate_ws2.to(device=self.device) if gate_ws2 is not None else None
+        self.gate_input_scale = gate_input_scale.to(self.device)
+
+        # Create Nvfp4Linear from BF16 weight (handles layout correctly)
+        if gate_weight_bf16 is not None:
+            from dsv4.layers.linear import Nvfp4Linear
+            from dsv4.ops.quantize import quantize_to_nvfp4
+            E = gate_weight_bf16.shape[0]
+            gate_lin = Nvfp4Linear(in_features=self.hidden_size, out_features=E, device=self.device)
+            g_fp4, g_sf, g_gs = quantize_to_nvfp4(gate_weight_bf16.bfloat16().to(self.device))
+            gate_lin.fp4 = [g_fp4]
+            gate_lin.sf = [g_sf]
+            gate_lin.gs = [g_gs]
+            ws2_val = gate_ws2.float().item() if gate_ws2.numel() == 1 else gate_ws2.float().mean().item()
+            gate_lin.ws2 = [torch.tensor([ws2_val], device=self.device, dtype=torch.float32)]
+            gate_lin._activation_global_scale = gate_input_scale.float().item() if gate_input_scale.numel() == 1 else gate_input_scale.float().mean().item()
+            gate_lin._use_runtime_gsa = True  # compute gsa from actual input to avoid E4M3 overflow
+            gate_lin.finalize_weights()
+            self.gate_lin = gate_lin
+
+    def finalize_weights(self) -> None:
+        """Allocate output buffers and JIT-compile the routing kernel.
+
+        Mirrors the finalize_weights() pattern in Nvfp4Linear: a one-time
+        setup step called after all parameters are loaded. Triggers
+        kernel compilation so the first forward isn't paying that cost.
+        """
+        self._topk_weights_buf = torch.empty(
+            self.max_num_tokens, self.top_k,
+            dtype=torch.float32, device=self.device,
+        )
+        self._topk_ids_buf = torch.empty(
+            self.max_num_tokens, self.top_k,
+            dtype=torch.int32, device=self.device,
+        )
+
+        # Eager JIT — dispatcher knows our mode and triggers the right
+        # kernel's compile path. See dsv4/ops/router.py.
+        from dsv4.ops.router import warmup_router_compilation
+        warmup_router_compilation(self)
+
+    # ------------------------------------------------------------------
+    # Forward
+    # ------------------------------------------------------------------
+    def __call__(
+        self,
+        hidden_states: torch.Tensor,
+        token_ids: Optional[torch.Tensor] = None,
+    ) -> tuple[torch.Tensor, torch.Tensor]:
+        """Produce (topk_weights, topk_ids) for downstream Nvfp4MoE.
+
+        Parameters
+        ----------
+        hidden_states : Tensor [N, hidden_size] bfloat16
+            Required for dense mode. Ignored for hash mode (kept in the
+            signature so the call site is mode-agnostic).
+        token_ids : Tensor [N] int32, optional
+            Required for hash mode. Ignored for dense mode.
+
+        Returns
+        -------
+        topk_weights : Tensor [N, top_k] float32
+        topk_ids     : Tensor [N, top_k] int32
+
+        Notes
+        -----
+        Both outputs are views into pre-allocated buffers — do not retain
+        them across router calls. Nvfp4MoE consumes them immediately,
+        which matches its existing contract.
+        """
+        if self._topk_weights_buf is None:
+            raise RuntimeError("Router.finalize_weights() not called")
+
+        if self.mode == "dense":
+            if hidden_states is None:
+                raise ValueError("dense router requires hidden_states")
+            return self._run_dense(hidden_states)
+        else:
+            if token_ids is None:
+                raise ValueError("hash router requires token_ids")
+            return self._run_hash(token_ids)
+
+    # ------------------------------------------------------------------
+    # Mode-specific dispatch — each routes through a torch.library.custom_op
+    # so Dynamo / torch.compile treats the kernel as opaque.
+    # ------------------------------------------------------------------
+    def _run_dense(self, hidden_states: torch.Tensor):
+        if self._runner_id is None:
+            self._runner_id = register_router(self)
+        return dense_router_op(
+            hidden_states,
+            self._runner_id,
+            self.num_experts,
+            self.top_k,
+        )
+
+    def _run_hash(self, token_ids: torch.Tensor):
+        if self._runner_id is None:
+            self._runner_id = register_router(self)
+        return hash_router_op(
+            token_ids,
+            self._runner_id,
+            self.top_k,
+        )
+
+    # ------------------------------------------------------------------
+    # Called by the custom_op dispatch in dsv4/ops/router.py — not by user code.
+    # ------------------------------------------------------------------
+    def _run_dense_impl(self, hidden_states: torch.Tensor):
+        """Hot-path: fused NVFP4, 2-kernel NVFP4, or BF16 fallback.
+
+        Priority:
+        1. Fused NVFP4 kernel (single-kernel GEMM + router epilogue)
+        2. 2-kernel NVFP4 path (Nvfp4Linear + activation_topk)
+        3. BF16 cuBLAS fallback
+        """
+        N = hidden_states.shape[0]
+        out_w = self._topk_weights_buf[:N]
+        out_ids = self._topk_ids_buf[:N]
+        if self.gate_lin is not None:
+            # NVFP4 production GEMM path (proven Nvfp4Linear)
+            from dsv4.kernels.router import dense_router_dispatch_nvfp4
+            dense_router_dispatch_nvfp4(
+                hidden_states=hidden_states,
+                gate_lin=self.gate_lin,
+                e_bias=self.e_bias,
+                routed_scaling_factor=self.routed_scaling_factor,
+                top_k=self.top_k,
+                out_weights=out_w,
+                out_ids=out_ids,
+            )
+        elif self.gate_weight is not None:
+            # Fused NVFP4 path (gate_lin was not created)
+            # Fall back to BF16
+            from dsv4.kernels.router import dense_router_dispatch
+            dense_router_dispatch(
+                hidden_states=hidden_states,
+                W_gate=self.W_gate,
+                e_bias=self.e_bias,
+                routed_scaling_factor=self.routed_scaling_factor,
+                top_k=self.top_k,
+                out_weights=out_w,
+                out_ids=out_ids,
+            )
+        else:
+            from dsv4.kernels.router import dense_router_dispatch
+            dense_router_dispatch(
+                hidden_states=hidden_states,
+                W_gate=self.W_gate,
+                e_bias=self.e_bias,
+                routed_scaling_factor=self.routed_scaling_factor,
+                top_k=self.top_k,
+                out_weights=out_w,
+                out_ids=out_ids,
+            )
+        return out_w, out_ids
+
+    def _run_hash_impl(self, token_ids: torch.Tensor):
+        """Hot-path entry into the hash gather kernel.
+
+        Implementation lives in dsv4/kernels/cuda/hash_router.cu via the
+        wrapper in dsv4/ops/router.py.
+        """
+        from dsv4.kernels.router import hash_router_dispatch
+        N = token_ids.shape[0]
+        out_w = self._topk_weights_buf[:N]
+        out_ids = self._topk_ids_buf[:N]
+        hash_router_dispatch(
+            token_ids=token_ids,
+            hash_lut=self.hash_lut,
+            top_k=self.top_k,
+            out_weights=out_w,  # filled with 1/k
+            out_ids=out_ids,
+        )
+        return out_w, out_ids

dsv4/_archive/layers/shared_expert.py

@@ -0,0 +1,409 @@
+"""CuTeDSL Shared Expert Pipeline
+
+NVFP4 inference for DeepSeek V4 shared experts.
+Uses ScaledGroupedGemmKernel with num_groups=1.
+
+Pipeline:
+  1. Quantize activation: BF16 → NVFP4 (using warmup gs)
+  2. L1 GEMM: NVFP4_act × NVFP4_weight(gate_up) → BF16
+  3. SiLU(gate) * up → BF16
+  4. Re-quantize: BF16 → NVFP4 (using warmup gs)
+  5. L2 GEMM: NVFP4_act × NVFP4_weight(down) → BF16
+
+Unlike MoE, there's no routing, no scatter, no expert offsets.
+All tokens go through the same expert (the shared expert).
+Scale assembly is just: quantize activation → pad to 128-row alignment → Blackwell swizzle.
+
+CUDA-graph-compatible: all buffers pre-allocated, no CPU-GPU syncs,
+no dynamic shapes. Padding rows are zeros that contribute nothing to GEMM output.
+"""
+
+import torch
+
+from dsv4.ops.quantize import (
+    quantize_activation_nvfp4,
+    quantize_to_nvfp4,
+)
+from dsv4.ops.layouts import (
+    make_b_k_major,
+    interleave_l1_weights,
+    deinterleave_l1_weights,
+)
+from dsv4.ops.gemm_runner import (
+    run_nvfp4_grouped_gemm,
+    run_fused_swiglu_grouped_gemm,
+)
+from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+from dsv4.kernels.gemm.grouped import (
+    ceil_div as cutedsl_ceil_div,
+    pad_and_swizzle_single,
+)
+
+
+class _SharedExpertApply(torch.autograd.Function):
+    """Custom autograd function to make CuTeDSL runner opaque to torch.compile."""
+    @staticmethod
+    def forward(ctx, runner, hidden_states):
+        return runner._run_impl(hidden_states)
+
+
+class Nvfp4SharedExpert:
+    """NVFP4 shared expert runner using CuTeDSL GEMM (num_groups=1).
+
+    CUDA-graph-compatible: all buffers pre-allocated, no CPU-GPU syncs.
+    """
+
+    def __init__(
+        self,
+        hidden_size: int,
+        intermediate_size: int,
+        max_num_tokens: int = 8192,
+        device: str = "cuda",
+        swiglu_limit: float = 10.0,
+    ):
+        self.hidden_size = hidden_size
+        self.intermediate_size = intermediate_size
+        self.max_num_tokens = max_num_tokens
+        self.device = device
+        self.swiglu_limit = swiglu_limit
+        self._fused_swiglu = False  # Set via set_fused_swiglu()
+
+        # Weights (set after construction, then call finalize_weights)
+        self.l1_fp4 = None
+        self.l1_sf = None
+        self.l1_gs = None
+        self.l2_fp4 = None
+        self.l2_sf = None
+        self.l2_gs = None
+        # weight_scale_2 per layer (scalar, folded into global_scale_b in finalize_weights)
+        self.l1_ws2 = None
+        self.l2_ws2 = None
+
+        # Processed weights (set by finalize_weights)
+        self._l1_mat_b = None
+        self._l2_mat_b = None
+        self._l1_scale_b = None
+        self._l2_scale_b = None
+        self._l1_gsb = None
+        self._l2_gsb = None
+
+        # Activation global scales (set by compute_activation_global_scales)
+        self._l1_activation_global_scale = 1.0 / (6.0 * 448.0)
+        self._l2_activation_global_scale = 1.0 / (6.0 * 448.0)
+
+        # Pre-allocated cudagraph buffers (set in _allocate_buffers)
+        self._padded_x_fp4_buf_l1 = None
+        self._padded_x_sf_buf_l1 = None
+        self._padded_x_fp4_buf_l2 = None
+        self._padded_x_sf_buf_l2 = None
+        self._l1_gsa_buf = None
+        self._l2_gsa_buf = None
+        self._expert_offsets_buf = None
+        self._buffers_allocated = False
+
+    def set_swiglu_limit(self, limit: float):
+        self.swiglu_limit = limit
+
+    def set_fused_swiglu(self, enabled: bool):
+        """Enable fused L1 GEMM + SwiGLU kernel (1-group variant of MoE fused kernel)."""
+        self._fused_swiglu = enabled
+
+    def finalize_weights(self):
+        """Process weights for CuTeDSL GEMM. Must be called after setting l1/l2 weights."""
+        # Convert uint8 checkpoint weights to float4_e2m1fn_x2 view
+        l1_view = [w.view(torch.float4_e2m1fn_x2) if w.dtype == torch.uint8 else w for w in self.l1_fp4]
+        l2_view = [w.view(torch.float4_e2m1fn_x2) if w.dtype == torch.uint8 else w for w in self.l2_fp4]
+        # Checkpoint weight is (N_packed, K_packed), make_b_k_major expects (E, K_packed, N_packed)
+        l1_stacked = torch.stack(l1_view).permute(0, 2, 1).contiguous()
+        l2_stacked = torch.stack(l2_view).permute(0, 2, 1).contiguous()
+        # P1: Interleave L1 gate/up weights for fused SwiGLU kernel compatibility.
+        # The fused kernel's SwiGLU epilogue expects granularity-8 interleaved gate/up.
+        # The unfused path (if _fused_swiglu=False) deinterleaves the GEMM output before splitting.
+        if self._fused_swiglu:
+            l1_stacked = interleave_l1_weights(l1_stacked, granularity_bf16=8)
+        # Stack weights and convert to K-major
+        self._l1_mat_b = make_b_k_major(l1_stacked)  # (1, K_packed, N_packed)
+        self._l2_mat_b = make_b_k_major(l2_stacked)
+        # Checkpoint scale is (N_packed, K_sf) — use assemble_raw_scales_2d3d_3d_side
+        from dsv4.ops.layouts import assemble_raw_scales_2d3d_3d_side
+        self._l1_scale_b = assemble_raw_scales_2d3d_3d_side(self.l1_sf)
+        self._l2_scale_b = assemble_raw_scales_2d3d_3d_side(self.l2_sf)
+        self._l1_gsb = torch.tensor(self.l1_gs, dtype=torch.float32, device=self.device)
+        self._l2_gsb = torch.tensor(self.l2_gs, dtype=torch.float32, device=self.device)
+
+        # Fold weight_scale_2 into global_scale_b
+        # gsb = input_scale * weight_scale_2
+        if self.l1_ws2 is not None:
+            for i, ws2 in enumerate(self.l1_ws2):
+                if ws2 is not None:
+                    self._l1_gsb[i] *= ws2.float().item()
+        if self.l2_ws2 is not None:
+            for i, ws2 in enumerate(self.l2_ws2):
+                if ws2 is not None:
+                    self._l2_gsb[i] *= ws2.float().item()
+
+        # Free raw weights
+        self.l1_fp4 = None
+        self.l1_sf = None
+        self.l1_gs = None
+        self.l2_fp4 = None
+        self.l2_sf = None
+        self.l2_gs = None
+        self.l1_ws2 = None
+        self.l2_ws2 = None
+
+    def _allocate_buffers(self):
+        """Pre-allocate all buffers at max size for cudagraph compatibility."""
+        max_rows = cutedsl_ceil_div(self.max_num_tokens, 128) * 128  # pad to 128
+
+        # L1: hidden_size packed, L2: intermediate_size packed
+        self._padded_x_fp4_buf_l1 = torch.zeros(
+            max_rows, self.hidden_size // 2, dtype=torch.uint8, device=self.device
+        ).view(torch.float4_e2m1fn_x2)
+        self._padded_x_fp4_buf_l2 = torch.zeros(
+            max_rows, self.intermediate_size // 2, dtype=torch.uint8, device=self.device
+        ).view(torch.float4_e2m1fn_x2)
+
+        # Padded scale buffers (need same padded dimensions as pad_and_swizzle_single produces)
+        K_sf_l1 = cutedsl_ceil_div(self.hidden_size, 16)
+        padded_cols_l1 = cutedsl_ceil_div(K_sf_l1, 4) * 4
+        K_sf_l2 = cutedsl_ceil_div(self.intermediate_size, 16)
+        padded_cols_l2 = cutedsl_ceil_div(K_sf_l2, 4) * 4
+        self._padded_x_sf_buf_l1 = torch.zeros(
+            max_rows, padded_cols_l1, dtype=torch.float16, device=self.device
+        ).to(torch.float8_e4m3fn)
+        self._padded_x_sf_buf_l2 = torch.zeros(
+            max_rows, padded_cols_l2, dtype=torch.float16, device=self.device
+        ).to(torch.float8_e4m3fn)
+
+        # Global scale buffers
+        self._l1_gsa_buf = torch.zeros(1, dtype=torch.float32, device=self.device)
+        self._l2_gsa_buf = torch.zeros(1, dtype=torch.float32, device=self.device)
+
+        # Expert offsets for num_groups=1: just [num_tokens_padded]
+        # The GEMM expects expert_offsets as (num_experts,) cumulative offsets
+        # For 1 expert: offsets = [num_tokens] (just one element)
+        self._expert_offsets_buf = torch.zeros(1, dtype=torch.int32, device=self.device)
+
+        self._buffers_allocated = True
+
+    def _ensure_initialized(self):
+        """Lazily initialize stacked weights and buffers."""
+        if self._l1_mat_b is None:
+            self.finalize_weights()
+        if not self._buffers_allocated:
+            self._allocate_buffers()
+
+    def _assemble_scales_single_group(self, x_sf, num_tokens, padded_x_sf_buf):
+        """Assemble 2D-side activation scales for num_groups=1.
+
+        For a single group, scale assembly is just:
+        1. Copy x_sf into a correctly-sized buffer (padded to 128 rows, 4 cols)
+        2. Apply pad_and_swizzle_single (Blackwell swizzle)
+        3. Reshape back to 2D (kernel expects 2D scale_a)
+
+        The padded buffer must be sized exactly for 128-aligned num_tokens,
+        NOT the max_num_tokens buffer (which would be way too large).
+        """
+        num_rows, num_cols = x_sf.shape
+        padded_rows = cutedsl_ceil_div(num_rows, 128) * 128
+        padded_cols = cutedsl_ceil_div(num_cols, 4) * 4
+
+        # Use a temp buffer sized for this exact token count
+        buf = torch.zeros(padded_rows, padded_cols, dtype=torch.float16, device=x_sf.device).to(torch.float8_e4m3fn)
+        buf[:num_rows, :num_cols] = x_sf
+        swizzled_flat = pad_and_swizzle_single(buf)
+        return swizzled_flat.reshape(padded_rows, padded_cols)
+
+    def compute_activation_global_scales(self, hidden_states_sample):
+        """Compute activation global scales from a warmup forward pass.
+
+        Called BEFORE cudagraph capture. Uses quantize_to_nvfp4 to get
+        the exact global_scale from the data, then runs L1 to compute
+        L2 gs from actual SiLU(gate)*up output.
+        """
+        self._ensure_initialized()
+
+        with torch.no_grad():
+            # L1: exact gs from quantize_to_nvfp4
+            _, _, l1_gs = quantize_to_nvfp4(hidden_states_sample)
+            self._l1_activation_global_scale = l1_gs
+
+            # Run L1 GEMM to get intermediate for L2 gs
+            num_tokens = hidden_states_sample.shape[0]
+            l1_out = self._run_l1(hidden_states_sample)
+            if l1_out is not None and not torch.isnan(l1_out).any():
+                gate = l1_out[:, :self.intermediate_size]
+                up = l1_out[:, self.intermediate_size:]
+                if self.swiglu_limit is not None:
+                    gate = gate.clamp(max=self.swiglu_limit)
+                    up = up.clamp(min=-self.swiglu_limit, max=self.swiglu_limit)
+                activated = torch.nn.functional.silu(gate) * up
+                _, _, l2_gs = quantize_to_nvfp4(activated)
+                self._l2_activation_global_scale = l2_gs
+
+
+
+    def _run_l1_fused(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        """Fused L1 GEMM + SwiGLU + clamp — single kernel launch (1-group variant of MoE fused kernel)."""
+        num_tokens = hidden_states.shape[0]
+        x_bf16 = hidden_states.reshape(num_tokens, self.hidden_size)
+
+        # Quantize activation to NVFP4 (fused amax + quantize)
+        if getattr(self, '_use_runtime_gsa', False):
+            from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+            x_fp4, x_sf, gsa_l1_gpu = quantize_nvfp4_gpu_fused(x_bf16)
+            self._l1_gsa_buf.copy_(gsa_l1_gpu[:1].reshape(1))  # GPU → GPU
+        else:
+            from dsv4.ops.quantize import quantize_activation_nvfp4
+            x_fp4, x_sf = quantize_activation_nvfp4(x_bf16, self._l1_activation_global_scale)
+
+        # Padded buffer setup for 1-group GEMM
+        padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+        padded_x_fp4 = self._padded_x_fp4_buf_l1
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[:num_tokens] = x_fp4.view(torch.uint8)
+
+        # Assemble A-side scales
+        scale_a = self._assemble_scales_single_group(x_sf, num_tokens, self._padded_x_sf_buf_l1)
+
+        # Expert offsets: [padded_rows] for 1 group (int32, pre-allocated)
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.fill_(padded_rows)
+
+        # Global scales — GPU-computed gsa already in _l1_gsa_buf (no CPU sync)
+        gsa = self._l1_gsa_buf
+
+        # Run fused GEMM + SwiGLU
+        l1_out = run_fused_swiglu_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._l1_mat_b,
+            scale_a=scale_a,
+            scale_b=self._l1_scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=gsa,
+            global_scale_b=self._l1_gsb,
+            swiglu_limit=self.swiglu_limit if self.swiglu_limit is not None else 0.0,
+        )
+        l1_out_real = l1_out[:num_tokens]  # (num_tokens, 2*intermediate) BF16, interleaved [silu(gate), silu(gate)*up]
+        # Deinterleave to separate gate and up, then take up half (SwiGLU result)
+        l1_deil = deinterleave_l1_weights(l1_out_real.unsqueeze(0).contiguous())[0]  # (num_tokens, 2*intermediate) deinterleaved
+        intermediate = l1_deil[:, self.intermediate_size:]  # up half = silu(gate)*up
+        return intermediate  # (num_tokens, intermediate_size) BF16
+
+    def _run_l1(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        """L1 GEMM: activation × gate_up_weight → BF16."""
+        num_tokens = hidden_states.shape[0]
+        padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+
+        # Fused amax + quantize: zero CPU syncs.
+        if getattr(self, '_use_runtime_gsa', False):
+            from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+            x_fp4, x_sf, gsa_l1_gpu = quantize_nvfp4_gpu_fused(hidden_states)
+            self._l1_gsa_buf.copy_(gsa_l1_gpu[:1].reshape(1))  # GPU → GPU, no sync
+        else:
+            x_fp4, x_sf = quantize_activation_nvfp4(
+                hidden_states, self._l1_activation_global_scale
+            )
+
+        # Scatter x_fp4 into padded buffer
+        padded_x_fp4 = self._padded_x_fp4_buf_l1
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[:num_tokens] = x_fp4.view(torch.uint8)
+
+        # Assemble A-side scales
+        scale_a = self._assemble_scales_single_group(x_sf, num_tokens, self._padded_x_sf_buf_l1)
+
+        # Expert offsets: [padded_rows] for 1 group
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.fill_(padded_rows)
+
+        # Global scales — GPU-computed gsa already in _l1_gsa_buf (no CPU sync)
+        gsa = self._l1_gsa_buf
+
+        # Run GEMM
+        out = run_nvfp4_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._l1_mat_b,
+            scale_a=scale_a,
+            scale_b=self._l1_scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=gsa,
+            global_scale_b=self._l1_gsb,
+        )
+
+        # Extract real token outputs
+        return out[:num_tokens]
+
+    def _run_l2(self, intermediate: torch.Tensor) -> torch.Tensor:
+        """L2 GEMM: intermediate × down_weight → BF16."""
+        num_tokens = intermediate.shape[0]
+        padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+
+        # Fused amax + quantize: zero CPU syncs.
+        if getattr(self, '_use_runtime_gsa', False):
+            from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+            x_fp4, x_sf, gsa_l2_gpu = quantize_nvfp4_gpu_fused(intermediate)
+            self._l2_gsa_buf.copy_(gsa_l2_gpu[:1].reshape(1))  # GPU → GPU, no sync
+        else:
+            x_fp4, x_sf = quantize_activation_nvfp4(
+                intermediate, self._l2_activation_global_scale
+            )
+
+        # Scatter into padded buffer
+        padded_x_fp4 = self._padded_x_fp4_buf_l2
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[:num_tokens] = x_fp4.view(torch.uint8)
+
+        # Assemble A-side scales
+        scale_a = self._assemble_scales_single_group(x_sf, num_tokens, self._padded_x_sf_buf_l2)
+
+        # Expert offsets
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.fill_(padded_rows)
+
+        # Global scales — GPU-computed gsa already in _l2_gsa_buf (no CPU sync)
+        gsa = self._l2_gsa_buf
+
+        # Run GEMM
+        out = run_nvfp4_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._l2_mat_b,
+            scale_a=scale_a,
+            scale_b=self._l2_scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=gsa,
+            global_scale_b=self._l2_gsb,
+        )
+
+        return out[:num_tokens]
+
+    def run(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        """Full shared expert forward: L1 → SiLU → L2 → output."""
+        return _SharedExpertApply.apply(self, hidden_states)
+
+    def _run_impl(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        """Actual implementation — called via custom autograd to be torch.compile-safe."""
+        self._ensure_initialized()
+
+        if self._fused_swiglu:
+            # P1: Fused L1 GEMM + SwiGLU + clamp in one kernel launch
+            intermediate = self._run_l1_fused(hidden_states)
+        else:
+            l1_out = self._run_l1(hidden_states)
+            if l1_out.shape[1] < 2 * self.intermediate_size:
+                print(f"  WARNING: l1_out shape {l1_out.shape} < expected (N, {2*self.intermediate_size})", flush=True)
+
+            gate = l1_out[:, :self.intermediate_size]
+            up = l1_out[:, self.intermediate_size:]
+            if torch.isnan(l1_out).any():
+                print(f"  SE L1 NaN: l1_out nan at {torch.isnan(l1_out).sum().item()} / {l1_out.numel()} positions, shape={l1_out.shape}", flush=True)
+            if torch.isnan(gate).any() or torch.isnan(up).any():
+                print(f"  SE gate nan={torch.isnan(gate).any().item()} up nan={torch.isnan(up).any().item()}", flush=True)
+            if self.swiglu_limit is not None:
+                gate = gate.clamp(max=self.swiglu_limit)
+                up = up.clamp(min=-self.swiglu_limit, max=self.swiglu_limit)
+            intermediate = torch.nn.functional.silu(gate) * up
+
+        output = self._run_l2(intermediate)
+        return output

dsv4/_archive/ops/custom_ops.py

@@ -0,0 +1,138 @@
+"""torch.library.custom_op wrappers for CuTeDSL NVFP4 kernels.
+
+Dynamo (torch.compile fullgraph) cannot trace through CuTeDSL internals
+(JIT compilation, cute.compile, etc.). By wrapping the runner calls in
+torch.library.custom_op, Dynamo treats them as opaque black boxes.
+
+This is the correct approach per PyTorch's extensibility model:
+- custom_op is the supported way to make Dynamo skip tracing
+- autograd.Function does NOT work reliably with fullgraph mode
+- The runner's _run_impl is already cudagraph-safe
+
+The registry pattern: custom ops can only take tensor/scalar arguments.
+We store runners in a global dict keyed by integer ID, and pass the ID
+as an int parameter. During Dynamo tracing, the fake impl returns a
+correctly-shaped tensor without touching the runner. During execution,
+the real impl looks up the runner and calls _run_impl.
+"""
+
+import torch
+
+# ---------------------------------------------------------------------------
+# Runner registry — maps integer IDs to runner objects
+# ---------------------------------------------------------------------------
+_next_runner_id = 0
+_runner_registry: dict[int, object] = {}
+
+
+def register_runner(runner) -> int:
+    """Register a CuTeDSL runner and return its integer ID."""
+    global _next_runner_id
+    rid = _next_runner_id
+    _next_runner_id += 1
+    _runner_registry[rid] = runner
+    return rid
+
+
+def get_runner(rid: int):
+    """Look up a runner by ID."""
+    return _runner_registry[rid]
+
+
+# ---------------------------------------------------------------------------
+# NVFP4 Linear GEMM custom op (single linear layer)
+# ---------------------------------------------------------------------------
+@torch.library.custom_op("nvfp4::linear_gemm", mutates_args=())
+def nvfp4_linear_gemm(
+    x: torch.Tensor,
+    runner_id: int,
+    out_features: int,
+) -> torch.Tensor:
+    """Opaque NVFP4 linear GEMM for torch.compile.
+
+    Args:
+        x: (M, K) BF16 input
+        runner_id: integer key into the runner registry
+        out_features: output dimension (for shape inference)
+    Returns:
+        (M, out_features) BF16 output
+    """
+    runner = get_runner(runner_id)
+    return runner._run_impl(x)
+
+
+@nvfp4_linear_gemm.register_fake
+def _(x, runner_id, out_features):
+    return torch.empty(x.shape[0], out_features, dtype=torch.bfloat16, device=x.device)
+
+
+# ---------------------------------------------------------------------------
+# NVFP4 MoE custom op (L1 + SiLU + L2 grouped GEMM)
+# ---------------------------------------------------------------------------
+@torch.library.custom_op("nvfp4::moe_gemm", mutates_args=())
+def nvfp4_moe_gemm(
+    hidden_states: torch.Tensor,
+    topk_weights: torch.Tensor,
+    topk_ids: torch.Tensor,
+    runner_id: int,
+    hidden_size: int,
+) -> torch.Tensor:
+    """Opaque NVFP4 MoE GEMM for torch.compile.
+
+    Args:
+        hidden_states: (M, K) BF16 input
+        topk_weights: (M, top_k) float32 routing weights
+        topk_ids: (M, top_k) int32 expert IDs
+        runner_id: integer key into the runner registry
+        hidden_size: output dimension (for shape inference)
+    Returns:
+        (M, hidden_size) BF16 output
+    """
+    runner = get_runner(runner_id)
+    return runner._run_impl(hidden_states, topk_weights, topk_ids)
+
+
+@nvfp4_moe_gemm.register_fake
+def _(hidden_states, topk_weights, topk_ids, runner_id, hidden_size):
+    return torch.empty(
+        hidden_states.shape[0], hidden_size,
+        dtype=torch.bfloat16, device=hidden_states.device,
+    )
+
+
+# ---------------------------------------------------------------------------
+# DSV4 Sparse FMHA custom op (attention with SWA + sink bias)
+# ---------------------------------------------------------------------------
+@torch.library.custom_op("dsv4::sparse_fmha_with_swa", mutates_args=())
+def dsv4_sparse_fmha(
+    q: torch.Tensor,          # (n_q_heads, T, hd) BF16
+    k: torch.Tensor,          # (n_kv_heads, N, hd) or (N, hd) BF16
+    v: torch.Tensor,          # same as k
+    sink_bias: torch.Tensor,  # (n_q_heads,) FP32 — can be zeros if unused
+    scale: float,
+    swa_len: int,
+    is_causal: bool,
+    n_comp: int,
+) -> torch.Tensor:
+    """Opaque DSV4 attention for torch.compile.
+
+    Delegates to dsv4_attention with the appropriate flags.
+    sink_bias is always passed (use zeros when unused) to keep the
+    custom_op signature tensor-only for Dynamo compatibility.
+    """
+    from dsv4.kernels.attention.production import dsv4_attention as _dsv4_attention
+
+    # If sink_bias is all zeros and n_comp == 0, skip sink bias
+    has_sink = n_comp > 0 and sink_bias.abs().sum().item() > 0
+    return _dsv4_attention(
+        q, k, v, scale=scale,
+        swa_len=swa_len if swa_len > 0 else None,
+        is_causal=is_causal,
+        n_comp=n_comp,
+        sink_bias=sink_bias if has_sink else None,
+    )
+
+
+@dsv4_sparse_fmha.register_fake
+def _(q, k, v, sink_bias, scale, swa_len, is_causal, n_comp):
+    return torch.empty_like(q)

dsv4/_archive/ops/router.py

@@ -0,0 +1,93 @@
+"""torch.library.custom_op wrappers and dispatch for the Router kernels.
+
+Mirrors the pattern in dsv4/ops/custom_ops.py:
+  - Routers are registered into an integer-keyed table.
+  - The custom_op takes the integer ID and tensor args only.
+  - Dynamo can't trace through the kernel; the op is opaque.
+"""
+
+import torch
+from dsv4.kernels.router import (
+    dense_router_dispatch,   # picks decode vs prefill internally
+    hash_router_dispatch,
+)
+
+_next_router_id = 0
+_router_registry: dict[int, object] = {}
+
+
+def register_router(router) -> int:
+    global _next_router_id
+    rid = _next_router_id
+    _next_router_id += 1
+    _router_registry[rid] = router
+    return rid
+
+
+def get_router(rid: int):
+    return _router_registry[rid]
+
+
+def warmup_router_compilation(router) -> None:
+    """Trigger eager JIT compilation for the router's kernel path.
+
+    Runs a dummy forward at max_num_tokens to compile the kernel for the
+    expected shape range. Caller already has the buffers allocated.
+    """
+    if router.mode == "dense":
+        # Dummy forward at small N triggers decode-path compile.
+        # CuTeDSL fused kernel is WIP — falls through to prefill path.
+        dummy = torch.zeros(
+            1, router.hidden_size,
+            dtype=torch.bfloat16, device=router.device,
+        )
+        try:
+            router._run_dense_impl(dummy)
+        except Exception:
+            pass  # CuTeDSL kernel not yet working; prefill path is fine
+    else:
+        dummy = torch.zeros(1, dtype=torch.int32, device=router.device)
+        router._run_hash_impl(dummy)
+
+
+# ----- Dense router custom op -----
+@torch.library.custom_op("dsv4::dense_router", mutates_args=())
+def dense_router_op(
+    hidden_states: torch.Tensor,
+    router_id: int,
+    num_experts: int,
+    top_k: int,
+) -> tuple[torch.Tensor, torch.Tensor]:
+    router = get_router(router_id)
+    return router._run_dense_impl(hidden_states)
+
+
+@dense_router_op.register_fake
+def _(hidden_states, router_id, num_experts, top_k):
+    N = hidden_states.shape[0]
+    device = hidden_states.device
+    return (
+        torch.empty(N, top_k, dtype=torch.float32, device=device),
+        torch.empty(N, top_k, dtype=torch.int32, device=device),
+    )
+
+
+# ----- Hash router custom op -----
+@torch.library.custom_op("dsv4::hash_router", mutates_args=())
+def hash_router_op(
+    token_ids: torch.Tensor,
+    router_id: int,
+    top_k: int,
+) -> tuple[torch.Tensor, torch.Tensor]:
+    router = get_router(router_id)
+    return router._run_hash_impl(token_ids)
+
+
+@hash_router_op.register_fake
+def _(token_ids, router_id, top_k):
+    N = token_ids.shape[0]
+    device = token_ids.device
+    return (
+        torch.empty(N, top_k, dtype=torch.float32, device=device),
+        torch.empty(N, top_k, dtype=torch.int32, device=device),
+    )

dsv4/kernels/attention/__init__.py

@@ -1,180 +1,7 @@
 """DSV4 Attention kernels — public integration API.
 
-====================================================================
-STATUS: SKELETON — not yet connected to model
-====================================================================
-These functions define the API that AttentionSubBlock will call.
-They're correct in structure but depend on:
-1. LayerCacheHandle being fully implemented (gather_compressed_kv, etc.)
-2. The production FMHA wrapper supporting sink_bias and n_comp
-3. Custom op registration for torch.compile compatibility
-
-See ROADMAP.md Priority 5 for the full Stage E checklist.
-====================================================================
-
-These functions bridge the model's AttentionSubBlock to the production
-FMHA kernel wrapper. Each function handles the cache → dense-tensor
-materialization that the kernel requires.
-
-The model's attention layer calls these after:
-1. Projection (q_down, q_up, kv_down)
-2. RoPE application
-3. Compression + cache writes
-4. Indexer + top-k (CSA only)
-
-These functions handle:
-- Gathering sparse/dense KV from cache into dense tensors
-- Calling the production FMHA wrapper
-- Returning attention output for inverse RoPE + wo_a/wo_b
+The live inference path uses dsv4.kernels.attention.production directly.
+See production.py for the dsv4_attention function used by single_shot_inference.py.
 """
 from dsv4.kernels.attention.production import dsv4_attention
-import torch
-from typing import Optional, TYPE_CHECKING
-
-if TYPE_CHECKING:
-    from dsv4.cache.handle import LayerCacheHandle
-
-
-def sparse_fmha_with_swa(
-    q: torch.Tensor,               # (T, n_h * hd) BF16, post-RoPE
-    cache: "LayerCacheHandle",      # provides compressed + SWA KV
-    selected_indices: torch.Tensor, # (T, top_k) int64 — which compressed blocks
-    sink_logits: Optional[torch.Tensor] = None,  # (n_h,) FP32
-    sliding_window: int = 128,
-) -> torch.Tensor:
-    """CSA attention: sparse top-k compressed KV + sliding window, fused sink merge.
-
-    Gathers the top-k compressed KV blocks + SWA window into a contiguous
-    tensor, then calls the production FMHA with sink bias.
-
-    Args:
-        q: (T, n_h * hd) BF16 query (post-RoPE, pre-reshape)
-        cache: LayerCacheHandle with CSA compressed entries + SWA window
-        selected_indices: (T, top_k) int64 block indices from the indexer
-        sink_logits: (n_h,) FP32 per-head sink bias
-        sliding_window: SWA window length
-
-    Returns:
-        (T, n_h * hd) BF16 attention output (pre inverse-RoPE)
-    """
-    # Reshape q to (n_h, T, hd)
-    n_h_and_hd = q.shape[-1]
-    # n_h and hd come from the cache's config
-    n_h = cache.num_query_heads
-    hd = cache.head_dim
-    T = q.shape[0]
-    q_heads = q.reshape(T, n_h, hd).permute(1, 0, 2)  # (n_h, T, hd)
-
-    # Gather compressed KV for the selected blocks
-    # The cache handle provides the materialized dense KV from paged pool
-    k_compressed, v_compressed = cache.gather_compressed_kv(selected_indices)
-    # k_compressed: (1, n_comp_kv, hd) or (n_kv, n_comp_kv, hd)
-    # v_compressed: same shape
-
-    # Gather SWA window KV
-    k_swa, v_swa = cache.gather_swa_kv()
-    # k_swa: (1, swa_len, hd), v_swa: same
-
-    # Concatenate: [compressed, SWA] — single softmax (D5c insight)
-    k_full = torch.cat([k_compressed, k_swa], dim=-2)  # (1, n_comp+swa_len, hd)
-    v_full = torch.cat([v_compressed, v_swa], dim=-2)
-
-    # n_comp = compressed KV length (for sink bias offset)
-    n_comp = k_compressed.shape[-2]
-
-    # Call production attention — MQA (n_kv=1 for DSV4)
-    output = dsv4_attention(
-        q_heads, k_full, v_full,
-        swa_len=sliding_window,
-        is_causal=True,
-        n_comp=n_comp,
-        sink_bias=sink_logits,
-    )  # (n_h, T, hd)
-
-    # Reshape back to (T, n_h * hd)
-    return output.permute(1, 0, 2).reshape(T, n_h * hd)
-
-
-def dense_fmha_with_swa(
-    q: torch.Tensor,
-    cache: "LayerCacheHandle",
-    sink_logits: Optional[torch.Tensor] = None,
-    sliding_window: int = 128,
-) -> torch.Tensor:
-    """HCA attention: dense over all compressed KV + SWA window, fused sink merge.
-
-    No indexer — all compressed entries are attended (m'=128 compression
-    means the sequence is very short).
-
-    Args:
-        q: (T, n_h * hd) BF16 query
-        cache: LayerCacheHandle with HCA compressed entries + SWA window
-        sink_logits: (n_h,) FP32 per-head sink bias
-        sliding_window: SWA window length
-
-    Returns:
-        (T, n_h * hd) BF16 attention output
-    """
-    n_h = cache.num_query_heads
-    hd = cache.head_dim
-    T = q.shape[0]
-    q_heads = q.reshape(T, n_h, hd).permute(1, 0, 2)
-
-    # Dense: gather ALL compressed KV (no indexer needed)
-    k_compressed, v_compressed = cache.gather_all_compressed_kv()
-
-    k_swa, v_swa = cache.gather_swa_kv()
-
-    k_full = torch.cat([k_compressed, k_swa], dim=-2)
-    v_full = torch.cat([v_compressed, v_swa], dim=-2)
-
-    n_comp = k_compressed.shape[-2]
-
-    output = dsv4_attention(
-        q_heads, k_full, v_full,
-        swa_len=sliding_window,
-        is_causal=True,
-        n_comp=n_comp,
-        sink_bias=sink_logits,
-    )
-
-    return output.permute(1, 0, 2).reshape(T, n_h * hd)
-
-
-def swa_only_fmha(
-    q: torch.Tensor,
-    cache: "LayerCacheHandle",
-    sink_logits: Optional[torch.Tensor] = None,
-    sliding_window: int = 128,
-) -> torch.Tensor:
-    """SWA-only attention: pure local attention over the sliding window.
-
-    No compression branch, no indexer. Used for the first two layers
-    of the Flash variant.
-
-    Args:
-        q: (T, n_h * hd) BF16 query
-        cache: LayerCacheHandle with SWA window
-        sink_logits: (n_h,) FP32 per-head sink bias
-        sliding_window: SWA window length
-
-    Returns:
-        (T, n_h * hd) BF16 attention output
-    """
-    n_h = cache.num_query_heads
-    hd = cache.head_dim
-    T = q.shape[0]
-    q_heads = q.reshape(T, n_h, hd).permute(1, 0, 2)
-
-    k_swa, v_swa = cache.gather_swa_kv()
-
-    # No n_comp (no compressed branch), no sink bias offset
-    output = dsv4_attention(
-        q_heads, k_swa, v_swa,
-        swa_len=sliding_window,
-        is_causal=True,
-        n_comp=0,
-        sink_bias=sink_logits,
-    )
-
-    return output.permute(1, 0, 2).reshape(T, n_h * hd)
+from dsv4.kernels.attention.production import dsv4_attention_mixed_fp8_decode

dsv4/kernels/attention/fmha_mixed_fp8_capi.cu

@@ -0,0 +1,79 @@
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cstdint>
+#include "fmha_common.cuh"
+#include "fmha_umma_desc.cuh"
+#include "fmha_mixed_fp8_decode.cuh"
+
+using namespace dsv4::kernels::attention;
+
+extern "C" {
+
+int fmha_mixed_fp8_decode_launch(
+    const void* q_nope_fp8,
+    const float* q_nope_scale,
+    const void* q_rope_bf16,
+    const void* k_nope_fp8,
+    const float* k_nope_scale,
+    const void* k_rope_bf16,
+    void* o_ptr,
+    void* lse_ptr,
+    const float* sink_bias_ptr,
+    int B, int H, int T, int N, int HD, int NOPE, int ROPE,
+    int q_nope_head_stride, int q_nope_batch_stride,
+    int q_scale_head_stride, int q_scale_batch_stride,
+    int q_rope_head_stride, int q_rope_batch_stride,
+    int o_head_stride, int o_batch_stride,
+    int lse_head_stride, int lse_batch_stride,
+    float scale
+) {
+    if (T != 1 || HD != 512 || NOPE != 448 || ROPE != 64) return -2;
+
+    FmhaMixedFp8DecodeParams p;
+    p.q_nope_fp8 = (const uint8_t*)q_nope_fp8;
+    p.q_nope_scale = q_nope_scale;
+    p.q_rope_bf16 = (const bf16_t*)q_rope_bf16;
+    p.k_nope_fp8 = (const uint8_t*)k_nope_fp8;
+    p.k_nope_scale = k_nope_scale;
+    p.k_rope_bf16 = (const bf16_t*)k_rope_bf16;
+    p.o = (bf16_t*)o_ptr;
+    p.lse = (float*)lse_ptr;
+    p.sink_bias = sink_bias_ptr;
+    p.B = B; p.H = H; p.N = N; p.HD = HD; p.NOPE = NOPE; p.ROPE = ROPE;
+    p.q_nope_head_stride = q_nope_head_stride;
+    p.q_nope_batch_stride = q_nope_batch_stride;
+    p.q_scale_head_stride = q_scale_head_stride;
+    p.q_scale_batch_stride = q_scale_batch_stride;
+    p.q_rope_head_stride = q_rope_head_stride;
+    p.q_rope_batch_stride = q_rope_batch_stride;
+    p.o_head_stride = o_head_stride;
+    p.o_batch_stride = o_batch_stride;
+    p.lse_head_stride = lse_head_stride;
+    p.lse_batch_stride = lse_batch_stride;
+    p.scale = scale;
+
+    // Static shared memory size for fmha_mixed_fp8_decode_kernel<512,448,64>.
+    // Keep this mirrored with the header layout and aligned up generously.
+    int smem = 0;
+    smem += 4; smem = (smem + 127) & ~127;
+    smem += 128 * 32; smem = (smem + 127) & ~127;           // sQ8
+    smem += 128 * 32; smem = (smem + 127) & ~127;           // sK8
+    smem += 128 * 16 * 2; smem = (smem + 127) & ~127;       // sQ16
+    smem += 128 * 16 * 2; smem = (smem + 127) & ~127;       // sK16
+    smem += 128 * 16 * 2; smem = (smem + 127) & ~127;       // sPk
+    smem += 16 * 16 * 2; smem = (smem + 127) & ~127;        // sV
+    smem += 128 * 4;                                        // sLogits
+    smem += 128 * 4;                                        // sP
+    smem += 512 * 4;                                        // sOacc
+    smem += 512 * 2;                                        // sOepi
+    smem = (smem + 127) & ~127;
+
+    cudaFuncSetAttribute(fmha_mixed_fp8_decode_kernel<512,448,64>, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
+    dim3 grid(1, H, B);
+    dim3 block(192);
+    fmha_mixed_fp8_decode_kernel<512,448,64><<<grid, block, smem>>>(p);
+    cudaError_t err = cudaGetLastError();
+    return err == cudaSuccess ? 0 : (int)err;
+}
+
+} // extern C

dsv4/kernels/attention/fmha_mixed_fp8_decode.cuh

@@ -0,0 +1,374 @@
+/**
+ * DSV4 B1 — mixed FP8/BF16 decode FMHA for DeepSeek-V4 attention KV.
+ *
+ * Inputs are the storage-native DSV4 layout:
+ *   Q noPE: FP8_E4M3 + per-row FP32 scale, Q RoPE: BF16
+ *   KV noPE: FP8_E4M3 + per-row FP32 scale, KV RoPE: BF16
+ *
+ * This first B1 kernel targets the decode hot path (T == 1) and HD=512,
+ * NOPE=448, ROPE=64. It removes the global FP8->BF16 KV dequant/gather and
+ * uses Blackwell tcgen05 tensor cores for:
+ *   - noPE QK: f8f6f4 E4M3 x E4M3 -> FP32
+ *   - RoPE QK: f16 BF16 x BF16 -> FP32
+ *   - PV:      f16 BF16 x BF16 -> FP32, with noPE V dequantized only into SMEM
+ *
+ * The noPE KV is never materialized as a global BF16 buffer.
+ */
+#pragma once
+
+#include <cuda_runtime.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <cstdint>
+#include <cmath>
+#include "fmha_common.cuh"
+#include "fmha_umma_desc.cuh"
+
+namespace dsv4::kernels::attention {
+
+struct FmhaMixedFp8DecodeParams {
+    const uint8_t* __restrict__ q_nope_fp8;   // (B,H,1,NOPE)
+    const float* __restrict__ q_nope_scale;   // (B,H,1)
+    const bf16_t* __restrict__ q_rope_bf16;   // (B,H,1,ROPE)
+
+    const uint8_t* __restrict__ k_nope_fp8;   // (N,NOPE), MQA shared
+    const float* __restrict__ k_nope_scale;   // (N,)
+    const bf16_t* __restrict__ k_rope_bf16;   // (N,ROPE)
+
+    bf16_t* __restrict__ o;                   // (B,H,1,HD)
+    float* __restrict__ lse;                  // (B,H,1), optional
+    const float* __restrict__ sink_bias;      // (B,H), optional
+
+    int B, H, N, HD, NOPE, ROPE;
+    int q_nope_head_stride, q_nope_batch_stride;
+    int q_scale_head_stride, q_scale_batch_stride;
+    int q_rope_head_stride, q_rope_batch_stride;
+    int o_head_stride, o_batch_stride;
+    int lse_head_stride, lse_batch_stride;
+    float scale;
+};
+
+__device__ __forceinline__ float fp8_e4m3_to_f32(uint8_t byte) {
+    __nv_fp8_e4m3 v;
+    *reinterpret_cast<uint8_t*>(&v) = byte;
+    return static_cast<float>(v);
+}
+
+// FP8 canonical K-major layout for tcgen05.mma.kind::f8f6f4.
+// Logical matrix shape is (128, 32): 8 row groups x 16 FP8 columns per 128B atom.
+__device__ __forceinline__ int canon_idx_fp8_128x32(int r, int c) {
+    constexpr int CORES_MN = 16;  // 128 / 8
+    int core_mn = r >> 3;
+    int core_k = c >> 4;          // 16 FP8 values = 16B atom width
+    int local_r = r & 7;
+    int local_c = c & 15;
+    return core_k * CORES_MN * 128 + core_mn * 128 + local_r * 16 + local_c;
+}
+
+__device__ __forceinline__ int canon_idx_bf16_128x16(int r, int c) {
+    constexpr int CORES_MN = 16;
+    int core_mn = r >> 3;
+    int core_k = c >> 3;
+    int local_r = r & 7;
+    int local_c = c & 7;
+    return core_k * CORES_MN * 64 + core_mn * 64 + local_r * 8 + local_c;
+}
+
+__device__ __forceinline__ int canon_idx_bf16_16x16(int r, int c) {
+    constexpr int CORES_MN = 2;   // 16 / 8
+    int core_mn = r >> 3;
+    int core_k = c >> 3;
+    int local_r = r & 7;
+    int local_c = c & 7;
+    return core_k * CORES_MN * 64 + core_mn * 64 + local_r * 8 + local_c;
+}
+
+__device__ __forceinline__ bf16_t f32_to_bf16_bits(float x) { return f32_to_bf16(x); }
+
+// Read row 0 of a 128-wide TMEM result. Must be called by a full warp;
+// lane 0 receives row 0, lanes 1..31 receive rows 1..31 and are ignored.
+__device__ __forceinline__ void read_tmem_row0_128(uint32_t tb, float* out128, bool lane0) {
+    for (int n = 0; n < 16; n++) {
+        float tmp[8];
+        asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
+            : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
+              "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
+            : "r"(tb + n * 8));
+        asm volatile("tcgen05.wait::ld.sync.aligned;" ::: "memory");
+        if (lane0) {
+            #pragma unroll
+            for (int c = 0; c < 8; c++) out128[n * 8 + c] = tmp[c];
+        }
+    }
+}
+
+template<int HD=512, int NOPE=448, int ROPE=64, int SK_TILE=128>
+__global__ void __launch_bounds__(192)
+fmha_mixed_fp8_decode_kernel(FmhaMixedFp8DecodeParams p) {
+    static_assert(HD == 512 && NOPE == 448 && ROPE == 64, "B1 first pass is specialized for DSV4 HD=512/NOPE=448/ROPE=64");
+    constexpr int MMA_K_F8 = 32;
+    constexpr int MMA_K_F16 = 16;
+    constexpr int NKT_NOPE = NOPE / MMA_K_F8;
+    constexpr int NKT_ROPE = ROPE / MMA_K_F16;
+    constexpr int NKT_PV = SK_TILE / MMA_K_F16;
+    constexpr int N_SUB = HD / 16;
+    constexpr int TILE_F8 = 128 * MMA_K_F8;    // bytes
+    constexpr int TILE_F16 = 128 * MMA_K_F16;  // bf16 elements
+    constexpr int V_SUB_SZ = 16 * MMA_K_F16;   // bf16 elements
+    constexpr int TMEM_COLS = 512;
+
+    const int head_idx = blockIdx.y;
+    const int batch_idx = blockIdx.z;
+    const int tid = threadIdx.x;
+    const int wid = tid >> 5;
+    const int lane = tid & 31;
+    const bool is_mma_warp = (wid == 4);
+    const bool is_lane0 = (wid == 0 && lane == 0);
+    const int n_kv_tiles = (p.N + SK_TILE - 1) / SK_TILE;
+
+    const uint8_t* q8 = p.q_nope_fp8 + batch_idx * p.q_nope_batch_stride + head_idx * p.q_nope_head_stride;
+    const float q8_scale = p.q_nope_scale[batch_idx * p.q_scale_batch_stride + head_idx * p.q_scale_head_stride];
+    const bf16_t* qrope = p.q_rope_bf16 + batch_idx * p.q_rope_batch_stride + head_idx * p.q_rope_head_stride;
+    bf16_t* out = p.o + batch_idx * p.o_batch_stride + head_idx * p.o_head_stride;
+    float* lse = p.lse ? p.lse + batch_idx * p.lse_batch_stride + head_idx * p.lse_head_stride : nullptr;
+
+    extern __shared__ __align__(128) char sbuf[];
+    size_t off = 0;
+    uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off += 4;
+    off = (off + 127) & ~(size_t)127;
+    uint8_t* sQ8 = (uint8_t*)(sbuf + off); off += TILE_F8;
+    off = (off + 127) & ~(size_t)127;
+    uint8_t* sK8 = (uint8_t*)(sbuf + off); off += TILE_F8;
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sQ16 = (bf16_t*)(sbuf + off); off += TILE_F16 * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sK16 = (bf16_t*)(sbuf + off); off += TILE_F16 * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sPk = (bf16_t*)(sbuf + off); off += TILE_F16 * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sV = (bf16_t*)(sbuf + off); off += V_SUB_SZ * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    float* sLogits = (float*)(sbuf + off); off += SK_TILE * sizeof(float);
+    float* sP = (float*)(sbuf + off); off += SK_TILE * sizeof(float);
+    float* sOacc = (float*)(sbuf + off); off += HD * sizeof(float);
+    bf16_t* sOepi = (bf16_t*)(sbuf + off); off += HD * sizeof(bf16_t);
+
+    if (is_mma_warp) tmem_alloc((uint32_t)__cvta_generic_to_shared(sTmemBase), TMEM_COLS);
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+    __syncthreads();
+    uint32_t tb = *sTmemBase;
+
+    if (tid < HD) sOacc[tid] = 0.0f;
+    if (tid < SK_TILE) { sLogits[tid] = -INFINITY; sP[tid] = 0.0f; }
+    __syncthreads();
+
+    float running_max = -INFINITY;
+    float running_sum = 0.0f;
+    const uint32_t idesc_f8_qk = make_idesc_f8_e4m3(128, 128);
+    const uint32_t idesc_f16_qk = make_idesc(128, 128);
+    const uint32_t idesc_pv = make_idesc(128, 16);
+
+    for (int kv_tile = 0; kv_tile < n_kv_tiles; kv_tile++) {
+        const int kv_start = kv_tile * SK_TILE;
+        const int kv_len = min(SK_TILE, p.N - kv_start);
+
+        // ------------------------------------------------------------
+        // QK noPE: FP8 tensor cores, raw logits in TMEM.
+        // ------------------------------------------------------------
+        for (int kt = 0; kt < NKT_NOPE; kt++) {
+            for (int i = tid; i < TILE_F8; i += blockDim.x) { sQ8[i] = 0; sK8[i] = 0; }
+            __syncthreads();
+            for (int c = tid; c < MMA_K_F8; c += blockDim.x) {
+                int d = kt * MMA_K_F8 + c;
+                sQ8[canon_idx_fp8_128x32(0, c)] = q8[d];
+            }
+            for (int i = tid; i < kv_len * MMA_K_F8; i += blockDim.x) {
+                int r = i / MMA_K_F8, c = i % MMA_K_F8;
+                int d = kt * MMA_K_F8 + c;
+                sK8[canon_idx_fp8_128x32(r, c)] = p.k_nope_fp8[(int64_t)(kv_start + r) * NOPE + d];
+            }
+            __syncthreads();
+            if (is_mma_warp && lane == 0) {
+                uint64_t dq = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sQ8), 128);
+                uint64_t dk = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sK8), 128);
+                umma_ss_f8f6f4(tb, dq, dk, idesc_f8_qk, kt > 0);
+                asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+            }
+            __syncthreads();
+        }
+        asm volatile("fence.sc.gpu;" ::: "memory");
+        __syncthreads();
+
+        if (wid == 0) read_tmem_row0_128(tb, sLogits, lane == 0);
+        __syncthreads();
+        if (is_lane0) {
+            #pragma unroll
+            for (int c = 0; c < SK_TILE; c++) {
+                if (c < kv_len) {
+                    float ks = p.k_nope_scale[kv_start + c];
+                    sLogits[c] = sLogits[c] * q8_scale * ks;
+                } else {
+                    sLogits[c] = -INFINITY;
+                }
+            }
+        }
+        __syncthreads();
+
+        // ------------------------------------------------------------
+        // QK RoPE: BF16 tensor cores, then add to scaled noPE logits.
+        // ------------------------------------------------------------
+        for (int kt = 0; kt < NKT_ROPE; kt++) {
+            for (int i = tid; i < TILE_F16; i += blockDim.x) { sQ16[i] = 0; sK16[i] = 0; }
+            __syncthreads();
+            for (int c = tid; c < MMA_K_F16; c += blockDim.x) {
+                int d = kt * MMA_K_F16 + c;
+                sQ16[canon_idx_bf16_128x16(0, c)] = qrope[d];
+            }
+            for (int i = tid; i < kv_len * MMA_K_F16; i += blockDim.x) {
+                int r = i / MMA_K_F16, c = i % MMA_K_F16;
+                int d = kt * MMA_K_F16 + c;
+                sK16[canon_idx_bf16_128x16(r, c)] = p.k_rope_bf16[(int64_t)(kv_start + r) * ROPE + d];
+            }
+            __syncthreads();
+            if (is_mma_warp && lane == 0) {
+                uint64_t dq = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sQ16), 128);
+                uint64_t dk = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sK16), 128);
+                umma_ss_f16(tb, dq, dk, idesc_f16_qk, kt > 0);
+                asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+            }
+            __syncthreads();
+        }
+        asm volatile("fence.sc.gpu;" ::: "memory");
+        __syncthreads();
+
+        // Use sP as a temporary row buffer here; probabilities are formed later.
+        if (wid == 0) read_tmem_row0_128(tb, sP, lane == 0);
+        __syncthreads();
+        if (is_lane0) {
+            for (int c = 0; c < kv_len; c++) sLogits[c] += sP[c];
+        }
+        __syncthreads();
+
+        // ------------------------------------------------------------
+        // Softmax tile probabilities for row 0.
+        // ------------------------------------------------------------
+        float tile_max = -INFINITY;
+        if (is_lane0) {
+            for (int c = 0; c < kv_len; c++) tile_max = fmaxf(tile_max, sLogits[c] * p.scale);
+            float tile_sum = 0.0f;
+            for (int c = 0; c < kv_len; c++) {
+                float pv = expf(sLogits[c] * p.scale - tile_max);
+                sP[c] = pv;
+                tile_sum += pv;
+            }
+            for (int c = kv_len; c < SK_TILE; c++) sP[c] = 0.0f;
+
+            float new_max = fmaxf(running_max, tile_max);
+            float rescale_old = (running_max > -INFINITY) ? expf(running_max - new_max) : 0.0f;
+            for (int d = 0; d < HD; d++) sOacc[d] *= rescale_old;
+            running_sum = running_sum * rescale_old + tile_sum * expf(tile_max - new_max);
+            running_max = new_max;
+        }
+        __syncthreads();
+
+        // ------------------------------------------------------------
+        // PV: probabilities BF16 x V BF16. noPE V is dequantized into SMEM only.
+        // ------------------------------------------------------------
+        for (int n_sub = 0; n_sub < N_SUB; n_sub++) {
+            int d_base = n_sub * 16;
+            for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
+                const int col_start = pv_kt * MMA_K_F16;
+                for (int i = tid; i < TILE_F16; i += blockDim.x) sPk[i] = 0;
+                for (int i = tid; i < V_SUB_SZ; i += blockDim.x) sV[i] = 0;
+                __syncthreads();
+
+                // P matrix: only row 0 non-zero.
+                for (int c = tid; c < MMA_K_F16; c += blockDim.x) {
+                    int gc = col_start + c;
+                    sPk[canon_idx_bf16_128x16(0, c)] = f32_to_bf16_bits(sP[gc]);
+                }
+
+                // V matrix B: logical (16 K rows, 16 N cols) in BF16 canonical layout.
+                for (int i = tid; i < 16 * MMA_K_F16; i += blockDim.x) {
+                    int dd = i / MMA_K_F16;
+                    int kk = i % MMA_K_F16;
+                    int row = col_start + kk;
+                    int g_row = kv_start + row;
+                    int d = d_base + dd;
+                    bf16_t vbits = 0;
+                    if (row < kv_len) {
+                        if (d < NOPE) {
+                            uint8_t b = p.k_nope_fp8[(int64_t)g_row * NOPE + d];
+                            float v = fp8_e4m3_to_f32(b) * p.k_nope_scale[g_row];
+                            vbits = f32_to_bf16_bits(v);
+                        } else {
+                            vbits = p.k_rope_bf16[(int64_t)g_row * ROPE + (d - NOPE)];
+                        }
+                    }
+                    // B is (K=16 rows, N=16 cols). Reuse BF16 canonical with rows=16
+                    // by embedding into the first 16 rows of a 128-row tile; MMA_N=16.
+                    sV[canon_idx_bf16_16x16(dd, kk)] = vbits;
+                }
+                __syncthreads();
+
+                if (is_mma_warp && lane == 0) {
+                    uint64_t dp = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sPk), 128);
+                    uint64_t dv = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sV), 16);
+                    umma_ss_f16(tb + n_sub * 16, dp, dv, idesc_pv, pv_kt > 0);
+                    asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+                }
+                __syncthreads();
+            }
+        }
+        asm volatile("fence.sc.gpu;" ::: "memory");
+        __syncthreads();
+
+        // Accumulate PV tile contribution after applying exp(tile_max-new_max).
+        if (wid == 0) {
+            float rescale_new = 0.0f;
+            if (lane == 0) {
+                // running_max is already the post-tile max. Recompute tile scale.
+                float tile_max2 = -INFINITY;
+                for (int c = 0; c < kv_len; c++) tile_max2 = fmaxf(tile_max2, sLogits[c] * p.scale);
+                rescale_new = expf(tile_max2 - running_max);
+            }
+            for (int n = 0; n < HD / 8; n++) {
+                float tmp[8];
+                asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
+                    : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
+                      "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
+                    : "r"(tb + n * 8));
+                asm volatile("tcgen05.wait::ld.sync.aligned;" ::: "memory");
+                if (lane == 0) {
+                    #pragma unroll
+                    for (int c = 0; c < 8; c++) sOacc[n * 8 + c] += tmp[c] * rescale_new;
+                }
+            }
+        }
+        __syncthreads();
+    }
+
+    // Attention sink: denominator-only logit.
+    if (is_lane0 && p.sink_bias != nullptr) {
+        float sb = p.sink_bias[batch_idx * p.H + head_idx];
+        float new_max = fmaxf(running_max, sb);
+        float rescale_old = (running_max > -INFINITY) ? expf(running_max - new_max) : 0.0f;
+        for (int d = 0; d < HD; d++) sOacc[d] *= rescale_old;
+        running_sum = running_sum * rescale_old + expf(sb - new_max);
+        running_max = new_max;
+    }
+    __syncthreads();
+
+    if (is_lane0) {
+        float inv_sum = 1.0f / running_sum;
+        for (int d = 0; d < HD; d++) sOepi[d] = f32_to_bf16_bits(sOacc[d] * inv_sum);
+        if (lse) lse[0] = logf(running_sum) + running_max;
+    }
+    __syncthreads();
+    for (int d = tid; d < HD; d += blockDim.x) out[d] = sOepi[d];
+    __syncthreads();
+
+    if (is_mma_warp) tmem_dealloc(tb, TMEM_COLS);
+}
+
+} // namespace dsv4::kernels::attention

dsv4/kernels/attention/fmha_mixed_fp8_op.py

@@ -0,0 +1,148 @@
+"""DSV4 B1 mixed FP8/BF16 decode FMHA loader.
+
+This path is intentionally hard-error only: it does not fall back to PyTorch or to
+BF16 FMHA if the mixed FP8 kernel is requested.
+"""
+import ctypes
+import logging
+import os
+import subprocess
+from typing import Optional
+
+import torch
+
+logger = logging.getLogger(__name__)
+
+KERNEL_DIR = os.path.dirname(os.path.abspath(__file__))
+REPO_ROOT = os.path.normpath(os.path.join(KERNEL_DIR, "..", ".."))
+SOURCE = os.path.join(KERNEL_DIR, "fmha_mixed_fp8_capi.cu")
+BUILD_DIR = os.path.join(REPO_ROOT, "build", "fmha_mixed_fp8")
+SO_NAME = "libfmha_mixed_fp8.so"
+
+_lib = None
+_lib_lock = False
+
+
+def _find_nvcc():
+    import shutil
+    for c in ["/usr/local/cuda-13.2/bin/nvcc", "/usr/local/cuda/bin/nvcc"]:
+        if os.path.isfile(c):
+            return c
+    nvcc = shutil.which("nvcc")
+    if nvcc:
+        return nvcc
+    raise RuntimeError("nvcc not found")
+
+
+def _ensure_built():
+    global _lib, _lib_lock
+    if _lib is not None:
+        return _lib
+    if _lib_lock:
+        raise RuntimeError("Recursive mixed-FP8 FMHA build")
+    _lib_lock = True
+    try:
+        so_path = os.path.join(BUILD_DIR, SO_NAME)
+        deps = [
+            SOURCE,
+            os.path.join(KERNEL_DIR, "fmha_common.cuh"),
+            os.path.join(KERNEL_DIR, "fmha_umma_desc.cuh"),
+            os.path.join(KERNEL_DIR, "fmha_mixed_fp8_decode.cuh"),
+        ]
+        src_mtime = max(os.path.getmtime(p) for p in deps if os.path.exists(p))
+        need_build = not os.path.isfile(so_path) or src_mtime > os.path.getmtime(so_path)
+        if not need_build:
+            _lib = ctypes.CDLL(so_path)
+            return _lib
+
+        os.makedirs(BUILD_DIR, exist_ok=True)
+        nvcc = _find_nvcc()
+        cmd = [
+            nvcc, "-std=c++20", "-shared", "-Xcompiler", "-fPIC",
+            "-gencode=arch=compute_100a,code=sm_100a",
+            "-gencode=arch=compute_100a,code=compute_100a",
+            f"-I{KERNEL_DIR}", f"-I{REPO_ROOT}",
+            "-O3", "--use_fast_math", "--expt-relaxed-constexpr",
+            SOURCE, "-o", so_path, "-lcudart", "-lcuda",
+        ]
+        logger.info("Building libfmha_mixed_fp8.so (sm_100a)...")
+        res = subprocess.run(cmd, capture_output=True, text=True)
+        if res.returncode != 0:
+            raise RuntimeError(f"mixed FP8 FMHA nvcc failed:\nSTDOUT:\n{res.stdout}\nSTDERR:\n{res.stderr}")
+        _lib = ctypes.CDLL(so_path)
+        return _lib
+    finally:
+        _lib_lock = False
+
+
+def _quantize_q_split(q: torch.Tensor, rope_dim: int):
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("fp8_attention_io", ["fp8_attention_io.cu"],
+                          extra_cuda_cflags=[
+                              "-gencode=arch=compute_100a,code=sm_100a",
+                              "-O3", "--use_fast_math", "--expt-relaxed-constexpr",
+                          ])
+    return mod.quantize_q_fp8_split(q, rope_dim)
+
+
+def fmha_mixed_fp8_decode_raw(
+    q: torch.Tensor,                 # (B,H,1,HD) BF16
+    k_nope_fp8: torch.Tensor,        # (N,NOPE) uint8/float8_e4m3fn
+    k_nope_scale: torch.Tensor,      # (N,) FP32
+    k_rope_bf16: torch.Tensor,       # (N,ROPE) BF16
+    scale: float,
+    attn_sink: Optional[torch.Tensor] = None,
+    rope_dim: int = 64,
+):
+    if q.dim() != 4:
+        raise RuntimeError("q must be (B,H,T,HD)")
+    B, H, T, HD = q.shape
+    if T != 1:
+        raise RuntimeError("mixed FP8 FMHA supports decode T==1 only")
+    NOPE = HD - rope_dim
+    if HD != 512 or NOPE != 448 or rope_dim != 64:
+        raise RuntimeError(f"mixed FP8 FMHA first pass supports HD=512/NOPE=448/ROPE=64, got {HD}/{NOPE}/{rope_dim}")
+
+    q = q.contiguous()
+    k_nope_fp8 = k_nope_fp8.contiguous()
+    k_nope_scale = k_nope_scale.contiguous()
+    k_rope_bf16 = k_rope_bf16.contiguous()
+    q_nope_fp8, q_nope_scale, q_rope = _quantize_q_split(q, rope_dim)
+
+    N = k_nope_fp8.shape[0]
+    o = torch.empty((B, H, T, HD), dtype=torch.bfloat16, device=q.device)
+    lse = torch.empty((B, H, T), dtype=torch.float32, device=q.device)
+
+    sink_ptr = ctypes.c_void_p(0)
+    sb = None
+    if attn_sink is not None:
+        sb = attn_sink.float().contiguous()
+        if sb.dim() == 1:
+            sb = sb.unsqueeze(0).expand(B, -1).contiguous()
+        if tuple(sb.shape) != (B, H):
+            raise RuntimeError(f"sink bias shape {tuple(sb.shape)} != {(B,H)}")
+        sink_ptr = ctypes.c_void_p(sb.data_ptr())
+
+    lib = _ensure_built()
+    ret = lib.fmha_mixed_fp8_decode_launch(
+        ctypes.c_void_p(q_nope_fp8.data_ptr()),
+        ctypes.c_void_p(q_nope_scale.data_ptr()),
+        ctypes.c_void_p(q_rope.data_ptr()),
+        ctypes.c_void_p(k_nope_fp8.data_ptr()),
+        ctypes.c_void_p(k_nope_scale.data_ptr()),
+        ctypes.c_void_p(k_rope_bf16.data_ptr()),
+        ctypes.c_void_p(o.data_ptr()),
+        ctypes.c_void_p(lse.data_ptr()),
+        sink_ptr,
+        ctypes.c_int(B), ctypes.c_int(H), ctypes.c_int(T), ctypes.c_int(N),
+        ctypes.c_int(HD), ctypes.c_int(NOPE), ctypes.c_int(rope_dim),
+        ctypes.c_int(q_nope_fp8.stride(1)), ctypes.c_int(q_nope_fp8.stride(0)),
+        ctypes.c_int(q_nope_scale.stride(1)), ctypes.c_int(q_nope_scale.stride(0)),
+        ctypes.c_int(q_rope.stride(1)), ctypes.c_int(q_rope.stride(0)),
+        ctypes.c_int(o.stride(1)), ctypes.c_int(o.stride(0)),
+        ctypes.c_int(lse.stride(1)), ctypes.c_int(lse.stride(0)),
+        ctypes.c_float(scale),
+    )
+    if ret != 0:
+        raise RuntimeError(f"mixed FP8 FMHA launch failed: return code {ret}")
+    return o, lse

dsv4/kernels/attention/fmha_mixed_fp8_prefill.cuh

@@ -0,0 +1,488 @@
+/**
+ * DSV4 B1 — mixed FP8/BF16 prefill FMHA for DeepSeek-V4 attention KV.
+ *
+ * Extension of the decode kernel (fmha_mixed_fp8_decode.cuh) to support T > 1.
+ * Same storage-native DSV4 layout as decode:
+ *   Q noPE: FP8_E4M3 + per-row FP32 scale, Q RoPE: BF16
+ *   KV noPE: FP8_E4M3 + per-row FP32 scale, KV RoPE: BF16
+ *
+ * Architecture:
+ *   - noPE QK: f8f6f4 E4M3 x E4M3 -> FP32  (same MMA as decode)
+ *   - RoPE QK: f16 BF16 x BF16 -> FP32      (same MMA as decode)
+ *   - Multi-row softmax: T independent per-row softmax in SMEM (online algorithm)
+ *   - PV: per query row (one PV MMA per row; correctness first, batched PV is TODO)
+ *   - Sink bias: denominator-only logit per head
+ *   - Output: normalized (BF16)
+ *
+ * SMEM budget: process in T_BATCH sub-batches to fit in 232KB.
+ * T_BATCH=32: sOacc=64KB, sLogits=16KB, sP=16KB, rest=40KB → ~136KB ✓
+ * T_BATCH=64: sOacc=128KB, sLogits=32KB, sP=32KB, rest=40KB → ~232KB (tight)
+ *
+ * Supports T=1..128. For T>128, caller must split into multiple launches.
+ */
+#pragma once
+
+#include <cuda_runtime.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <cstdint>
+#include <cmath>
+#include "fmha_common.cuh"
+#include "fmha_umma_desc.cuh"
+
+namespace dsv4::kernels::attention {
+
+struct FmhaMixedFp8PrefillParams {
+    const uint8_t* __restrict__ q_nope_fp8;   // (B,H,T,NOPE)
+    const float* __restrict__ q_nope_scale;   // (B,H,T)
+    const bf16_t* __restrict__ q_rope_bf16;   // (B,H,T,ROPE)
+
+    const uint8_t* __restrict__ k_nope_fp8;   // (N,NOPE), MQA shared
+    const float* __restrict__ k_nope_scale;   // (N,)
+    const bf16_t* __restrict__ k_rope_bf16;   // (N,ROPE)
+
+    bf16_t* __restrict__ o;                   // (B,H,T,HD)
+    float* __restrict__ lse;                  // (B,H,T), optional
+    const float* __restrict__ sink_bias;      // (B,H), optional
+
+    int B, H, T, N, HD, NOPE, ROPE;
+    int q_nope_t_stride, q_nope_head_stride, q_nope_batch_stride;
+    int q_scale_t_stride, q_scale_head_stride, q_scale_batch_stride;
+    int q_rope_t_stride, q_rope_head_stride, q_rope_batch_stride;
+    int o_head_stride, o_batch_stride, o_t_stride;
+    int lse_head_stride, lse_batch_stride, lse_t_stride;
+    float scale;
+};
+
+// ---- Reuse helpers from decode kernel ----
+
+__device__ __forceinline__ float _prefill_fp8_to_f32(uint8_t byte) {
+    __nv_fp8_e4m3 v; *reinterpret_cast<uint8_t*>(&v) = byte;
+    return static_cast<float>(v);
+}
+
+__device__ __forceinline__ int _pfill_cidx_f8(int r, int c) {
+    int cm = r >> 3, ck = c >> 4, lr = r & 7, lc = c & 15;
+    return ck * 16 * 128 + cm * 128 + lr * 16 + lc;
+}
+
+__device__ __forceinline__ int _pfill_cidx_bf16_128(int r, int c) {
+    int cm = r >> 3, ck = c >> 3, lr = r & 7, lc = c & 7;
+    return ck * 16 * 64 + cm * 64 + lr * 8 + lc;
+}
+
+__device__ __forceinline__ int _pfill_cidx_bf16_16(int r, int c) {
+    int cm = r >> 3, ck = c >> 3, lr = r & 7, lc = c & 7;
+    return ck * 2 * 64 + cm * 64 + lr * 8 + lc;
+}
+
+/**
+ * Read T_ACT rows of QK TMEM result into sLogits (T_ACT × SK_TILE).
+ *
+ * tcgen05.ld.32x32b.x8 reads 32 rows × 8 columns per call.
+ * Warp 0 → rows 0-31, Warp 1 → rows 32-63 (from SAME TMEM address).
+ * Rows 64-127 require TMEM base offset +256.
+ *
+ * Only warps 0 and 1 participate.
+ */
+template<int SK_TILE=128>
+__device__ void prefill_read_qk_rows(uint32_t tb, float* sLogits,
+                                      int T_ACT, int kv_len) {
+    const int wid = threadIdx.x >> 5;
+    const int lane = threadIdx.x & 31;
+    if (wid >= 2) return;
+
+    // 2 super-groups: rows 0-63 (tb+0), rows 64-127 (tb+256)
+    for (int sg = 0; sg < 2; sg++) {
+        int row_base = sg * 64;
+        if (row_base >= T_ACT) break;
+
+        uint32_t sg_off = sg * 256;
+        int warp_row = row_base + (wid == 0 ? 0 : 32);
+        if (warp_row >= T_ACT) continue;
+
+        for (int n = 0; n < SK_TILE / 8; n++) {
+            float tmp[8];
+            asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
+                : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
+                  "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
+                : "r"(tb + sg_off + n * 8));
+            asm volatile("tcgen05.wait::ld.sync.aligned;" ::: "memory");
+
+            int row = warp_row + lane;
+            if (row < T_ACT) {
+                #pragma unroll
+                for (int c = 0; c < 8; c++) {
+                    int col = n * 8 + c;
+                    sLogits[row * SK_TILE + col] = (col < kv_len) ? tmp[c] : -INFINITY;
+                }
+            }
+        }
+    }
+}
+
+/**
+ * Read a single row (query row qr) from PV TMEM result.
+ * The PV MMA result has 128 rows, but only row qr has valid data.
+ * Using tcgen05.ld.32x32b.x8, lane (qr % 32) holds row qr's data.
+ * For qr >= 64, offset TMEM base by 256.
+ *
+ * Writes 16 values (one n_sub PV output) to sOacc[qr*HD + d_base + 0..15].
+ */
+/**
+ * Read a single row (query row qr) from ALL PV TMEM results.
+ * Uses the SAME approach as the decode kernel PV read, but extracts
+ * from the lane corresponding to row qr instead of always lane 0.
+ *
+ * For qr < 32: warp 0, lane qr
+ * For qr 32-63: warp 1, lane (qr-32) -- same TMEM address, different rows
+ * For qr 64-95: same but TMEM offset +256
+ * For qr 96-127: same but TMEM offset +256
+ *
+ * This mirrors the proven decode kernel read pattern exactly.
+ */
+template<int HD=512, int N_SUB=32>
+__device__ void prefill_read_pv_all_subs(uint32_t tb, int qr,
+                                          float* sOacc, float rescale) {
+    const int lane = threadIdx.x & 31;
+    const int wid = threadIdx.x >> 5;
+
+    int local_lane = qr % 32;
+    int target_wid = (qr < 32) ? 0 : 1;
+    uint32_t rg_off = (qr >= 64) ? 256 : 0;
+
+    for (int n = 0; n < HD / 8; n++) {
+        float tmp[8];
+        if (wid == target_wid) {
+            asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
+                : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
+                  "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
+                : "r"(tb + rg_off + n * 8));
+            asm volatile("tcgen05.wait::ld.sync.aligned;" ::: "memory");
+        }
+
+        if (wid == target_wid && lane == local_lane) {
+            #pragma unroll
+            for (int c = 0; c < 8; c++) {
+                int d = n * 8 + c;
+                sOacc[qr * HD + d] += tmp[c] * rescale;
+            }
+        }
+    }
+}
+
+/**
+ * Prefill kernel: T query rows, processing in T_BATCH sub-batches.
+ *
+ * T_BATCH controls the SMEM usage. T_BATCH=32 uses ~136KB. T_BATCH=64 uses ~232KB.
+ * For each sub-batch of T_BATCH rows, we iterate over all KV tiles, computing
+ * QK → softmax → PV for those rows.
+ */
+template<int HD=512, int NOPE=448, int ROPE=64, int SK_TILE=128, int T_BATCH=32>
+__global__ void __launch_bounds__(192)
+fmha_mixed_fp8_prefill_kernel(FmhaMixedFp8PrefillParams p) {
+    static_assert(HD == 512 && NOPE == 448 && ROPE == 64,
+        "B1 prefill kernel specialized for DSV4 HD=512/NOPE=448/ROPE=64");
+
+    constexpr int MMA_K_F8 = 32;
+    constexpr int MMA_K_F16 = 16;
+    constexpr int NKT_NOPE = NOPE / MMA_K_F8;
+    constexpr int NKT_ROPE = ROPE / MMA_K_F16;
+    constexpr int NKT_PV = SK_TILE / MMA_K_F16;
+    constexpr int N_SUB = HD / 16;
+    constexpr int TILE_F8 = 128 * MMA_K_F8;
+    constexpr int TILE_F16 = 128 * MMA_K_F16;
+    constexpr int V_SUB_SZ = 16 * MMA_K_F16;
+    constexpr int TMEM_COLS = 512;
+
+    const int head_idx = blockIdx.y;
+    const int batch_idx = blockIdx.z;
+    const int tid = threadIdx.x;
+    const int wid = tid >> 5;
+    const int lane = tid & 31;
+    const bool is_mma_warp = (wid == 4);
+    const int n_kv_tiles = (p.N + SK_TILE - 1) / SK_TILE;
+
+    const uint8_t* q8 = p.q_nope_fp8 + batch_idx * p.q_nope_batch_stride + head_idx * p.q_nope_head_stride;
+    const float* q8_scale = p.q_nope_scale + batch_idx * p.q_scale_batch_stride + head_idx * p.q_scale_head_stride;
+    const bf16_t* qrope = p.q_rope_bf16 + batch_idx * p.q_rope_batch_stride + head_idx * p.q_rope_head_stride;
+
+    // SMEM layout — sized for T_BATCH rows
+    extern __shared__ __align__(128) char sbuf[];
+    size_t off = 0;
+    uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off += 4;
+    off = (off + 127) & ~(size_t)127;
+    uint8_t* sQ8 = (uint8_t*)(sbuf + off); off += TILE_F8;
+    off = (off + 127) & ~(size_t)127;
+    uint8_t* sK8 = (uint8_t*)(sbuf + off); off += TILE_F8;
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sQ16 = (bf16_t*)(sbuf + off); off += TILE_F16 * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sK16 = (bf16_t*)(sbuf + off); off += TILE_F16 * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sPk = (bf16_t*)(sbuf + off); off += TILE_F16 * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    bf16_t* sV = (bf16_t*)(sbuf + off); off += V_SUB_SZ * sizeof(bf16_t);
+    off = (off + 127) & ~(size_t)127;
+    // Per-sub-batch SMEM
+    float* sLogits = (float*)(sbuf + off); off += T_BATCH * SK_TILE * sizeof(float);
+    float* sP = (float*)(sbuf + off); off += T_BATCH * SK_TILE * sizeof(float);
+    float* sOacc = (float*)(sbuf + off); off += T_BATCH * HD * sizeof(float);
+    float* sRunningMax = (float*)(sbuf + off); off += T_BATCH * sizeof(float);
+    float* sRunningSum = (float*)(sbuf + off); off += T_BATCH * sizeof(float);
+    bf16_t* sOepi = (bf16_t*)(sbuf + off); off += T_BATCH * HD * sizeof(bf16_t);
+
+    // TMEM alloc
+    if (is_mma_warp) tmem_alloc((uint32_t)__cvta_generic_to_shared(sTmemBase), TMEM_COLS);
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+    __syncthreads();
+    uint32_t tb = *sTmemBase;
+
+    const uint32_t idesc_f8_qk = make_idesc_f8_e4m3(128, 128);
+    const uint32_t idesc_f16_qk = make_idesc(128, 128);
+    const uint32_t idesc_pv = make_idesc(128, 16);
+
+    // ================================================================
+    // Outer loop: process T_BATCH rows at a time
+    // ================================================================
+    for (int t_start = 0; t_start < p.T; t_start += T_BATCH) {
+        int T_ACT = min(T_BATCH, p.T - t_start);
+
+        // Initialize accumulators for this sub-batch
+        for (int i = tid; i < T_ACT * HD; i += blockDim.x) sOacc[i] = 0.0f;
+        for (int t = tid; t < T_ACT; t += blockDim.x) {
+            sRunningMax[t] = -INFINITY;
+            sRunningSum[t] = 0.0f;
+        }
+        __syncthreads();
+
+        // ============================================================
+        // KV-tile loop (shared across all sub-batch rows)
+        // ============================================================
+        for (int kv_tile = 0; kv_tile < n_kv_tiles; kv_tile++) {
+            const int kv_start = kv_tile * SK_TILE;
+            const int kv_len = min(SK_TILE, p.N - kv_start);
+
+            // --------------------------------------------------------
+            // QK noPE: FP8 tensor cores
+            // Write T_ACT rows of Q (not just row 0)
+            // --------------------------------------------------------
+            for (int kt = 0; kt < NKT_NOPE; kt++) {
+                for (int i = tid; i < TILE_F8; i += blockDim.x) { sQ8[i] = 0; sK8[i] = 0; }
+                __syncthreads();
+                // T_ACT rows of Q
+                for (int r = tid; r < T_ACT; r += blockDim.x) {
+                    int qr = t_start + r;
+                    for (int c = 0; c < MMA_K_F8; c++) {
+                        int d = kt * MMA_K_F8 + c;
+                        sQ8[_pfill_cidx_f8(r, c)] = q8[qr * p.q_nope_t_stride + d];
+                    }
+                }
+                // K: same as decode
+                for (int i = tid; i < kv_len * MMA_K_F8; i += blockDim.x) {
+                    int r = i / MMA_K_F8, c = i % MMA_K_F8;
+                    int d = kt * MMA_K_F8 + c;
+                    sK8[_pfill_cidx_f8(r, c)] = p.k_nope_fp8[(int64_t)(kv_start + r) * NOPE + d];
+                }
+                __syncthreads();
+                if (is_mma_warp && lane == 0) {
+                    uint64_t dq = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sQ8), 128);
+                    uint64_t dk = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sK8), 128);
+                    umma_ss_f8f6f4(tb, dq, dk, idesc_f8_qk, kt > 0);
+                    asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+                }
+                __syncthreads();
+            }
+            asm volatile("fence.sc.gpu;" ::: "memory");
+            __syncthreads();
+
+            // Read all T_ACT rows of QK noPE result
+            prefill_read_qk_rows<SK_TILE>(tb, sLogits, T_ACT, kv_len);
+            __syncthreads();
+
+            // Apply Q and K scales
+            for (int r = tid; r < T_ACT; r += blockDim.x) {
+                int qr = t_start + r;
+                float q_s = q8_scale[qr * p.q_scale_t_stride];
+                for (int c = 0; c < kv_len; c++) {
+                    float ks = p.k_nope_scale[kv_start + c];
+                    sLogits[r * SK_TILE + c] *= q_s * ks;
+                }
+            }
+            __syncthreads();
+
+            // --------------------------------------------------------
+            // QK RoPE: BF16 tensor cores
+            // --------------------------------------------------------
+            for (int kt = 0; kt < NKT_ROPE; kt++) {
+                for (int i = tid; i < TILE_F16; i += blockDim.x) { sQ16[i] = 0; sK16[i] = 0; }
+                __syncthreads();
+                for (int r = tid; r < T_ACT; r += blockDim.x) {
+                    int qr = t_start + r;
+                    for (int c = 0; c < MMA_K_F16; c++) {
+                        int d = kt * MMA_K_F16 + c;
+                        sQ16[_pfill_cidx_bf16_128(r, c)] = qrope[qr * p.q_rope_t_stride + d];
+                    }
+                }
+                for (int i = tid; i < kv_len * MMA_K_F16; i += blockDim.x) {
+                    int r = i / MMA_K_F16, c = i % MMA_K_F16;
+                    int d = kt * MMA_K_F16 + c;
+                    sK16[_pfill_cidx_bf16_128(r, c)] = p.k_rope_bf16[(int64_t)(kv_start + r) * ROPE + d];
+                }
+                __syncthreads();
+                if (is_mma_warp && lane == 0) {
+                    uint64_t dq = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sQ16), 128);
+                    uint64_t dk = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sK16), 128);
+                    umma_ss_f16(tb, dq, dk, idesc_f16_qk, kt > 0);
+                    asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+                }
+                __syncthreads();
+            }
+            asm volatile("fence.sc.gpu;" ::: "memory");
+            __syncthreads();
+
+            // Add RoPE logits to noPE logits (reuse sP as temp buffer)
+            prefill_read_qk_rows<SK_TILE>(tb, sP, T_ACT, kv_len);
+            __syncthreads();
+            for (int i = tid; i < T_ACT * kv_len; i += blockDim.x) {
+                sLogits[i] += sP[i];
+            }
+            __syncthreads();
+
+            // --------------------------------------------------------
+            // Per-row softmax (online algorithm)
+            // Each thread handles a few rows
+            // --------------------------------------------------------
+            for (int r = tid; r < T_ACT; r += blockDim.x) {
+                float tile_max = -INFINITY;
+                for (int c = 0; c < kv_len; c++)
+                    tile_max = fmaxf(tile_max, sLogits[r * SK_TILE + c] * p.scale);
+
+                float tile_sum = 0.0f;
+                for (int c = 0; c < kv_len; c++) {
+                    float pv = expf(sLogits[r * SK_TILE + c] * p.scale - tile_max);
+                    sP[r * SK_TILE + c] = pv;
+                    tile_sum += pv;
+                }
+                for (int c = kv_len; c < SK_TILE; c++) sP[r * SK_TILE + c] = 0.0f;
+
+                float old_max = sRunningMax[r];
+                float new_max = fmaxf(old_max, tile_max);
+                float rescale_old = (old_max > -INFINITY) ? expf(old_max - new_max) : 0.0f;
+                for (int d = 0; d < HD; d++) sOacc[r * HD + d] *= rescale_old;
+                float rescale_new = expf(tile_max - new_max);
+                sRunningSum[r] = sRunningSum[r] * rescale_old + tile_sum * rescale_new;
+                sRunningMax[r] = new_max;
+
+                // Store rescale_new for PV (reuse sLogits first column)
+                sLogits[r * SK_TILE] = rescale_new;
+            }
+            __syncthreads();
+
+            // --------------------------------------------------------
+            // PV: per query row (one PV MMA per row)
+            // TODO: batch all T_ACT rows into one PV MMA for performance
+            // --------------------------------------------------------
+            for (int qr = 0; qr < T_ACT; qr++) {
+                float p_rescale = sLogits[qr * SK_TILE];
+
+                for (int n_sub = 0; n_sub < N_SUB; n_sub++) {
+                    int d_base = n_sub * 16;
+                    for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
+                        const int col_start = pv_kt * MMA_K_F16;
+                        for (int i = tid; i < TILE_F16; i += blockDim.x) sPk[i] = 0;
+                        for (int i = tid; i < V_SUB_SZ; i += blockDim.x) sV[i] = 0;
+                        __syncthreads();
+
+                        // P matrix: only row qr is active
+                        for (int c = tid; c < MMA_K_F16; c += blockDim.x) {
+                            int gc = col_start + c;
+                            sPk[_pfill_cidx_bf16_128(qr, c)] = f32_to_bf16(sP[qr * SK_TILE + gc]);
+                        }
+
+                        // V matrix (same as decode)
+                        for (int i = tid; i < 16 * MMA_K_F16; i += blockDim.x) {
+                            int dd = i / MMA_K_F16, kk = i % MMA_K_F16;
+                            int row = col_start + kk;
+                            int g_row = kv_start + row;
+                            int d = d_base + dd;
+                            bf16_t vbits = 0;
+                            if (row < kv_len) {
+                                if (d < NOPE) {
+                                    uint8_t b = p.k_nope_fp8[(int64_t)g_row * NOPE + d];
+                                    float v = _prefill_fp8_to_f32(b) * p.k_nope_scale[g_row];
+                                    vbits = f32_to_bf16(v);
+                                } else {
+                                    vbits = p.k_rope_bf16[(int64_t)g_row * ROPE + (d - NOPE)];
+                                }
+                            }
+                            sV[_pfill_cidx_bf16_16(dd, kk)] = vbits;
+                        }
+                        __syncthreads();
+
+                        bool first = (pv_kt == 0);  // Fresh for each query row's PV
+                        if (is_mma_warp && lane == 0) {
+                            uint64_t dp = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sPk), 128);
+                            uint64_t dv = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sV), 16);
+                            umma_ss_f16(tb + n_sub * 16, dp, dv, idesc_pv, !first);
+                            asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+                        }
+                        __syncthreads();
+                    }  // pv_kt
+                }  // n_sub
+
+                // Read PV result for row qr from TMEM
+                asm volatile("fence.sc.gpu;" ::: "memory");
+                __syncthreads();
+                prefill_read_pv_all_subs<HD, N_SUB>(tb, qr, sOacc, p_rescale);
+                __syncthreads();
+            }  // qr
+        }  // kv_tile
+
+        // --------------------------------------------------------
+        // Attention sink
+        // --------------------------------------------------------
+        if (p.sink_bias != nullptr) {
+            float sb = p.sink_bias[batch_idx * p.H + head_idx];
+            for (int r = tid; r < T_ACT; r += blockDim.x) {
+                float old_max = sRunningMax[r];
+                float new_max = fmaxf(old_max, sb);
+                float rescale_old = (old_max > -INFINITY) ? expf(old_max - new_max) : 0.0f;
+                for (int d = 0; d < HD; d++) sOacc[r * HD + d] *= rescale_old;
+                sRunningSum[r] = sRunningSum[r] * rescale_old + expf(sb - new_max);
+                sRunningMax[r] = new_max;
+            }
+            __syncthreads();
+        }
+
+        // --------------------------------------------------------
+        // Normalize and write output
+        // --------------------------------------------------------
+        bf16_t* out = p.o + batch_idx * p.o_batch_stride + head_idx * p.o_head_stride;
+        float* lse = p.lse ? p.lse + batch_idx * p.lse_batch_stride + head_idx * p.lse_head_stride : nullptr;
+
+        for (int r = tid; r < T_ACT; r += blockDim.x) {
+            float inv_sum = 1.0f / sRunningSum[r];
+            int qr = t_start + r;
+            for (int d = 0; d < HD; d++) {
+                bf16_t val = f32_to_bf16(sOacc[r * HD + d] * inv_sum);
+                sOepi[r * HD + d] = val;
+            }
+            if (lse) lse[qr * p.lse_t_stride] = logf(sRunningSum[r]) + sRunningMax[r];
+        }
+        __syncthreads();
+
+        // Write to GMEM
+        for (int r = 0; r < T_ACT; r++) {
+            int qr = t_start + r;
+            bf16_t* out_row = out + qr * p.o_t_stride;
+            for (int d = tid; d < HD; d += blockDim.x) out_row[d] = sOepi[r * HD + d];
+        }
+        __syncthreads();
+
+    }  // t_start sub-batch loop
+
+    if (is_mma_warp) tmem_dealloc(tb, TMEM_COLS);
+}
+
+} // namespace dsv4::kernels::attention

dsv4/kernels/attention/fmha_mixed_fp8_prefill_capi.cu

@@ -0,0 +1,95 @@
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cstdint>
+#include "fmha_common.cuh"
+#include "fmha_umma_desc.cuh"
+#include "fmha_mixed_fp8_prefill.cuh"
+
+using namespace dsv4::kernels::attention;
+
+extern "C" {
+
+int fmha_mixed_fp8_prefill_launch(
+    const void* q_nope_fp8,
+    const float* q_nope_scale,
+    const void* q_rope_bf16,
+    const void* k_nope_fp8,
+    const float* k_nope_scale,
+    const void* k_rope_bf16,
+    void* o_ptr,
+    void* lse_ptr,
+    const float* sink_bias_ptr,
+    int B, int H, int T, int N, int HD, int NOPE, int ROPE,
+    int q_nope_t_stride, int q_nope_head_stride, int q_nope_batch_stride,
+    int q_scale_t_stride, int q_scale_head_stride, int q_scale_batch_stride,
+    int q_rope_t_stride, int q_rope_head_stride, int q_rope_batch_stride,
+    int o_head_stride, int o_batch_stride, int o_t_stride,
+    int lse_head_stride, int lse_batch_stride, int lse_t_stride,
+    float scale
+) {
+    if (HD != 512 || NOPE != 448 || ROPE != 64) return -2;
+    if (T < 1 || T > 128) return -3;
+
+    FmhaMixedFp8PrefillParams p;
+    p.q_nope_fp8 = (const uint8_t*)q_nope_fp8;
+    p.q_nope_scale = q_nope_scale;
+    p.q_rope_bf16 = (const bf16_t*)q_rope_bf16;
+    p.k_nope_fp8 = (const uint8_t*)k_nope_fp8;
+    p.k_nope_scale = k_nope_scale;
+    p.k_rope_bf16 = (const bf16_t*)k_rope_bf16;
+    p.o = (bf16_t*)o_ptr;
+    p.lse = (float*)lse_ptr;
+    p.sink_bias = sink_bias_ptr;
+    p.B = B; p.H = H; p.T = T; p.N = N;
+    p.HD = HD; p.NOPE = NOPE; p.ROPE = ROPE;
+    p.q_nope_t_stride = q_nope_t_stride;
+    p.q_nope_head_stride = q_nope_head_stride;
+    p.q_nope_batch_stride = q_nope_batch_stride;
+    p.q_scale_t_stride = q_scale_t_stride;
+    p.q_scale_head_stride = q_scale_head_stride;
+    p.q_scale_batch_stride = q_scale_batch_stride;
+    p.q_rope_t_stride = q_rope_t_stride;
+    p.q_rope_head_stride = q_rope_head_stride;
+    p.q_rope_batch_stride = q_rope_batch_stride;
+    p.o_head_stride = o_head_stride;
+    p.o_batch_stride = o_batch_stride;
+    p.o_t_stride = o_t_stride;
+    p.lse_head_stride = lse_head_stride;
+    p.lse_batch_stride = lse_batch_stride;
+    p.lse_t_stride = lse_t_stride;
+    p.scale = scale;
+
+    // SMEM size for T_BATCH=32
+    constexpr int T_BATCH = 32;
+    constexpr int SK_TILE = 128;
+    constexpr int TILE_F8 = 128 * 32;
+    constexpr int TILE_F16 = 128 * 16;
+    constexpr int V_SUB_SZ = 16 * 16;
+    int smem = 0;
+    smem += 4; smem = (smem + 127) & ~127;
+    smem += TILE_F8; smem = (smem + 127) & ~127;           // sQ8
+    smem += TILE_F8; smem = (smem + 127) & ~127;           // sK8
+    smem += TILE_F16 * 2; smem = (smem + 127) & ~127;      // sQ16
+    smem += TILE_F16 * 2; smem = (smem + 127) & ~127;      // sK16
+    smem += TILE_F16 * 2; smem = (smem + 127) & ~127;      // sPk
+    smem += V_SUB_SZ * 2; smem = (smem + 127) & ~127;      // sV
+    smem += T_BATCH * SK_TILE * 4;                           // sLogits
+    smem += T_BATCH * SK_TILE * 4;                           // sP
+    smem += T_BATCH * 512 * 4;                               // sOacc
+    smem += T_BATCH * 4;                                     // sRunningMax
+    smem += T_BATCH * 4;                                     // sRunningSum
+    smem += T_BATCH * 512 * 2;                               // sOepi
+    smem = (smem + 127) & ~127;
+
+    cudaFuncSetAttribute(
+        fmha_mixed_fp8_prefill_kernel<512,448,64,128,32>,
+        cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
+    dim3 grid(1, H, B);
+    dim3 block(192);
+    fmha_mixed_fp8_prefill_kernel<512,448,64,128,32>
+        <<<grid, block, smem>>>(p);
+    cudaError_t err = cudaGetLastError();
+    return err == cudaSuccess ? 0 : (int)err;
+}
+
+} // extern C

dsv4/kernels/attention/fmha_mixed_fp8_prefill_op.py

@@ -0,0 +1,149 @@
+"""DSV4 B1 mixed FP8/BF16 prefill FMHA loader.
+
+Supports T > 1 for batched prefill. Same storage-native format as the
+decode kernel: FP8_E4M3 for noPE KV, BF16 for RoPE KV.
+"""
+import ctypes
+import logging
+import os
+import subprocess
+from typing import Optional
+
+import torch
+
+logger = logging.getLogger(__name__)
+
+KERNEL_DIR = os.path.dirname(os.path.abspath(__file__))
+REPO_ROOT = os.path.normpath(os.path.join(KERNEL_DIR, "..", ".."))
+SOURCE = os.path.join(KERNEL_DIR, "fmha_mixed_fp8_prefill_capi.cu")
+BUILD_DIR = os.path.join(REPO_ROOT, "build", "fmha_mixed_fp8_prefill")
+SO_NAME = "libfmha_mixed_fp8_prefill.so"
+
+_lib = None
+_lib_lock = False
+
+
+def _find_nvcc():
+    import shutil
+    for c in ["/usr/local/cuda-13.2/bin/nvcc", "/usr/local/cuda/bin/nvcc"]:
+        if os.path.isfile(c):
+            return c
+    nvcc = shutil.which("nvcc")
+    if nvcc:
+        return nvcc
+    raise RuntimeError("nvcc not found")
+
+
+def _ensure_built():
+    global _lib, _lib_lock
+    if _lib is not None:
+        return _lib
+    if _lib_lock:
+        raise RuntimeError("Recursive mixed-FP8 prefill FMHA build")
+    _lib_lock = True
+    try:
+        so_path = os.path.join(BUILD_DIR, SO_NAME)
+        deps = [
+            SOURCE,
+            os.path.join(KERNEL_DIR, "fmha_common.cuh"),
+            os.path.join(KERNEL_DIR, "fmha_umma_desc.cuh"),
+            os.path.join(KERNEL_DIR, "fmha_mixed_fp8_prefill.cuh"),
+        ]
+        src_mtime = max(os.path.getmtime(p) for p in deps if os.path.exists(p))
+        need_build = not os.path.isfile(so_path) or src_mtime > os.path.getmtime(so_path)
+        if not need_build:
+            _lib = ctypes.CDLL(so_path)
+            return _lib
+
+        os.makedirs(BUILD_DIR, exist_ok=True)
+        nvcc = _find_nvcc()
+        cmd = [
+            nvcc, "-std=c++20", "-shared", "-Xcompiler", "-fPIC",
+            "-gencode=arch=compute_100a,code=sm_100a",
+            "-gencode=arch=compute_100a,code=compute_100a",
+            f"-I{KERNEL_DIR}", f"-I{REPO_ROOT}",
+            "-O3", "--use_fast_math", "--expt-relaxed-constexpr",
+            SOURCE, "-o", so_path, "-lcudart", "-lcuda",
+        ]
+        logger.info("Building libfmha_mixed_fp8_prefill.so (sm_100a)...")
+        res = subprocess.run(cmd, capture_output=True, text=True)
+        if res.returncode != 0:
+            raise RuntimeError(f"mixed FP8 prefill FMHA nvcc failed:\n{res.stderr}")
+        _lib = ctypes.CDLL(so_path)
+        return _lib
+    finally:
+        _lib_lock = False
+
+
+def _quantize_q_split(q: torch.Tensor, rope_dim: int):
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("fp8_attention_io", ["fp8_attention_io.cu"],
+                          extra_cuda_cflags=[
+                              "-gencode=arch=compute_100a,code=sm_100a",
+                              "-O3", "--use_fast_math", "--expt-relaxed-constexpr",
+                          ])
+    return mod.quantize_q_fp8_split(q, rope_dim)
+
+
+def fmha_mixed_fp8_prefill_raw(
+    q: torch.Tensor,                 # (B,H,T,HD) BF16
+    k_nope_fp8: torch.Tensor,        # (N,NOPE) uint8/float8_e4m3fn
+    k_nope_scale: torch.Tensor,      # (N,) FP32
+    k_rope_bf16: torch.Tensor,       # (N,ROPE) BF16
+    scale: float,
+    attn_sink: Optional[torch.Tensor] = None,
+    rope_dim: int = 64,
+):
+    """Mixed FP8/BF16 prefill FMHA. Supports T = 1..128."""
+    if q.dim() != 4:
+        raise RuntimeError("q must be (B,H,T,HD)")
+    B, H, T, HD = q.shape
+    if T < 1 or T > 128:
+        raise RuntimeError(f"mixed FP8 prefill FMHA supports 1 ≤ T ≤ 128, got T={T}")
+    NOPE = HD - rope_dim
+    if HD != 512 or NOPE != 448 or rope_dim != 64:
+        raise RuntimeError(f"First pass supports HD=512/NOPE=448/ROPE=64, got {HD}/{NOPE}/{rope_dim}")
+
+    q = q.contiguous()
+    k_nope_fp8 = k_nope_fp8.contiguous()
+    k_nope_scale = k_nope_scale.contiguous()
+    k_rope_bf16 = k_rope_bf16.contiguous()
+    q_nope_fp8, q_nope_scale, q_rope = _quantize_q_split(q, rope_dim)
+
+    N = k_nope_fp8.shape[0]
+    o = torch.empty((B, H, T, HD), dtype=torch.bfloat16, device=q.device)
+    lse = torch.empty((B, H, T), dtype=torch.float32, device=q.device)
+
+    sink_ptr = ctypes.c_void_p(0)
+    sb = None
+    if attn_sink is not None:
+        sb = attn_sink.float().contiguous()
+        if sb.dim() == 1:
+            sb = sb.unsqueeze(0).expand(B, -1).contiguous()
+        if tuple(sb.shape) != (B, H):
+            raise RuntimeError(f"sink bias shape {tuple(sb.shape)} != {(B,H)}")
+        sink_ptr = ctypes.c_void_p(sb.data_ptr())
+
+    lib = _ensure_built()
+    ret = lib.fmha_mixed_fp8_prefill_launch(
+        ctypes.c_void_p(q_nope_fp8.data_ptr()),
+        ctypes.c_void_p(q_nope_scale.data_ptr()),
+        ctypes.c_void_p(q_rope.data_ptr()),
+        ctypes.c_void_p(k_nope_fp8.data_ptr()),
+        ctypes.c_void_p(k_nope_scale.data_ptr()),
+        ctypes.c_void_p(k_rope_bf16.data_ptr()),
+        ctypes.c_void_p(o.data_ptr()),
+        ctypes.c_void_p(lse.data_ptr()),
+        sink_ptr,
+        ctypes.c_int(B), ctypes.c_int(H), ctypes.c_int(T), ctypes.c_int(N),
+        ctypes.c_int(HD), ctypes.c_int(NOPE), ctypes.c_int(rope_dim),
+        ctypes.c_int(q_nope_fp8.stride(2)), ctypes.c_int(q_nope_fp8.stride(1)), ctypes.c_int(q_nope_fp8.stride(0)),
+        ctypes.c_int(q_nope_scale.stride(2)), ctypes.c_int(q_nope_scale.stride(1)), ctypes.c_int(q_nope_scale.stride(0)),
+        ctypes.c_int(q_rope.stride(2)), ctypes.c_int(q_rope.stride(1)), ctypes.c_int(q_rope.stride(0)),
+        ctypes.c_int(o.stride(1)), ctypes.c_int(o.stride(0)), ctypes.c_int(o.stride(2)),
+        ctypes.c_int(lse.stride(1)), ctypes.c_int(lse.stride(0)), ctypes.c_int(lse.stride(2)),
+        ctypes.c_float(scale),
+    )
+    if ret != 0:
+        raise RuntimeError(f"mixed FP8 prefill FMHA launch failed: return code {ret}")
+    return o, lse

dsv4/kernels/attention/fmha_umma_desc.cuh

@@ -340,4 +340,31 @@ __device__ __forceinline__ uint32_t make_idesc(int block_m, int block_n) {
          | ((uint32_t)(block_m >> 4) << 24); // MMA_M
 }
 
+/**
+ * tcgen05.mma SS for .kind::f8f6f4 with E4M3xE4M3 -> FP32.
+ * A and B element types are encoded in idesc. For B1 we use E4M3/E4M3.
+ */
+__device__ void umma_ss_f8f6f4(
+    uint32_t tmem_c, uint64_t desc_a, uint64_t desc_b,
+    uint32_t i_desc, bool accumulate = false
+) {
+    uint32_t scaleC_bits = accumulate ? 0x3F800000u : 0u;
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "setp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], %1, %2, %3, p;\n\t"
+        "}"
+        :: "r"(tmem_c), "l"(desc_a), "l"(desc_b),
+           "r"(i_desc), "r"(scaleC_bits)
+    );
+}
+
+/** Instruction descriptor for .kind::f8f6f4 E4M3 x E4M3 -> FP32. */
+__device__ __forceinline__ uint32_t make_idesc_f8_e4m3(int block_m, int block_n) {
+    return (1U << 4)                         // dtype = F32
+         | ((uint32_t)(block_n >> 3) << 17)  // MMA_N
+         | ((uint32_t)(block_m >> 4) << 24); // MMA_M
+}
+
 } // namespace dsv4::kernels::attention

dsv4/kernels/attention/production.py

@@ -195,3 +195,78 @@ def dsv4_attention_per_head(
             output[q_idx] = o
 
     return output
+
+
+# ---------------------------------------------------------------------------
+# B1: mixed FP8/BF16 DeepSeek-V4 decode attention
+# ---------------------------------------------------------------------------
+
+def dsv4_attention_mixed_fp8_decode(
+    q: torch.Tensor,                 # (n_q_heads,T,HD) or (B,n_q_heads,T,HD) BF16
+    k_nope_fp8: torch.Tensor,        # (N,NOPE) uint8/float8_e4m3fn
+    k_nope_scale: torch.Tensor,      # (N,) FP32
+    k_rope_bf16: torch.Tensor,       # (N,ROPE) BF16
+    scale: Optional[float] = None,
+    sink_bias: Optional[torch.Tensor] = None,
+    rope_dim: int = 64,
+) -> torch.Tensor:
+    """B1 production path: storage-native FP8/BF16 KV decode FMHA.
+
+    This intentionally has no PyTorch/BF16 fallback. It is the decode-only path
+    for DeepSeek-V4 attention where noPE KV is already stored as FP8_E4M3 with
+    per-row FP32 scales and RoPE KV is BF16.
+    """
+    from dsv4.kernels.attention.fmha_mixed_fp8_op import fmha_mixed_fp8_decode_raw
+
+    has_batch = q.dim() == 4
+    if q.dim() == 3:
+        q4 = q.unsqueeze(0).contiguous()
+    elif q.dim() == 4:
+        q4 = q.contiguous()
+    else:
+        raise RuntimeError("q must be (H,T,HD) or (B,H,T,HD)")
+
+    hd = q4.shape[-1]
+    scale = scale or (1.0 / math.sqrt(hd))
+    o4, _lse = fmha_mixed_fp8_decode_raw(
+        q4, k_nope_fp8, k_nope_scale, k_rope_bf16,
+        scale, attn_sink=sink_bias, rope_dim=rope_dim,
+    )
+    return o4 if has_batch else o4.squeeze(0)
+
+
+# ---------------------------------------------------------------------------
+# B1: mixed FP8/BF16 DeepSeek-V4 PREFILL attention (T > 1)
+# ---------------------------------------------------------------------------
+
+def dsv4_attention_mixed_fp8_prefill(
+    q: torch.Tensor,                 # (n_q_heads,T,HD) or (B,n_q_heads,T,HD) BF16
+    k_nope_fp8: torch.Tensor,        # (N,NOPE) uint8/float8_e4m3fn
+    k_nope_scale: torch.Tensor,      # (N,) FP32
+    k_rope_bf16: torch.Tensor,       # (N,ROPE) BF16
+    scale: Optional[float] = None,
+    sink_bias: Optional[torch.Tensor] = None,
+    rope_dim: int = 64,
+) -> torch.Tensor:
+    """B1 production path: storage-native FP8/BF16 KV prefill FMHA.
+
+    Supports T = 1..128. For T > 128, caller must split into multiple launches.
+    Uses the same mixed FP8/BF16 KV format as the decode path.
+    """
+    from dsv4.kernels.attention.fmha_mixed_fp8_prefill_op import fmha_mixed_fp8_prefill_raw
+
+    has_batch = q.dim() == 4
+    if q.dim() == 3:
+        q4 = q.unsqueeze(0).contiguous()  # (1, H, T, HD)
+    elif q.dim() == 4:
+        q4 = q.contiguous()
+    else:
+        raise RuntimeError("q must be (H,T,HD) or (B,H,T,HD)")
+
+    hd = q4.shape[-1]
+    scale = scale or (1.0 / math.sqrt(hd))
+    o4, _lse = fmha_mixed_fp8_prefill_raw(
+        q4, k_nope_fp8, k_nope_scale, k_rope_bf16,
+        scale, attn_sink=sink_bias, rope_dim=rope_dim,
+    )
+    return o4 if has_batch else o4.squeeze(0)

dsv4/kernels/compressor/__init__.py

@@ -1,56 +1,5 @@
 """CSA/HCA compressor — Python API bridge.
 
-Wraps the compression functions with the interface that
-AttentionSubBlock and flush.py expect.
-
-The compressor runs token-level softmax over m entries (CSA) or m' entries (HCA)
-to produce compressed KV entries. The compressed entries are then written to the
-paged pool by the flush_write kernel.
+See dsv4/kernels/compressor/production_compress.py for the live path.
+See dsv4/kernels/cuda/compressor_reduce.cu for the CUDA kernel.
 """
-import torch
-from typing import TYPE_CHECKING
-
-if TYPE_CHECKING:
-    from dsv4.cache.handle import LayerCacheHandle
-
-from dsv4.kernels.compressor.compress_tail import csa_compress_tail, hca_compress_tail
-
-
-def csa_compress_and_store(
-    kv_raw: torch.Tensor,          # (T, head_dim) BF16 — current KV (goes to tail)
-    cache: "LayerCacheHandle",     # reads tail, writes compressed to paged pool
-) -> None:
-    """CSA: compress KV entries and store into the classical paged cache.
-
-    Steps:
-    1. Check if tail has enough entries (tail_len >= m=4)
-    2. If so, run compression (csa_compress_tail)
-    3. Write compressed output to paged pool via flush_write
-    4. Update tail buffer (a-stream becomes next b-stream)
-    """
-    from dsv4.kernels.cuda.flush_write import flush_write_csa_cuda
-    # NOTE: This function is called from AttentionSubBlock.forward, which
-    # writes the raw KV to the tail buffer first (via cache.write_swa).
-    # The actual compression + flush happens when tail_len >= m.
-    # For now, the write_swa call handles the tail buffer write.
-    # The flush is triggered separately by the flush pipeline.
-    # See dsv4/cache/flush.py for the flush orchestration.
-    pass  # Compression is handled by flush.py, not directly here
-
-
-def hca_compress_and_store(
-    kv_raw: torch.Tensor,          # (T, head_dim) BF16
-    cache: "LayerCacheHandle",     # reads tail, writes compressed to paged pool
-) -> None:
-    """HCA: compress KV entries and store into the classical paged cache.
-
-    Same structure as CSA but no b-stream, no overlap, m'=128.
-    """
-    pass  # See flush.py
-
-
-# Make compress_tail functions importable from this package
-__all__ = [
-    'csa_compress_and_store', 'hca_compress_and_store',
-    'csa_compress_tail', 'hca_compress_tail',
-]

dsv4/kernels/compressor/production_compress.py

@@ -6,6 +6,9 @@ Pipeline:
   3. CUDA kernel: token-level softmax(gate) * kv → compressed entries
   4. CUDA kernel: kv_norm (unweighted RMSNorm + weight)
 
+KV-1/KV-2: NVFP4 output variants compress + quantize in a single kernel.
+No intermediate BF16. Stored as FP4 data + E4M3 block scales + FP32 global scale.
+
 No PyTorch softmax. No reference fallback. All on the GPU.
 """
 
@@ -40,27 +43,28 @@ def csa_compress_production(
     kv_norm_weight: Optional[torch.Tensor], # (hd) BF16 or None
     m: int = 4,
 ) -> torch.Tensor:
-    """CSA compress: softmax + weighted sum + kv_norm.
+    """CSA compress: softmax + weighted sum + kv_norm. Returns BF16."""
+    return csa_compress_production_fp32(
+        kv_proj_out, gate_proj_out, position_bias, kv_norm_weight, m
+    ).bfloat16()
 
-    Args:
-        kv_proj_out: FP32 projection output, (T, 2*hd), Ca in first hd cols, Cb in second
-        gate_proj_out: FP32 projection output, (T, 2*hd), Ga in first hd cols, Gb in second
-        position_bias: (m, 2*hd) BF16 position bias, or None
-        kv_norm_weight: (hd) BF16 norm weight, or None
-        m: compression ratio (4 for CSA)
 
-    Returns:
-        compressed: (n_blocks, hd) BF16
-    """
+def csa_compress_production_fp32(
+    kv_proj_out: torch.Tensor,
+    gate_proj_out: torch.Tensor,
+    position_bias: Optional[torch.Tensor],
+    kv_norm_weight: Optional[torch.Tensor],
+    m: int = 4,
+) -> torch.Tensor:
+    """CSA compress: softmax + weighted sum + kv_norm. Returns FP32."""
     T = kv_proj_out.shape[0]
     hd = kv_proj_out.shape[1] // 2
     n_blocks = T // m
     if n_blocks == 0:
-        return torch.zeros(0, hd, dtype=torch.bfloat16, device=kv_proj_out.device)
+        return torch.zeros(0, hd, dtype=torch.float32, device=kv_proj_out.device)
 
     mod = _get_kernel()
 
-    # Convert position_bias and kv_norm_weight to FP32
     pos_bias_f32 = torch.empty(0, dtype=torch.float32, device=kv_proj_out.device)
     if position_bias is not None:
         pos_bias_f32 = position_bias.float()
@@ -80,7 +84,7 @@ def csa_compress_production(
         m, n_blocks,
     )
 
-    return compressed.bfloat16()
+    return compressed
 
 
 def hca_compress_production(
@@ -90,23 +94,25 @@ def hca_compress_production(
     kv_norm_weight: Optional[torch.Tensor], # (hd) BF16 or None
     m: int = 128,
 ) -> torch.Tensor:
-    """HCA compress: softmax + weighted sum + kv_norm.
+    """HCA compress: softmax + weighted sum + kv_norm. Returns BF16."""
+    return hca_compress_production_fp32(
+        kv_proj_out, gate_proj_out, position_bias, kv_norm_weight, m
+    ).bfloat16()
 
-    Args:
-        kv_proj_out: FP32 projection output, (T, hd)
-        gate_proj_out: FP32 projection output, (T, hd)
-        position_bias: (m, hd) BF16 position bias, or None
-        kv_norm_weight: (hd) BF16 norm weight, or None
-        m: compression ratio (128 for HCA)
 
-    Returns:
-        compressed: (n_blocks, hd) BF16
-    """
+def hca_compress_production_fp32(
+    kv_proj_out: torch.Tensor,
+    gate_proj_out: torch.Tensor,
+    position_bias: Optional[torch.Tensor],
+    kv_norm_weight: Optional[torch.Tensor],
+    m: int = 128,
+) -> torch.Tensor:
+    """HCA compress: softmax + weighted sum + kv_norm. Returns FP32."""
     T = kv_proj_out.shape[0]
     hd = kv_proj_out.shape[1]
     n_blocks = T // m
     if n_blocks == 0:
-        return torch.zeros(0, hd, dtype=torch.bfloat16, device=kv_proj_out.device)
+        return torch.zeros(0, hd, dtype=torch.float32, device=kv_proj_out.device)
 
     mod = _get_kernel()
 
@@ -129,4 +135,90 @@ def hca_compress_production(
         m, n_blocks,
     )
 
-    return compressed.bfloat16()
+    return compressed
+
+
+# ===========================================================================
+# KV-1/KV-2: NVFP4 output — two proven kernels, no BF16 intermediate
+#
+# Architecture:
+#   1. CUDA compress kernel (compressor_reduce.cu) → FP32 compressed output
+#   2. CUDA amax_gsa_fp32 → per-row gsa (GPU-only, no CPU sync)
+#   3. CUDA quantize_nvfp4_from_fp32 → NVFP4 triple (fp4 + sf + gsa)
+#
+# This is the same two-kernel pattern that works everywhere else in the
+# pipeline (quantize_nvfp4_gpu_fused). The previous single-kernel fused
+# approach had shared memory corruption bugs. Two kernels is correct.
+#
+# Storage: NVFP4 (E2M1 data + E4M3 block scales + FP32 global scale)
+# Read path: dequant_nvfp4 / dequant_nvfp4_selective → BF16 for FMHA
+# ===========================================================================
+
+def _quantize_fp32_to_nvfp4(compressed_fp32: torch.Tensor) -> tuple:
+    """Quantize FP32 compressed output → NVFP4. Two-kernel, GPU-only.
+
+    Uses the same proven pattern as quantize_nvfp4_gpu_fused (amax_gsa +
+    quantize_from_buffer) but with FP32 input instead of BF16.
+    No BF16 intermediate. No CPU sync.
+
+    Returns: (fp4_data, block_scales, global_scales) — NVFP4 triple.
+    """
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("kv_quantize", ["kv_quantize.cu"])
+    # Kernel 1: Compute per-row gsa from FP32 input (GPU-only)
+    gsa = mod.compute_amax_gsa_fp32(compressed_fp32.contiguous(), 6.0 * 448.0)
+    # Kernel 2: Quantize FP32 → NVFP4 using GPU gsa buffer
+    fp4, sf = mod.quantize_nvfp4_from_fp32(compressed_fp32.contiguous(), gsa)
+    return fp4, sf, gsa
+
+
+def csa_compress_production_nvfp4(
+    kv_proj_out: torch.Tensor,
+    gate_proj_out: torch.Tensor,
+    position_bias: Optional[torch.Tensor],
+    kv_norm_weight: Optional[torch.Tensor],
+    m: int = 4,
+) -> tuple:
+    """CSA compress → NVFP4. No BF16 intermediate.
+
+    KV-1: Production path. Compressed KV stored as NVFP4.
+    Pipeline: compress (FP32) → amax_gsa (GPU) → quantize (GPU) → NVFP4 triple.
+    Returns: (fp4_data, block_scales, global_scales) — NVFP4 triple.
+    """
+    # Step 1: Compress → FP32 (same proven kernel as BF16 path)
+    compressed_fp32 = csa_compress_production_fp32(
+        kv_proj_out, gate_proj_out, position_bias, kv_norm_weight, m)
+    if compressed_fp32.shape[0] == 0:
+        dev = kv_proj_out.device
+        hd = kv_proj_out.shape[1] // 2
+        return (torch.zeros(0, hd // 2, dtype=torch.float4_e2m1fn_x2, device=dev),
+                torch.zeros(0, hd // 16, dtype=torch.float8_e4m3fn, device=dev),
+                torch.zeros(0, dtype=torch.float32, device=dev))
+    # Step 2-3: FP32 → NVFP4 (two proven kernels)
+    return _quantize_fp32_to_nvfp4(compressed_fp32)
+
+
+def hca_compress_production_nvfp4(
+    kv_proj_out: torch.Tensor,
+    gate_proj_out: torch.Tensor,
+    position_bias: Optional[torch.Tensor],
+    kv_norm_weight: Optional[torch.Tensor],
+    m: int = 128,
+) -> tuple:
+    """HCA compress → NVFP4. No BF16 intermediate.
+
+    KV-2: Production path. Compressed KV stored as NVFP4.
+    Pipeline: compress (FP32) → amax_gsa (GPU) → quantize (GPU) → NVFP4 triple.
+    Returns: (fp4_data, block_scales, global_scales) — NVFP4 triple.
+    """
+    # Step 1: Compress → FP32
+    compressed_fp32 = hca_compress_production_fp32(
+        kv_proj_out, gate_proj_out, position_bias, kv_norm_weight, m)
+    if compressed_fp32.shape[0] == 0:
+        dev = kv_proj_out.device
+        hd = kv_proj_out.shape[1]
+        return (torch.zeros(0, hd // 2, dtype=torch.float4_e2m1fn_x2, device=dev),
+                torch.zeros(0, hd // 16, dtype=torch.float8_e4m3fn, device=dev),
+                torch.zeros(0, dtype=torch.float32, device=dev))
+    # Step 2-3: FP32 → NVFP4
+    return _quantize_fp32_to_nvfp4(compressed_fp32)

dsv4/kernels/cuda/__init__.py

@@ -1,2 +1,2 @@
 """CUDA kernel loader — re-exports from loader.py for convenience."""
-from dsv4.kernels.cuda.loader import get_cuda_module, preload_all
+from dsv4.kernels.cuda.loader import get_cuda_module

dsv4/kernels/cuda/compressor_reduce.cu

@@ -124,15 +124,13 @@ __global__ void csa_compress_reduce_kernel(
 
             float g = gate_proj[token_idx * kv_dim + gate_offset + c];
             float kv_val = kv_proj[token_idx * kv_dim + kv_offset + c];
-            // Position bias: same (m, 2*hd) bias added to every block
-            // Added to BOTH gate (softmax logit) and kv (content) per reference
+            // Position bias added ONLY to gate (softmax logit), NOT to KV content.
+            // Paper eq. 11-12: compressed = softmax(Z + B) * C — bias B is on the
+            // compression weights/logits, not on the KV content C.
             if (position_bias != nullptr) {
                 int pos_bias_row = (block_i > 0 && t < m) ? t : (block_i > 0 ? (t - m) : t);
                 if (pos_bias_row >= 0 && pos_bias_row < m) {
-                    float pb = position_bias[pos_bias_row * kv_dim + gate_offset + c];
-                    g += pb;
-                    // kv_offset matches gate_offset for CSA: both are 0 (a-stream) or hd (b-stream)
-                    kv_val += position_bias[pos_bias_row * kv_dim + kv_offset + c];
+                    g += position_bias[pos_bias_row * kv_dim + gate_offset + c];
                 }
             }
             float e = expf(g - local_max[ci]);
@@ -192,12 +190,11 @@ __global__ void hca_compress_reduce_kernel(
             if (token_idx >= T) break;
             float g = gate_proj[token_idx * hd + c];
             float kv_val = kv_proj[token_idx * hd + c];
-            // Position bias: same (m, hd) bias added to every block
-            // Added to BOTH gate (softmax logit) and kv (content) per reference
+            // Position bias added ONLY to gate (softmax logit), NOT to KV content.
+            // Paper eq. 9-10: compressed = softmax(Z + B) * C — bias B is on the
+            // compression weights/logits, not on the KV content C.
             if (position_bias != nullptr && t < m) {
-                float pb = position_bias[t * hd + c];
-                g += pb;
-                kv_val += pb;
+                g += position_bias[t * hd + c];
             }
             float e = expf(g - local_max);
             local_denom += e;

dsv4/kernels/cuda/dequant_nvfp4.cu

@@ -0,0 +1,192 @@
+/**
+ * NVFP4 → BF16 dequantization kernels.
+ *
+ * Converts FP4 (E2M1) data + FP8 (E4M3) block scales + FP32 global scales
+ * back to BF16. Used for the FMHA gather path: compressed KV is stored as
+ * NVFP4, and dequantized on-the-fly when gathering for attention.
+ *
+ * Two variants:
+ *   1. Full dequant: entire FP4 buffer → BF16 (for HCA dense gather)
+ *   2. Selective dequant: only selected rows → BF16 (for CSA top-k gather)
+ *
+ * Grid layout: (N/16, M) — one CTA per (row, 16-element block).
+ * Block size: 16 threads (1 thread per element in the 16-wide block).
+ *
+ * Memory savings: FP4 is 4× smaller than BF16. At hd=512:
+ *   BF16: 512 × 2 = 1024 bytes per entry
+ *   NVFP4: 256 + 64 + 4 = 324 bytes per entry (fp4 + sf + gsa)
+ *   Savings: ~3.2×
+ */
+
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <ATen/ATen.h>
+#include <c10/cuda/CUDAStream.h>
+#include <torch/extension.h>
+#include <cstdint>
+
+// E2M1 magnitudes: index 0-7 → 0, 0.5, 1, 1.5, 2, 3, 4, 6
+__device__ __constant__ float E2M1_LUT[8] = {0.0f, 0.5f, 1.0f, 1.5f, 2.0f, 3.0f, 4.0f, 6.0f};
+
+// ===========================================================================
+// Full dequant: entire buffer → BF16
+// ===========================================================================
+
+__global__ void dequant_nvfp4_kernel(
+    const uint8_t* __restrict__ fp4_data,     // (M, N/2) packed E2M1
+    const uint8_t* __restrict__ sf_data,      // (M, N/16) E4M3 block scales (stored as uint8)
+    const float* __restrict__ gsa_data,       // (M,) FP32 global scale per row
+    __nv_bfloat16* __restrict__ output,       // (M, N) BF16 output
+    int M, int N
+) {
+    int m = blockIdx.y;
+    int n_block = blockIdx.x;
+    if (m >= M || n_block * 16 >= N) return;
+
+    float gsa = gsa_data[m];
+
+    // Read FP8 E4M3 block scale
+    uint8_t sf_byte = sf_data[m * (N / 16) + n_block];
+    __nv_fp8_e4m3 sf_val;
+    memcpy(&sf_val, &sf_byte, 1);
+    float bsf = (float)sf_val;
+
+    // Read 8 packed bytes = 16 E2M1 values
+    for (int i = 0; i < 8; i++) {
+        uint8_t packed = fp4_data[m * (N / 2) + n_block * 8 + i];
+        uint8_t lo_nibble = packed & 0x0F;
+        uint8_t hi_nibble = (packed >> 4) & 0x0F;
+
+        // Low nibble
+        int lo_idx = lo_nibble & 0x07;
+        float lo_sign = (lo_nibble & 0x08) ? -1.0f : 1.0f;
+        float lo_val = lo_sign * E2M1_LUT[lo_idx] * bsf * gsa;
+        int lo_col = n_block * 16 + 2 * i;
+        if (lo_col < N) {
+            output[m * N + lo_col] = __float2bfloat16(lo_val);
+        }
+
+        // High nibble
+        int hi_idx = hi_nibble & 0x07;
+        float hi_sign = (hi_nibble & 0x08) ? -1.0f : 1.0f;
+        float hi_val = hi_sign * E2M1_LUT[hi_idx] * bsf * gsa;
+        int hi_col = n_block * 16 + 2 * i + 1;
+        if (hi_col < N) {
+            output[m * N + hi_col] = __float2bfloat16(hi_val);
+        }
+    }
+}
+
+// ===========================================================================
+// Selective dequant: only dequant selected rows from a larger FP4 buffer
+// This is the CSA gather path — dequant only the top-k entries needed by FMHA
+// ===========================================================================
+
+__global__ void dequant_nvfp4_selective_kernel(
+    const uint8_t* __restrict__ fp4_data,     // (max_comp, N/2) packed E2M1
+    const uint8_t* __restrict__ sf_data,      // (max_comp, N/16) E4M3 block scales
+    const float* __restrict__ gsa_data,       // (max_comp,) FP32 global scale per row
+    const int32_t* __restrict__ indices,      // (K,) int32 — which rows to dequant
+    __nv_bfloat16* __restrict__ output,       // (K, N) BF16 output
+    int K, int N
+) {
+    int k = blockIdx.y;       // which selected entry
+    int n_block = blockIdx.x; // which 16-element block
+    if (k >= K || n_block * 16 >= N) return;
+
+    int src_row = indices[k];
+    float gsa = gsa_data[src_row];
+
+    int N_half = N / 2;
+    int N_sf = N / 16;
+
+    // Read FP8 E4M3 block scale for this row and block
+    uint8_t sf_byte = sf_data[src_row * N_sf + n_block];
+    __nv_fp8_e4m3 sf_val;
+    memcpy(&sf_val, &sf_byte, 1);
+    float bsf = (float)sf_val;
+
+    for (int i = 0; i < 8; i++) {
+        uint8_t packed = fp4_data[src_row * N_half + n_block * 8 + i];
+        uint8_t lo_nibble = packed & 0x0F;
+        uint8_t hi_nibble = (packed >> 4) & 0x0F;
+
+        int lo_idx = lo_nibble & 0x07;
+        float lo_sign = (lo_nibble & 0x08) ? -1.0f : 1.0f;
+        float lo_val = lo_sign * E2M1_LUT[lo_idx] * bsf * gsa;
+        int lo_col = n_block * 16 + 2 * i;
+        if (lo_col < N) {
+            output[k * N + lo_col] = __float2bfloat16(lo_val);
+        }
+
+        int hi_idx = hi_nibble & 0x07;
+        float hi_sign = (hi_nibble & 0x08) ? -1.0f : 1.0f;
+        float hi_val = hi_sign * E2M1_LUT[hi_idx] * bsf * gsa;
+        int hi_col = n_block * 16 + 2 * i + 1;
+        if (hi_col < N) {
+            output[k * N + hi_col] = __float2bfloat16(hi_val);
+        }
+    }
+}
+
+// ===========================================================================
+// PyTorch bindings
+// ===========================================================================
+
+torch::Tensor dequant_nvfp4_cuda(
+    torch::Tensor fp4_data,    // (M, N/2) uint8 packed E2M1
+    torch::Tensor sf_data,     // (M, N/16) uint8 (viewed as E4M3)
+    torch::Tensor gsa_data     // (M,) float32 global scale
+) {
+    int M = fp4_data.size(0);
+    int N = fp4_data.size(1) * 2;  // N/2 packed → N actual
+    TORCH_CHECK(sf_data.size(0) == M, "sf_data row count must match fp4_data");
+    TORCH_CHECK(gsa_data.size(0) == M, "gsa_data row count must match fp4_data");
+
+    auto output = torch::zeros({M, N}, fp4_data.options().dtype(torch::kBFloat16));
+    int nb = N / 16;
+    dim3 grid(nb, M);
+    dim3 block(16);
+
+    dequant_nvfp4_kernel<<<grid, block, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        fp4_data.data_ptr<uint8_t>(),
+        sf_data.data_ptr<uint8_t>(),
+        gsa_data.data_ptr<float>(),
+        reinterpret_cast<__nv_bfloat16*>(output.data_ptr<at::BFloat16>()),
+        M, N
+    );
+    return output;
+}
+
+torch::Tensor dequant_nvfp4_selective_cuda(
+    torch::Tensor fp4_data,    // (max_comp, N/2) uint8 packed E2M1
+    torch::Tensor sf_data,     // (max_comp, N/16) uint8 (viewed as E4M3)
+    torch::Tensor gsa_data,    // (max_comp,) float32 global scale
+    torch::Tensor indices      // (K,) int32
+) {
+    int K = indices.size(0);
+    int N = fp4_data.size(1) * 2;  // N/2 packed → N actual
+    TORCH_CHECK(indices.scalar_type() == torch::kInt32, "indices must be int32");
+
+    auto output = torch::zeros({K, N}, fp4_data.options().dtype(torch::kBFloat16));
+    int nb = N / 16;
+    dim3 grid(nb, K);
+    dim3 block(16);
+
+    dequant_nvfp4_selective_kernel<<<grid, block, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        fp4_data.data_ptr<uint8_t>(),
+        sf_data.data_ptr<uint8_t>(),
+        gsa_data.data_ptr<float>(),
+        indices.data_ptr<int32_t>(),
+        reinterpret_cast<__nv_bfloat16*>(output.data_ptr<at::BFloat16>()),
+        K, N
+    );
+    return output;
+}
+
+PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
+    m.def("dequant_nvfp4", &dequant_nvfp4_cuda, "NVFP4 → BF16 dequant");
+    m.def("dequant_nvfp4_selective", &dequant_nvfp4_selective_cuda, "Selective NVFP4 → BF16 dequant for CSA gather");
+}

dsv4/kernels/cuda/fp8_attention_io.cu

@@ -0,0 +1,254 @@
+/**
+ * DSV4 B1 — FP8 attention input/output preparation kernels.
+ *
+ * These are deliberately tiny launch-count reducers for the mixed-precision
+ * FMHA path:
+ *   - quantize Q noPE dims BF16 -> FP8_E4M3 with a per-(batch,head,row) scale
+ *   - keep Q RoPE dims BF16
+ *   - gather compressed KV noPE bytes/scales and RoPE BF16 without global dequant
+ *   - quantize the SWA noPE tail BF16 -> FP8_E4M3 in the same gather kernel
+ *
+ * No PyTorch fallback and no FP8->BF16 global staging for noPE KV.
+ */
+
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <ATen/ATen.h>
+#include <c10/cuda/CUDAStream.h>
+#include <torch/extension.h>
+#include <cstdint>
+#include <cfloat>
+
+static constexpr float E4M3_MAX = 448.0f;
+
+__device__ __forceinline__ float bf16_load(const __nv_bfloat16* p) {
+    return __bfloat162float(*p);
+}
+
+__device__ __forceinline__ uint8_t fp8_e4m3_from_f32(float x) {
+    x = fminf(fmaxf(x, -E4M3_MAX), E4M3_MAX);
+    __nv_fp8_e4m3 v(x);
+    return *reinterpret_cast<uint8_t*>(&v);
+}
+
+__global__ void quantize_q_fp8_split_kernel(
+    const __nv_bfloat16* __restrict__ q,   // (B,H,T,HD)
+    uint8_t* __restrict__ q_nope_fp8,      // (B,H,T,NOPE)
+    float* __restrict__ q_nope_scale,      // (B,H,T)
+    __nv_bfloat16* __restrict__ q_rope,    // (B,H,T,ROPE)
+    int rows, int hd, int nope, int rope
+) {
+    int row = blockIdx.x;
+    if (row >= rows) return;
+
+    const __nv_bfloat16* q_row = q + (int64_t)row * hd;
+    uint8_t* out8 = q_nope_fp8 + (int64_t)row * nope;
+    __nv_bfloat16* outrope = q_rope + (int64_t)row * rope;
+
+    float local_max = 0.0f;
+    for (int c = threadIdx.x; c < nope; c += blockDim.x) {
+        local_max = fmaxf(local_max, fabsf(bf16_load(q_row + c)));
+    }
+
+    // block reduction over 256 threads
+    for (int off = 16; off > 0; off >>= 1)
+        local_max = fmaxf(local_max, __shfl_down_sync(0xffffffff, local_max, off));
+    __shared__ float warp_max[8];
+    if ((threadIdx.x & 31) == 0) warp_max[threadIdx.x >> 5] = local_max;
+    __syncthreads();
+    float amax = 0.0f;
+    if (threadIdx.x < 32) {
+        amax = (threadIdx.x < (blockDim.x + 31) / 32) ? warp_max[threadIdx.x] : 0.0f;
+        for (int off = 16; off > 0; off >>= 1)
+            amax = fmaxf(amax, __shfl_down_sync(0xffffffff, amax, off));
+        if (threadIdx.x == 0) {
+            float scale = amax / E4M3_MAX;
+            if (scale < 1e-8f) scale = 1e-8f;
+            q_nope_scale[row] = scale;
+        }
+    }
+    __syncthreads();
+
+    float scale = q_nope_scale[row];
+    float inv_scale = 1.0f / scale;
+    for (int c = threadIdx.x; c < nope; c += blockDim.x) {
+        out8[c] = fp8_e4m3_from_f32(bf16_load(q_row + c) * inv_scale);
+    }
+    for (int c = threadIdx.x; c < rope; c += blockDim.x) {
+        outrope[c] = q_row[nope + c];
+    }
+}
+
+__global__ void copy_comp_rows_kernel(
+    const uint8_t* __restrict__ comp_nope_fp8,
+    const float* __restrict__ comp_nope_scale,
+    const __nv_bfloat16* __restrict__ comp_rope,
+    const int32_t* __restrict__ indices,  // optional; nullptr => row i
+    uint8_t* __restrict__ out_nope_fp8,
+    float* __restrict__ out_nope_scale,
+    __nv_bfloat16* __restrict__ out_rope,
+    int K, int nope, int rope
+) {
+    int row = blockIdx.y;
+    int col = blockIdx.x * blockDim.x + threadIdx.x;
+    if (row >= K) return;
+    int src = indices ? indices[row] : row;
+    if (col < nope) out_nope_fp8[(int64_t)row * nope + col] = comp_nope_fp8[(int64_t)src * nope + col];
+    if (col < rope) out_rope[(int64_t)row * rope + col] = comp_rope[(int64_t)src * rope + col];
+    if (blockIdx.x == 0 && threadIdx.x == 0) out_nope_scale[row] = comp_nope_scale[src];
+}
+
+__global__ void quantize_swa_tail_kernel(
+    const __nv_bfloat16* __restrict__ swa, // (S, HD), BF16
+    uint8_t* __restrict__ out_nope_fp8,    // (K+S, NOPE)
+    float* __restrict__ out_nope_scale,    // (K+S)
+    __nv_bfloat16* __restrict__ out_rope,  // (K+S, ROPE)
+    int K, int S, int hd, int nope, int rope
+) {
+    int s = blockIdx.x;
+    if (s >= S) return;
+    int out_row = K + s;
+    const __nv_bfloat16* src = swa + (int64_t)s * hd;
+    uint8_t* out8 = out_nope_fp8 + (int64_t)out_row * nope;
+    __nv_bfloat16* outrope = out_rope + (int64_t)out_row * rope;
+
+    float local_max = 0.0f;
+    for (int c = threadIdx.x; c < nope; c += blockDim.x) {
+        local_max = fmaxf(local_max, fabsf(bf16_load(src + c)));
+    }
+    for (int off = 16; off > 0; off >>= 1)
+        local_max = fmaxf(local_max, __shfl_down_sync(0xffffffff, local_max, off));
+    __shared__ float warp_max[8];
+    if ((threadIdx.x & 31) == 0) warp_max[threadIdx.x >> 5] = local_max;
+    __syncthreads();
+    float amax = 0.0f;
+    if (threadIdx.x < 32) {
+        amax = (threadIdx.x < (blockDim.x + 31) / 32) ? warp_max[threadIdx.x] : 0.0f;
+        for (int off = 16; off > 0; off >>= 1)
+            amax = fmaxf(amax, __shfl_down_sync(0xffffffff, amax, off));
+        if (threadIdx.x == 0) {
+            float scale = amax / E4M3_MAX;
+            if (scale < 1e-8f) scale = 1e-8f;
+            out_nope_scale[out_row] = scale;
+        }
+    }
+    __syncthreads();
+
+    float inv_scale = 1.0f / out_nope_scale[out_row];
+    for (int c = threadIdx.x; c < nope; c += blockDim.x) {
+        out8[c] = fp8_e4m3_from_f32(bf16_load(src + c) * inv_scale);
+    }
+    for (int c = threadIdx.x; c < rope; c += blockDim.x) {
+        outrope[c] = src[nope + c];
+    }
+}
+
+std::tuple<torch::Tensor, torch::Tensor, torch::Tensor> quantize_q_fp8_split_cuda(
+    torch::Tensor q, int64_t rope_dim
+) {
+    TORCH_CHECK(q.is_cuda(), "q must be CUDA");
+    TORCH_CHECK(q.scalar_type() == torch::kBFloat16, "q must be BF16");
+    TORCH_CHECK(q.dim() == 4, "q must be (B,H,T,HD)");
+    q = q.contiguous();
+    int B = q.size(0), H = q.size(1), T = q.size(2), HD = q.size(3);
+    int rope = (int)rope_dim;
+    int nope = HD - rope;
+    TORCH_CHECK(nope > 0 && rope > 0, "invalid rope_dim");
+    auto q8 = torch::empty({B, H, T, nope}, q.options().dtype(torch::kUInt8));
+    auto qs = torch::empty({B, H, T}, q.options().dtype(torch::kFloat32));
+    auto qr = torch::empty({B, H, T, rope}, q.options().dtype(torch::kBFloat16));
+    int rows = B * H * T;
+    quantize_q_fp8_split_kernel<<<rows, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        reinterpret_cast<const __nv_bfloat16*>(q.data_ptr<at::BFloat16>()),
+        q8.data_ptr<uint8_t>(), qs.data_ptr<float>(),
+        reinterpret_cast<__nv_bfloat16*>(qr.data_ptr<at::BFloat16>()),
+        rows, HD, nope, rope);
+    return {q8.view(torch::kFloat8_e4m3fn), qs, qr};
+}
+
+void gather_mixed_selective_cuda(
+    torch::Tensor comp_nope_fp8, torch::Tensor comp_nope_scale, torch::Tensor comp_rope,
+    torch::Tensor swa, torch::Tensor indices,
+    torch::Tensor out_nope_fp8, torch::Tensor out_nope_scale, torch::Tensor out_rope
+) {
+    TORCH_CHECK(indices.scalar_type() == torch::kInt32, "indices must be int32");
+    int K = indices.size(0);
+    int S = swa.size(0);
+    int nope = comp_nope_fp8.size(1);
+    int rope = comp_rope.size(1);
+    int hd = nope + rope;
+    if (K > 0) {
+        dim3 grid(((nope > rope ? nope : rope) + 255) / 256, K);
+        copy_comp_rows_kernel<<<grid, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+            comp_nope_fp8.data_ptr<uint8_t>(), comp_nope_scale.data_ptr<float>(),
+            reinterpret_cast<const __nv_bfloat16*>(comp_rope.data_ptr<at::BFloat16>()),
+            indices.data_ptr<int32_t>(),
+            out_nope_fp8.data_ptr<uint8_t>(), out_nope_scale.data_ptr<float>(),
+            reinterpret_cast<__nv_bfloat16*>(out_rope.data_ptr<at::BFloat16>()),
+            K, nope, rope);
+    }
+    if (S > 0) {
+        quantize_swa_tail_kernel<<<S, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+            reinterpret_cast<const __nv_bfloat16*>(swa.data_ptr<at::BFloat16>()),
+            out_nope_fp8.data_ptr<uint8_t>(), out_nope_scale.data_ptr<float>(),
+            reinterpret_cast<__nv_bfloat16*>(out_rope.data_ptr<at::BFloat16>()),
+            K, S, hd, nope, rope);
+    }
+}
+
+void gather_mixed_all_cuda(
+    torch::Tensor comp_nope_fp8, torch::Tensor comp_nope_scale, torch::Tensor comp_rope,
+    torch::Tensor swa, torch::Tensor out_nope_fp8, torch::Tensor out_nope_scale, torch::Tensor out_rope
+) {
+    int K = comp_nope_fp8.size(0);
+    int S = swa.size(0);
+    int nope = comp_nope_fp8.size(1);
+    int rope = comp_rope.size(1);
+    int hd = nope + rope;
+    if (K > 0) {
+        dim3 grid(((nope > rope ? nope : rope) + 255) / 256, K);
+        copy_comp_rows_kernel<<<grid, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+            comp_nope_fp8.data_ptr<uint8_t>(), comp_nope_scale.data_ptr<float>(),
+            reinterpret_cast<const __nv_bfloat16*>(comp_rope.data_ptr<at::BFloat16>()),
+            nullptr,
+            out_nope_fp8.data_ptr<uint8_t>(), out_nope_scale.data_ptr<float>(),
+            reinterpret_cast<__nv_bfloat16*>(out_rope.data_ptr<at::BFloat16>()),
+            K, nope, rope);
+    }
+    if (S > 0) {
+        quantize_swa_tail_kernel<<<S, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+            reinterpret_cast<const __nv_bfloat16*>(swa.data_ptr<at::BFloat16>()),
+            out_nope_fp8.data_ptr<uint8_t>(), out_nope_scale.data_ptr<float>(),
+            reinterpret_cast<__nv_bfloat16*>(out_rope.data_ptr<at::BFloat16>()),
+            K, S, hd, nope, rope);
+    }
+}
+
+void gather_mixed_swa_only_cuda(torch::Tensor swa, torch::Tensor out_nope_fp8,
+                                torch::Tensor out_nope_scale, torch::Tensor out_rope,
+                                int64_t rope_dim) {
+    int S = swa.size(0);
+    int hd = swa.size(1);
+    int rope = (int)rope_dim;
+    int nope = hd - rope;
+    if (S > 0) {
+        quantize_swa_tail_kernel<<<S, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+            reinterpret_cast<const __nv_bfloat16*>(swa.data_ptr<at::BFloat16>()),
+            out_nope_fp8.data_ptr<uint8_t>(), out_nope_scale.data_ptr<float>(),
+            reinterpret_cast<__nv_bfloat16*>(out_rope.data_ptr<at::BFloat16>()),
+            0, S, hd, nope, rope);
+    }
+}
+
+PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
+    m.def("quantize_q_fp8_split", &quantize_q_fp8_split_cuda,
+          "Split Q into FP8_E4M3 noPE + BF16 RoPE");
+    m.def("gather_mixed_selective_", &gather_mixed_selective_cuda,
+          "In-place mixed KV gather for selected compressed rows + SWA tail");
+    m.def("gather_mixed_all_", &gather_mixed_all_cuda,
+          "In-place mixed KV gather for all compressed rows + SWA tail");
+    m.def("gather_mixed_swa_only_", &gather_mixed_swa_only_cuda,
+          "In-place mixed KV gather for SWA-only attention");
+}

dsv4/kernels/cuda/fused_mhc_rmsnorm_quantize.cu

@@ -0,0 +1,302 @@
+/**
+ * fused_mhc_rmsnorm_quantize.cu
+ *
+ * Fused mHC pre_block + RMSNorm + NVFP4 quantize.
+ * Replaces: bmm (1 launch) + rmsnorm (4+ launches) + quantize (2 launches)
+ * with just 2 kernel launches.
+ *
+ * For decode (T=1): x_in = sum_j A[j] * X[j, :] — weighted sum of n_hc streams
+ * Then: RMSNorm(x_in, weight) → quantize to NVFP4
+ *
+ * Two-kernel approach (same pattern as fused_rmsnorm_quantize.cu):
+ *   Kernel 1: mhc_rmsnorm_amax_gsa — compute x_in via bmm, then RMS + amax → gsa
+ *   Kernel 2: mhc_rmsnorm_quantize_nvfp4 — normalize + quantize using GPU-computed gsa
+ *
+ * Usage: 2 sites per layer (attn + ffn) × 61 layers = 122 calls/step
+ * Each site saves ~5 launches → ~610 launches/token eliminated
+ */
+
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cuda_bf16.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <ATen/ATen.h>
+#include <c10/cuda/CUDAStream.h>
+#include <torch/extension.h>
+#include <cstdint>
+#include <cfloat>
+#include <cmath>
+#include <cstring>
+
+// E2M1 half-step → index (same as quantize_nvfp4.cu)
+__device__ __forceinline__ int half_step_to_e2m1(int hs) {
+    if (hs <= 4) return hs;
+    if (hs <= 5) return 4;
+    if (hs <= 7) return 5;
+    if (hs <= 10) return 6;
+    return 7;
+}
+
+// ============================================================================
+// Kernel 1: mHC bmm + RMS + amax → gsa + inv_rms
+// ============================================================================
+// Input: X_l (M, n_hc, N) BF16, A_l (M, n_hc) BF16, norm_weight (N,) FP32
+// For T=1 decode: M=1, n_hc=4, N=7168
+//
+// Each block handles one row (one token).
+// The bmm: x_in = sum_j A[j] * X[j, :] is a weighted sum of n_hc streams.
+// For n_hc=4: x_in = A[0]*X[0,:] + A[1]*X[1,:] + A[2]*X[2,:] + A[3]*X[3,:]
+
+__global__ void mhc_rmsnorm_amax_gsa_kernel(
+    const __nv_bfloat16* __restrict__ X_l,    // (M, n_hc, N) BF16
+    const __nv_bfloat16* __restrict__ A_l,    // (M, n_hc) BF16
+    const float* __restrict__ norm_weight,     // (N,) FP32
+    float* __restrict__ gsa_out,               // (M,) FP32
+    float* __restrict__ inv_rms_out,           // (M,) FP32
+    const int M,
+    const int n_hc,
+    const int N,
+    const float eps,
+    const float divisor
+) {
+    const int row = blockIdx.x;
+    if (row >= M) return;
+
+    const __nv_bfloat16* X_row = X_l + (size_t)row * n_hc * N;
+    const __nv_bfloat16* A_row = A_l + (size_t)row * n_hc;
+
+    // Load A coefficients (n_hc=4 typically, always small)
+    float a_coeff[4];  // n_hc max = 4
+    for (int j = 0; j < n_hc && j < 4; j++) {
+        a_coeff[j] = __bfloat162float(A_row[j]);
+    }
+
+    // Sub-pass 1: compute x_in = sum_j A[j] * X[j, :] and sum(x_in^2)
+    float sum_sq = 0.0f;
+    for (int col = threadIdx.x; col < N; col += blockDim.x) {
+        float x_in_val = 0.0f;
+        for (int j = 0; j < n_hc && j < 4; j++) {
+            x_in_val += a_coeff[j] * __bfloat162float(X_row[(size_t)j * N + col]);
+        }
+        sum_sq += x_in_val * x_in_val;
+    }
+
+    // Warp-level reduction
+    for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+        sum_sq += __shfl_down_sync(0xFFFFFFFF, sum_sq, offset);
+    }
+
+    const int num_warps = blockDim.x / warpSize;
+    __shared__ float s_sum_sq[32];
+    int lane = threadIdx.x % warpSize;
+    int warp_id = threadIdx.x / warpSize;
+
+    if (lane == 0) s_sum_sq[warp_id] = sum_sq;
+    __syncthreads();
+
+    float row_sum_sq = 0.0f;
+    if (warp_id == 0) {
+        row_sum_sq = (lane < num_warps) ? s_sum_sq[lane] : 0.0f;
+        for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+            row_sum_sq += __shfl_down_sync(0xFFFFFFFF, row_sum_sq, offset);
+        }
+    }
+
+    __shared__ float s_inv_rms;
+    if (threadIdx.x == 0) {
+        float rms = sqrtf(row_sum_sq / N + eps);
+        s_inv_rms = 1.0f / fmaxf(rms, 1e-8f);
+    }
+    __syncthreads();
+    float inv_rms = s_inv_rms;
+
+    // Sub-pass 2: amax of (x_in * inv_rms * weight)
+    float row_amax = 0.0f;
+    for (int col = threadIdx.x; col < N; col += blockDim.x) {
+        float x_in_val = 0.0f;
+        for (int j = 0; j < n_hc && j < 4; j++) {
+            x_in_val += a_coeff[j] * __bfloat162float(X_row[(size_t)j * N + col]);
+        }
+        float normalized = x_in_val * inv_rms * norm_weight[col];
+        float abs_val = fabsf(normalized);
+        if (abs_val > row_amax) row_amax = abs_val;
+    }
+
+    // Warp-level reduce max
+    for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+        row_amax = fmaxf(row_amax, __shfl_down_sync(0xFFFFFFFF, row_amax, offset));
+    }
+
+    __shared__ float s_amax[32];
+    if (lane == 0) s_amax[warp_id] = row_amax;
+    __syncthreads();
+
+    if (warp_id == 0) {
+        float global_amax = 0.0f;
+        if (lane < num_warps) global_amax = s_amax[lane];
+        for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+            global_amax = fmaxf(global_amax, __shfl_down_sync(0xFFFFFFFF, global_amax, offset));
+        }
+        if (lane == 0) {
+            gsa_out[row] = fmaxf(global_amax, 1e-8f) / divisor;
+            inv_rms_out[row] = inv_rms;
+        }
+    }
+}
+
+// ============================================================================
+// Kernel 2: mHC bmm + normalize + quantize using GPU-computed gsa
+// ============================================================================
+
+__global__ void mhc_rmsnorm_quantize_nvfp4_kernel(
+    const __nv_bfloat16* __restrict__ X_l,    // (M, n_hc, N) BF16
+    const __nv_bfloat16* __restrict__ A_l,    // (M, n_hc) BF16
+    const float* __restrict__ norm_weight,     // (N,) FP32
+    const float* __restrict__ gsa,             // (M,) FP32
+    const float* __restrict__ inv_rms,         // (M,) FP32
+    uint8_t* __restrict__ out_fp4,             // (M, N//2) FP4 packed
+    uint8_t* __restrict__ out_sf,              // (M, N//16) E4M3 block scales
+    const int M,
+    const int n_hc,
+    const int N
+) {
+    const int row = blockIdx.y;
+    const int n_block = blockIdx.x;
+    if (row >= M) return;
+    if (n_block * 16 >= N) return;
+
+    const __nv_bfloat16* X_row = X_l + (size_t)row * n_hc * N;
+    const __nv_bfloat16* A_row = A_l + (size_t)row * n_hc;
+    float row_gsa = gsa[row];
+    float row_inv_rms = inv_rms[row];
+
+    // Load A coefficients
+    float a_coeff[4];
+    for (int j = 0; j < n_hc && j < 4; j++) {
+        a_coeff[j] = __bfloat162float(A_row[j]);
+    }
+
+    // Step 1: Compute x_in for 16 elements, normalize, compute block amax
+    float vals[16];
+    float block_amax = 0.0f;
+    const int col_base = n_block * 16;
+
+    for (int i = 0; i < 16; i++) {
+        int col = col_base + i;
+        if (col < N) {
+            float x_in_val = 0.0f;
+            for (int j = 0; j < n_hc && j < 4; j++) {
+                x_in_val += a_coeff[j] * __bfloat162float(X_row[(size_t)j * N + col]);
+            }
+            float normalized = x_in_val * row_inv_rms * norm_weight[col];  // RMSNorm
+            vals[i] = normalized;
+            float av = fabsf(normalized);
+            if (av > block_amax) block_amax = av;
+        } else {
+            vals[i] = 0.0f;
+        }
+    }
+
+    // Step 2: Compute FP8 E4M3 block scale (same as quantize_nvfp4.cu)
+    float bsf = block_amax / (row_gsa * 6.0f);
+    if (block_amax < row_gsa * 6.0f * 0.001953125f) {
+        bsf = 0.0f;
+        for (int i = 0; i < 16; i++) vals[i] = 0.0f;
+    }
+    __nv_fp8_e4m3 bsf8_obj(bsf);
+    float bs = (float)bsf8_obj;
+    uint8_t bsf8;
+    memcpy(&bsf8, &bsf8_obj, 1);
+
+    // Step 3: Quantize to FP4 E2M1 (same as quantize_nvfp4.cu)
+    uint8_t nibbles[16];
+    for (int i = 0; i < 16; i++) {
+        if (bs < 1e-8f) { nibbles[i] = 0; continue; }
+        float s = vals[i] / (row_gsa * bs);
+        int hs = __float2int_rn(fminf(fabsf(s), 6.0f) * 2.0f);
+        if (hs > 12) hs = 12;
+        int idx = half_step_to_e2m1(hs);
+        if (s < 0) idx += 8;
+        nibbles[i] = idx;
+    }
+
+    // Step 4: Pack pairs (same as quantize_nvfp4.cu)
+    for (int i = 0; i < 8; i++) {
+        out_fp4[(size_t)row * (N / 2) + n_block * 8 + i] =
+            (nibbles[2 * i + 1] << 4) | nibbles[2 * i];
+    }
+
+    // Step 5: Write FP8 block scale
+    out_sf[(size_t)row * (N / 16) + n_block] = bsf8;
+}
+
+// ============================================================================
+// PyTorch bridge
+// ============================================================================
+
+std::tuple<torch::Tensor, torch::Tensor, torch::Tensor, torch::Tensor>
+mhc_rmsnorm_quantize_nvfp4_cuda(
+    torch::Tensor X_l,               // (M, n_hc, N) BF16
+    torch::Tensor A_l,               // (M, n_hc) BF16
+    torch::Tensor norm_weight,       // (N,) FP32
+    double eps,
+    double divisor
+) {
+    TORCH_CHECK(X_l.is_contiguous(), "X_l must be contiguous");
+    TORCH_CHECK(X_l.scalar_type() == torch::kBFloat16, "X_l must be BF16");
+    TORCH_CHECK(A_l.scalar_type() == torch::kBFloat16, "A_l must be BF16");
+    TORCH_CHECK(norm_weight.scalar_type() == torch::kFloat32, "norm_weight must be FP32");
+
+    const int M = X_l.size(0);
+    const int n_hc = X_l.size(1);
+    const int N = X_l.size(2);
+    TORCH_CHECK(N % 16 == 0, "N must be multiple of 16");
+    TORCH_CHECK(n_hc <= 4, "n_hc must be <= 4");
+
+    auto stream = c10::cuda::getCurrentCUDAStream();
+    auto options = X_l.options();
+
+    auto gsa = torch::empty({M}, options.dtype(torch::kFloat32));
+    auto inv_rms = torch::empty({M}, options.dtype(torch::kFloat32));
+    auto x_fp4 = torch::empty({M, N / 2}, options.dtype(torch::kUInt8));
+    auto x_sf = torch::empty({M, N / 16}, options.dtype(torch::kUInt8));
+
+    // Kernel 1: mHC bmm + RMS + amax → gsa (1 block per row)
+    const int threads1 = 256;
+    mhc_rmsnorm_amax_gsa_kernel<<<M, threads1, 0, stream>>>(
+        reinterpret_cast<const __nv_bfloat16*>(X_l.data_ptr<at::BFloat16>()),
+        reinterpret_cast<const __nv_bfloat16*>(A_l.data_ptr<at::BFloat16>()),
+        norm_weight.data_ptr<float>(),
+        gsa.data_ptr<float>(),
+        inv_rms.data_ptr<float>(),
+        M, n_hc, N, (float)eps, (float)divisor
+    );
+
+    // Kernel 2: bmm + normalize + quantize
+    const int n_blocks = N / 16;
+    dim3 grid2(n_blocks, M);
+    const int threads2 = 16;
+    mhc_rmsnorm_quantize_nvfp4_kernel<<<grid2, threads2, 0, stream>>>(
+        reinterpret_cast<const __nv_bfloat16*>(X_l.data_ptr<at::BFloat16>()),
+        reinterpret_cast<const __nv_bfloat16*>(A_l.data_ptr<at::BFloat16>()),
+        norm_weight.data_ptr<float>(),
+        gsa.data_ptr<float>(),
+        inv_rms.data_ptr<float>(),
+        x_fp4.data_ptr<uint8_t>(),
+        x_sf.data_ptr<uint8_t>(),
+        M, n_hc, N
+    );
+
+    return std::make_tuple(
+        x_fp4.view(torch::kFloat4_e2m1fn_x2),
+        x_sf.view(torch::kFloat8_e4m3fn),
+        gsa,
+        inv_rms
+    );
+}
+
+PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
+    m.def("mhc_rmsnorm_quantize_nvfp4", &mhc_rmsnorm_quantize_nvfp4_cuda,
+          "Fused mHC pre_block + RMSNorm + NVFP4 quantize");
+}

dsv4/kernels/cuda/fused_rmsnorm_quantize.cu

@@ -0,0 +1,315 @@
+/**
+ * fused_rmsnorm_quantize.cu
+ *
+ * Fused RMSNorm + amax + NVFP4 quantize.
+ * Replaces: rmsnorm (4+ BF16 launches) + amax (1 launch) + quantize (1 launch)
+ * with just 2 kernel launches.
+ *
+ * Kernel 1: rmsnorm_amax_gsa_kernel
+ *   - Compute RMS of each row: rms = sqrt(mean(x^2) + eps)
+ *   - Compute row-wise amax of (x / rms * weight) — the normalized output
+ *   - Derive gsa = amax / divisor for each row
+ *   - Write gsa (per-row) and inv_rms (per-row) to GPU buffers
+ *
+ * Kernel 2: rmsnorm_quantize_nvfp4_kernel
+ *   - Read gsa + inv_rms from GPU buffers (no CPU sync)
+ *   - Normalize: val = x * inv_rms * weight
+ *   - Quantize to NVFP4 using the same proven path as quantize_nvfp4.cu
+ *   - Write FP4 data + E4M3 block scales
+ *
+ * Quantization is bit-identical to quantize_nvfp4.cu:
+ *   - half_step_to_e2m1 for E2M1 encoding
+ *   - __nv_fp8_e4m3 for block scale
+ *   - (nibbles[2*i+1] << 4) | nibbles[2*i] packing
+ */
+
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cuda_bf16.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <ATen/ATen.h>
+#include <c10/cuda/CUDAStream.h>
+#include <torch/extension.h>
+#include <cstdint>
+#include <cfloat>
+#include <cmath>
+#include <cstring>
+
+// FP4 E2M1 half-step → index mapping (same as quantize_nvfp4.cu)
+__device__ __forceinline__ int half_step_to_e2m1(int hs) {
+    if (hs <= 4) return hs;
+    if (hs <= 5) return 4;
+    if (hs <= 7) return 5;
+    if (hs <= 10) return 6;
+    return 7;
+}
+
+// ============================================================================
+// Kernel 1: Compute RMS + amax of normalized output → gsa per row
+// ============================================================================
+// Each block processes one row of (M, N).
+// Threadblock: blockDim.x threads per row (must be multiple of warpSize).
+
+__global__ void rmsnorm_amax_gsa_kernel(
+    const __nv_bfloat16* __restrict__ x,     // (M, N) BF16 row-major
+    const float* __restrict__ norm_weight,    // (N,) FP32
+    float* __restrict__ gsa_out,              // (M,) FP32 — per-row gsa
+    float* __restrict__ inv_rms_out,          // (M,) FP32 — per-row 1/rms (for kernel 2)
+    const int M,
+    const int N,
+    const float eps,
+    const float divisor                        // gsa = amax / divisor
+) {
+    const int row = blockIdx.x;
+    if (row >= M) return;
+
+    const __nv_bfloat16* x_row = x + (size_t)row * N;
+
+    // Sub-pass 1: compute sum(x^2) for RMS
+    float sum_sq = 0.0f;
+    for (int col = threadIdx.x; col < N; col += blockDim.x) {
+        float val = __bfloat162float(x_row[col]);
+        sum_sq += val * val;
+    }
+
+    // Warp-level reduction
+    for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+        sum_sq += __shfl_down_sync(0xFFFFFFFF, sum_sq, offset);
+    }
+
+    // Block-level reduction via shared memory
+    const int num_warps = blockDim.x / warpSize;
+    __shared__ float s_sum_sq[32];  // max 32 warps
+    int lane = threadIdx.x % warpSize;
+    int warp_id = threadIdx.x / warpSize;
+
+    if (lane == 0) {
+        s_sum_sq[warp_id] = sum_sq;
+    }
+    __syncthreads();
+
+    // First warp reduces across warps
+    float row_sum_sq = 0.0f;
+    if (warp_id == 0) {
+        row_sum_sq = (lane < num_warps) ? s_sum_sq[lane] : 0.0f;
+        for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+            row_sum_sq += __shfl_down_sync(0xFFFFFFFF, row_sum_sq, offset);
+        }
+    }
+
+    // Broadcast inv_rms to all threads
+    __shared__ float s_inv_rms;
+    if (threadIdx.x == 0) {
+        float rms = sqrtf(row_sum_sq / N + eps);
+        s_inv_rms = 1.0f / fmaxf(rms, 1e-8f);
+    }
+    __syncthreads();
+    float inv_rms = s_inv_rms;
+
+    // Sub-pass 2: amax of normalized output (x * inv_rms * weight)
+    float row_amax = 0.0f;
+    for (int col = threadIdx.x; col < N; col += blockDim.x) {
+        float val = __bfloat162float(x_row[col]) * inv_rms * norm_weight[col];
+        float abs_val = fabsf(val);
+        if (abs_val > row_amax) row_amax = abs_val;
+    }
+
+    // Warp-level reduce max
+    for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+        row_amax = fmaxf(row_amax, __shfl_down_sync(0xFFFFFFFF, row_amax, offset));
+    }
+
+    __shared__ float s_amax[32];
+    if (lane == 0) {
+        s_amax[warp_id] = row_amax;
+    }
+    __syncthreads();
+
+    if (warp_id == 0) {
+        float global_amax = 0.0f;
+        if (lane < num_warps) global_amax = s_amax[lane];
+        for (int offset = warpSize / 2; offset > 0; offset /= 2) {
+            global_amax = fmaxf(global_amax, __shfl_down_sync(0xFFFFFFFF, global_amax, offset));
+        }
+        if (lane == 0) {
+            gsa_out[row] = fmaxf(global_amax, 1e-8f) / divisor;
+            inv_rms_out[row] = inv_rms;
+        }
+    }
+}
+
+// ============================================================================
+// Kernel 2: RMSNorm + quantize using gsa from GPU buffer
+// ============================================================================
+// Same grid as quantize_nvfp4_kernel: (N/16, M, 1)
+// Each CTA processes one 16-element microblock in one row.
+// Bit-identical quantization to quantize_nvfp4.cu.
+
+__global__ void rmsnorm_quantize_nvfp4_kernel(
+    const __nv_bfloat16* __restrict__ x,     // (M, N) BF16 row-major
+    const float* __restrict__ norm_weight,    // (N,) FP32
+    const float* __restrict__ gsa,            // (M,) FP32 — per-row global scale
+    const float* __restrict__ inv_rms,        // (M,) FP32 — per-row 1/rms
+    uint8_t* __restrict__ out_fp4,            // (M, N//2) FP4 packed
+    uint8_t* __restrict__ out_sf,             // (M, N//16) E4M3 block scales (uint8 view)
+    const int M,
+    const int N
+) {
+    const int row = blockIdx.y;
+    const int n_block = blockIdx.x;
+    if (row >= M) return;
+    if (n_block * 16 >= N) return;
+
+    const __nv_bfloat16* x_row = x + (size_t)row * N;
+    float row_gsa = gsa[row];
+    float row_inv_rms = inv_rms[row];
+
+    // Step 1: Load 16 BF16 elements, normalize (RMSNorm), compute block amax
+    float vals[16];
+    float block_amax = 0.0f;
+    const int col_base = n_block * 16;
+
+    for (int i = 0; i < 16; i++) {
+        int col = col_base + i;
+        if (col < N) {
+            float v = __bfloat162float(x_row[col]);
+            v = v * row_inv_rms * norm_weight[col];  // RMSNorm
+            vals[i] = v;
+            float av = fabsf(v);
+            if (av > block_amax) block_amax = av;
+        } else {
+            vals[i] = 0.0f;
+        }
+    }
+
+    // Step 2: Compute FP8 E4M3 block scale (same as quantize_nvfp4.cu)
+    // block_scale = block_amax / (gsa * 6.0)
+    float bsf = block_amax / (row_gsa * 6.0f);
+    if (block_amax < row_gsa * 6.0f * 0.001953125f) {
+        bsf = 0.0f;
+        for (int i = 0; i < 16; i++) vals[i] = 0.0f;
+    }
+    __nv_fp8_e4m3 bsf8_obj(bsf);
+    float bs = (float)bsf8_obj;  // dequantized block scale for FP4 computation
+    uint8_t bsf8;
+    memcpy(&bsf8, &bsf8_obj, 1);
+
+    // Step 3: Quantize each value to FP4 E2M1 (same as quantize_nvfp4.cu)
+    uint8_t nibbles[16];
+    for (int i = 0; i < 16; i++) {
+        if (bs < 1e-8f) { nibbles[i] = 0; continue; }
+        float s = vals[i] / (row_gsa * bs);  // scale by gsa * block_scale
+        int hs = __float2int_rn(fminf(fabsf(s), 6.0f) * 2.0f);
+        if (hs > 12) hs = 12;
+        int idx = half_step_to_e2m1(hs);
+        if (s < 0) idx += 8;
+        nibbles[i] = idx;
+    }
+
+    // Step 4: Pack pairs: (nibbles[2*i+1] << 4) | nibbles[2*i] (same as quantize_nvfp4.cu)
+    for (int i = 0; i < 8; i++) {
+        out_fp4[(size_t)row * (N / 2) + n_block * 8 + i] =
+            (nibbles[2 * i + 1] << 4) | nibbles[2 * i];
+    }
+
+    // Step 5: Write FP8 block scale (uint8 view, same as quantize_nvfp4.cu)
+    out_sf[(size_t)row * (N / 16) + n_block] = bsf8;
+}
+
+// ============================================================================
+// PyTorch bridge
+// ============================================================================
+
+std::tuple<torch::Tensor, torch::Tensor, torch::Tensor, torch::Tensor>
+rmsnorm_quantize_nvfp4_cuda(
+    torch::Tensor x,               // (M, N) BF16
+    torch::Tensor norm_weight,     // (N,) FP32
+    double eps,
+    double divisor
+) {
+    TORCH_CHECK(x.is_contiguous(), "x must be contiguous");
+    TORCH_CHECK(x.scalar_type() == torch::kBFloat16, "x must be BF16");
+    TORCH_CHECK(norm_weight.scalar_type() == torch::kFloat32, "norm_weight must be FP32");
+
+    const int M = x.size(0);
+    const int N = x.size(1);
+    TORCH_CHECK(N % 16 == 0, "N must be multiple of 16");
+
+    auto stream = c10::cuda::getCurrentCUDAStream();
+    auto options = x.options();
+
+    // Output buffers (uint8, then .view() to FP4/FP8 dtypes)
+    auto gsa = torch::empty({M}, options.dtype(torch::kFloat32));
+    auto inv_rms = torch::empty({M}, options.dtype(torch::kFloat32));
+    auto x_fp4 = torch::empty({M, N / 2}, options.dtype(torch::kUInt8));
+    auto x_sf = torch::empty({M, N / 16}, options.dtype(torch::kUInt8));
+
+    // Kernel 1: RMSNorm + amax → gsa (1 block per row)
+    const int threads1 = 256;  // 8 warps, handles up to N=8192
+    rmsnorm_amax_gsa_kernel<<<M, threads1, 0, stream>>>(
+        reinterpret_cast<const __nv_bfloat16*>(x.data_ptr<at::BFloat16>()),
+        norm_weight.data_ptr<float>(),
+        gsa.data_ptr<float>(),
+        inv_rms.data_ptr<float>(),
+        M, N, (float)eps, (float)divisor
+    );
+
+    // Kernel 2: Normalize + quantize (1 block per (row, microblock))
+    const int n_blocks = N / 16;
+    dim3 grid2(n_blocks, M);
+    const int threads2 = 16;  // 1 thread per element in the 16-elem microblock
+    rmsnorm_quantize_nvfp4_kernel<<<grid2, threads2, 0, stream>>>(
+        reinterpret_cast<const __nv_bfloat16*>(x.data_ptr<at::BFloat16>()),
+        norm_weight.data_ptr<float>(),
+        gsa.data_ptr<float>(),
+        inv_rms.data_ptr<float>(),
+        x_fp4.data_ptr<uint8_t>(),
+        x_sf.data_ptr<uint8_t>(),
+        M, N
+    );
+
+    // View as proper dtypes (same as quantize_nvfp4.cu)
+    return std::make_tuple(
+        x_fp4.view(torch::kFloat4_e2m1fn_x2),
+        x_sf.view(torch::kFloat8_e4m3fn),
+        gsa,
+        inv_rms
+    );
+}
+
+// Standalone kernel 1 entry point (for testing / when only gsa needed)
+torch::Tensor rmsnorm_amax_gsa_cuda(
+    torch::Tensor x,
+    torch::Tensor norm_weight,
+    double eps,
+    double divisor
+) {
+    TORCH_CHECK(x.is_contiguous(), "x must be contiguous");
+    TORCH_CHECK(x.scalar_type() == torch::kBFloat16, "x must be BF16");
+
+    const int M = x.size(0);
+    const int N = x.size(1);
+    auto stream = c10::cuda::getCurrentCUDAStream();
+
+    auto gsa = torch::empty({M}, x.options().dtype(torch::kFloat32));
+    auto inv_rms = torch::empty({M}, x.options().dtype(torch::kFloat32));
+
+    const int threads = 256;
+    rmsnorm_amax_gsa_kernel<<<M, threads, 0, stream>>>(
+        reinterpret_cast<const __nv_bfloat16*>(x.data_ptr<at::BFloat16>()),
+        norm_weight.data_ptr<float>(),
+        gsa.data_ptr<float>(),
+        inv_rms.data_ptr<float>(),
+        M, N, (float)eps, (float)divisor
+    );
+
+    return gsa;
+}
+
+PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
+    m.def("rmsnorm_quantize_nvfp4", &rmsnorm_quantize_nvfp4_cuda,
+          "Fused RMSNorm + amax + quantize to NVFP4");
+    m.def("rmsnorm_amax_gsa", &rmsnorm_amax_gsa_cuda,
+          "RMSNorm + amax → gsa (kernel 1 only)");
+}

dsv4/kernels/cuda/indexer_fp8_score_topk.cu

@@ -0,0 +1,470 @@
+/**
+ * DSV4 B2 — FP8 tensor-core indexer scoring + weighted ReLU + top-k.
+ *
+ * CSA Lightning Indexer (paper §2.3.1, eq. 16):
+ *   I[t,s] = Σ_h w_h[t,h] · ReLU(q_I[t,h] · K^IComp[s])
+ *
+ * Decode-specialized Blackwell FP8 tensor-core path (T=1):
+ *   1. Quantize Q (n_ih=64, ihd=128) BF16 → FP8_E4M3 with per-row FP32 scale.
+ *   2. Run Q (128x128 padded) × K^T (128x128 tile) with tcgen05.mma.kind::f8f6f4.
+ *   3. Read accumulator rows from TMEM with tcgen05.ld.32x32b.x8.
+ *   4. Dequant logits in registers, apply ReLU, weighted sum across indexer heads.
+ *   5. Block-local top-k selection.
+ *
+ * Important TMEM rule for M=128, cta_group::1:
+ *   tcgen05.ld.32x32b.x8 does NOT use a row offset in the address.  The warp id in
+ *   the first warpgroup selects the row/lane slice:
+ *     warp 0 -> TMEM lanes/rows  0..31
+ *     warp 1 -> TMEM lanes/rows 32..63
+ *     warp 2 -> TMEM lanes/rows 64..95
+ *     warp 3 -> TMEM lanes/rows 96..127
+ *   All those warps use the same taddr for the same column group.
+ *
+ * No PyTorch fallback here.  No FP32 einsum.  The only FP32 CUDA-core work is the
+ * unavoidable post-MMA dequant/ReLU/weighted-reduction/top-k epilogue.
+ */
+
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <ATen/ATen.h>
+#include <c10/cuda/CUDAStream.h>
+#include <torch/extension.h>
+#include <cstdint>
+#include <cfloat>
+#include <cmath>
+
+static constexpr float E4M3_MAX = 448.0f;
+static constexpr int NTHREADS = 192;
+static constexpr int NWARPS = 6;
+typedef unsigned short bf16_t;
+
+// ---- PTX helpers ----
+__device__ __forceinline__ float bf16_to_f32_ptx(bf16_t h) {
+    float f; asm("cvt.f32.bf16 %0, %1;" : "=f"(f) : "h"(h)); return f;
+}
+__device__ __forceinline__ uint8_t fp8_e4m3_from_f32(float x) {
+    x = fminf(fmaxf(x, -E4M3_MAX), E4M3_MAX);
+    __nv_fp8_e4m3 v(x);
+    return *reinterpret_cast<uint8_t*>(&v);
+}
+
+// ---- UMMA helpers (mirrors the B1 FMHA helpers) ----
+__device__ __forceinline__ uint64_t desc_encode(uint64_t byte_val) { return byte_val >> 4; }
+
+__device__ __forceinline__ uint64_t make_umma_desc_kmajor_none(uint32_t smem_addr, int block_mn) {
+    const uint64_t LBO = block_mn * 16;
+    const uint64_t SBO = 128;
+    uint64_t desc = 0;
+    desc |= desc_encode(smem_addr) & 0x3FFF;
+    desc |= (desc_encode(LBO) & 0x3FFF) << 16;
+    desc |= (desc_encode(SBO) & 0x3FFF) << 32;
+    desc |= 1ULL << 46;
+    return desc;
+}
+
+__device__ __forceinline__ uint32_t make_idesc_f8_e4m3(int block_m, int block_n) {
+    return (1U << 4) | ((uint32_t)(block_n >> 3) << 17) | ((uint32_t)(block_m >> 4) << 24);
+}
+
+__device__ __forceinline__ void umma_ss_f8f6f4(uint32_t tmem_c, uint64_t desc_a, uint64_t desc_b,
+                                               uint32_t i_desc, bool accumulate) {
+    uint32_t scaleC_bits = accumulate ? 0x3F800000u : 0u;
+    asm volatile("{\n\t.reg .pred p;\n\tsetp.ne.b32 p, %4, 0;\n\t"
+        "tcgen05.mma.cta_group::1.kind::f8f6f4 [%0], %1, %2, %3, p;\n\t}"
+        :: "r"(tmem_c), "l"(desc_a), "l"(desc_b), "r"(i_desc), "r"(scaleC_bits)
+        : "memory");
+}
+
+__device__ __forceinline__ void tmem_alloc(uint32_t smem_ptr, int num_cols) {
+    asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;"
+        :: "r"(smem_ptr), "r"(num_cols) : "memory");
+}
+__device__ __forceinline__ void tmem_dealloc(uint32_t tmem_ptr, int num_cols) {
+    asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;"
+        :: "r"(tmem_ptr), "r"(num_cols) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_init_cta(uint32_t smem_mbar, uint32_t arrival_count = 1) {
+    asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;"
+        :: "r"(smem_mbar), "r"(arrival_count) : "memory");
+}
+
+__device__ __forceinline__ void tcgen05_commit_mma(uint32_t smem_mbar) {
+    asm volatile("tcgen05.commit.cta_group::1.mbarrier::arrive::one.b64 [%0];"
+        :: "r"(smem_mbar) : "memory");
+}
+
+__device__ __forceinline__ void mbarrier_wait_cta(uint32_t smem_mbar, int phase) {
+    asm volatile(
+        "{\n\t"
+        ".reg .pred p;\n\t"
+        "B2_WAIT_MMA:\n\t"
+        "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 p, [%0], %1, %2;\n\t"
+        "@p bra.uni B2_DONE_MMA;\n\t"
+        "bra.uni B2_WAIT_MMA;\n\t"
+        "B2_DONE_MMA:\n\t"
+        "}\n"
+        :: "r"(smem_mbar), "r"(phase), "r"(0x989680)
+        : "memory");
+}
+
+// ---- FP8 canonical SMEM layout for tcgen05.mma.kind::f8f6f4 ----
+__device__ __forceinline__ int canon_idx_fp8_128x32(int r, int c) {
+    int core_mn = r >> 3;
+    int core_k = c >> 4;
+    int local_r = r & 7;
+    int local_c = c & 15;
+    return core_k * 16 * 128 + core_mn * 128 + local_r * 16 + local_c;
+}
+
+// ---- Top-k helpers ----
+#ifndef INDEXER_LOCAL_K
+#define INDEXER_LOCAL_K 8
+#endif
+
+__device__ __forceinline__ void local_heap_insert(float* scores, int32_t* blocks,
+                                                   float score, int32_t block_id, int k) {
+    if (score <= scores[0]) return;
+    scores[0] = score; blocks[0] = block_id;
+    int root = 0;
+    while (root < (k >> 1)) {
+        int left = 2 * root + 1, right = 2 * root + 2, smallest = root;
+        if (left < k && scores[left] < scores[smallest]) smallest = left;
+        if (right < k && scores[right] < scores[smallest]) smallest = right;
+        if (smallest == root) break;
+        float ts = scores[root]; int32_t ti = blocks[root];
+        scores[root] = scores[smallest]; blocks[root] = blocks[smallest];
+        scores[smallest] = ts; blocks[smallest] = ti;
+        root = smallest;
+    }
+}
+
+__device__ __forceinline__ void heap_insert_shared(float* heap_scores, int32_t* heap_blocks,
+                                                    float score, int32_t block_id, int k) {
+    if (score <= heap_scores[0]) return;
+    heap_scores[0] = score; heap_blocks[0] = block_id;
+    int root = 0;
+    while (root < (k >> 1)) {
+        int left = 2 * root + 1, right = 2 * root + 2, smallest = root;
+        if (left < k && heap_scores[left] < heap_scores[smallest]) smallest = left;
+        if (right < k && heap_scores[right] < heap_scores[smallest]) smallest = right;
+        if (smallest == root) break;
+        float ts = heap_scores[root]; int32_t ti = heap_blocks[root];
+        heap_scores[root] = heap_scores[smallest]; heap_blocks[root] = heap_blocks[smallest];
+        heap_scores[smallest] = ts; heap_blocks[smallest] = ti;
+        root = smallest;
+    }
+}
+
+// ===========================================================================
+// Kernel
+// ===========================================================================
+
+template<int SK_TILE=128>
+__global__ void __launch_bounds__(192)
+indexer_fp8_score_topk_kernel(
+    const bf16_t* __restrict__ q_bf16,     // (n_ih, ihd) BF16 row-major
+    const uint8_t* __restrict__ k_fp8,     // (n_comp, ihd) FP8_E4M3 bytes
+    const float* __restrict__ k_scale,     // (n_comp,) FP32 dequant scales
+    const bf16_t* __restrict__ w_h_bf16,   // (n_ih,) BF16 weights
+    int32_t* __restrict__ topk_indices,    // (top_k,) int32 output
+    int n_comp, int n_ih, int ihd, int top_k
+) {
+    constexpr int MMA_K_F8 = 32;
+    constexpr int NKT = 4;               // ihd=128 / 32
+    constexpr int TILE_F8 = 128 * 32;    // bytes per canonical FP8 tile
+    constexpr int TMEM_COLS = 512;       // full 128 lanes x 512 columns allocation
+
+    const int tid = threadIdx.x;
+    const int wid = tid >> 5;
+    const int lane = tid & 31;
+    const bool is_mma_warp = (wid == 4);
+
+    __shared__ float sQ_amax_warp[NWARPS];
+
+    // ---- SMEM layout ----
+    extern __shared__ __align__(128) char sbuf[];
+    size_t off = 0;
+    uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off += 4;
+    off = (off + 15) & ~(size_t)15;
+    uint64_t* sMbar = (uint64_t*)(sbuf + off); off += 8;
+    off = (off + 127) & ~(size_t)127;
+
+    uint8_t* sQ8 = (uint8_t*)(sbuf + off); off += TILE_F8;
+    off = (off + 127) & ~(size_t)127;
+    uint8_t* sK8 = (uint8_t*)(sbuf + off); off += TILE_F8;
+    off = (off + 127) & ~(size_t)127;
+
+    float* sQ_scale = (float*)(sbuf + off); off += 128 * sizeof(float);
+    off = (off + 127) & ~(size_t)127;
+    float* sW_h = (float*)(sbuf + off); off += 128 * sizeof(float);
+    off = (off + 127) & ~(size_t)127;
+
+    // Two warp partial sums: warp 0 covers heads 0..31, warp 1 covers 32..63.
+    float* sWarpScores = (float*)(sbuf + off); off += 2 * SK_TILE * sizeof(float);
+    off = (off + 127) & ~(size_t)127;
+
+    float* sMergeScores = (float*)(sbuf + off); off += top_k * sizeof(float);
+    int32_t* sMergeBlocks = (int32_t*)(sbuf + off); off += top_k * sizeof(int32_t);
+    float* sCandScores = (float*)(sbuf + off); off += NTHREADS * INDEXER_LOCAL_K * sizeof(float);
+    int32_t* sCandBlocks = (int32_t*)(sbuf + off); off += NTHREADS * INDEXER_LOCAL_K * sizeof(int32_t);
+
+    float local_scores[INDEXER_LOCAL_K];
+    int32_t local_blocks[INDEXER_LOCAL_K];
+    #pragma unroll
+    for (int i = 0; i < INDEXER_LOCAL_K; i++) {
+        local_scores[i] = -INFINITY;
+        local_blocks[i] = -1;
+    }
+
+    for (int i = tid; i < 128; i += NTHREADS) {
+        sQ_scale[i] = 0.0f;
+        sW_h[i] = 0.0f;
+    }
+    for (int i = tid; i < n_ih; i += NTHREADS) sW_h[i] = bf16_to_f32_ptx(w_h_bf16[i]);
+    __syncthreads();
+
+    // ---- Phase 0: Q per-row amax + scale ----
+    for (int h = 0; h < n_ih; h++) {
+        float local_max = 0.0f;
+        for (int d = tid; d < ihd; d += NTHREADS) {
+            local_max = fmaxf(local_max, fabsf(bf16_to_f32_ptx(q_bf16[h * ihd + d])));
+        }
+        for (int o = 16; o > 0; o >>= 1)
+            local_max = fmaxf(local_max, __shfl_down_sync(0xffffffff, local_max, o));
+        if (lane == 0) sQ_amax_warp[wid] = local_max;
+        __syncthreads();
+
+        float amax = 0.0f;
+        if (tid < 32) {
+            amax = (tid < NWARPS) ? sQ_amax_warp[tid] : 0.0f;
+            for (int o = 16; o > 0; o >>= 1)
+                amax = fmaxf(amax, __shfl_down_sync(0xffffffff, amax, o));
+        }
+        if (tid == 0) {
+            float scale = amax / E4M3_MAX;
+            sQ_scale[h] = (scale < 1e-8f) ? 1e-8f : scale;
+        }
+        __syncthreads();
+    }
+
+    // ---- TMEM + mbarrier init ----
+    const uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(sMbar);
+    if (tid == 0) {
+        mbarrier_init_cta(mbar_addr, 1);
+        asm volatile("fence.mbarrier_init.release.cluster;" ::: "memory");
+    }
+    __syncthreads();
+
+    if (is_mma_warp) tmem_alloc((uint32_t)__cvta_generic_to_shared(sTmemBase), TMEM_COLS);
+    asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+    __syncthreads();
+    uint32_t tb = *sTmemBase;
+
+    const int n_k_tiles = (n_comp + SK_TILE - 1) / SK_TILE;
+    const uint32_t idesc_f8 = make_idesc_f8_e4m3(128, 128);
+    int mma_phase = 0;
+
+    for (int kv_tile = 0; kv_tile < n_k_tiles; kv_tile++) {
+        const int kv_start = kv_tile * SK_TILE;
+        const int kv_len = min(SK_TILE, n_comp - kv_start);
+
+        for (int i = tid; i < 2 * SK_TILE; i += NTHREADS) sWarpScores[i] = 0.0f;
+        __syncthreads();
+
+        // ---- FP8 QK GEMM over ihd=128 in four K-slices ----
+        for (int kt = 0; kt < NKT; kt++) {
+            for (int i = tid; i < TILE_F8; i += NTHREADS) { sQ8[i] = 0; sK8[i] = 0; }
+            __syncthreads();
+
+            for (int i = tid; i < n_ih * MMA_K_F8; i += NTHREADS) {
+                int row = i / MMA_K_F8;
+                int col = i % MMA_K_F8;
+                int d = kt * MMA_K_F8 + col;
+                float val = bf16_to_f32_ptx(q_bf16[row * ihd + d]);
+                sQ8[canon_idx_fp8_128x32(row, col)] = fp8_e4m3_from_f32(val / sQ_scale[row]);
+            }
+            for (int i = tid; i < kv_len * MMA_K_F8; i += NTHREADS) {
+                int row = i / MMA_K_F8;
+                int col = i % MMA_K_F8;
+                int d = kt * MMA_K_F8 + col;
+                int g_row = kv_start + row;
+                sK8[canon_idx_fp8_128x32(row, col)] = k_fp8[(int64_t)g_row * ihd + d];
+            }
+            __syncthreads();
+            // Generic-proxy SMEM writes above must be visible to the tcgen05 async proxy.
+            asm volatile("fence.proxy.async.shared::cta;" ::: "memory");
+            __syncthreads();
+
+            if (is_mma_warp && lane == 0) {
+                uint64_t dq = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sQ8), 128);
+                uint64_t dk = make_umma_desc_kmajor_none((uint32_t)__cvta_generic_to_shared(sK8), 128);
+                umma_ss_f8f6f4(tb, dq, dk, idesc_f8, kt > 0);
+            }
+            __syncthreads();
+        }
+
+        // Track completion of all prior tcgen05.mma operations before TMEM reads.
+        if (is_mma_warp && lane == 0) tcgen05_commit_mma(mbar_addr);
+        mbarrier_wait_cta(mbar_addr, mma_phase);
+        mma_phase ^= 1;
+        asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
+        __syncthreads();
+
+        // ---- Read TMEM and reduce across indexer heads ----
+        // warps 0/1 read the same taddr; hardware maps them to lanes 0..31 / 32..63.
+        if (wid < 2) {
+            const int h = wid * 32 + lane;
+            const bool h_valid = h < n_ih;
+            const float q_s = h_valid ? sQ_scale[h] : 0.0f;
+            const float wh = h_valid ? sW_h[h] : 0.0f;
+
+            #pragma unroll
+            for (int n = 0; n < SK_TILE / 8; n++) {
+                int col_base = n * 8;
+                float tmp[8];
+                asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
+                    : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
+                      "=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
+                    : "r"(tb + col_base));
+                asm volatile("tcgen05.wait::ld.sync.aligned;" ::: "memory");
+
+                float contrib[8];
+                #pragma unroll
+                for (int j = 0; j < 8; j++) {
+                    int c = col_base + j;
+                    if (h_valid && c < kv_len) {
+                        float logit = tmp[j] * q_s * k_scale[kv_start + c];
+                        contrib[j] = wh * fmaxf(logit, 0.0f);
+                    } else {
+                        contrib[j] = 0.0f;
+                    }
+                }
+
+                #pragma unroll
+                for (int j = 0; j < 8; j++) {
+                    float v = contrib[j];
+                    for (int o = 16; o > 0; o >>= 1) v += __shfl_down_sync(0xffffffff, v, o);
+                    if (lane == 0 && (col_base + j) < kv_len) {
+                        sWarpScores[wid * SK_TILE + col_base + j] = v;
+                    }
+                }
+            }
+        }
+        __syncthreads();
+
+        // ---- Merge per-column scores into per-thread local top-k heaps ----
+        for (int c = tid; c < kv_len; c += NTHREADS) {
+            float score = sWarpScores[c] + sWarpScores[SK_TILE + c];
+            local_heap_insert(local_scores, local_blocks, score, kv_start + c, INDEXER_LOCAL_K);
+        }
+        __syncthreads();
+    }
+
+    if (is_mma_warp) tmem_dealloc(tb, TMEM_COLS);
+    __syncthreads();
+
+    // ---- Block-level top-k merge ----
+    for (int i = tid; i < top_k; i += NTHREADS) {
+        sMergeScores[i] = -INFINITY;
+        sMergeBlocks[i] = -1;
+    }
+    int my_offset = tid * INDEXER_LOCAL_K;
+    #pragma unroll
+    for (int i = 0; i < INDEXER_LOCAL_K; i++) {
+        sCandScores[my_offset + i] = local_scores[i];
+        sCandBlocks[my_offset + i] = local_blocks[i];
+    }
+    __syncthreads();
+
+    if (tid == 0) {
+        for (int i = 0; i < NTHREADS * INDEXER_LOCAL_K; i++) {
+            if (sCandBlocks[i] >= 0) {
+                heap_insert_shared(sMergeScores, sMergeBlocks,
+                                   sCandScores[i], sCandBlocks[i], top_k);
+            }
+        }
+
+        // Sort descending for deterministic torch.topk-like output order.
+        for (int i = 0; i < top_k; i++) {
+            int best = i;
+            for (int j = i + 1; j < top_k; j++) {
+                if (sMergeScores[j] > sMergeScores[best]) best = j;
+            }
+            if (best != i) {
+                float ts = sMergeScores[i]; int32_t ti = sMergeBlocks[i];
+                sMergeScores[i] = sMergeScores[best]; sMergeBlocks[i] = sMergeBlocks[best];
+                sMergeScores[best] = ts; sMergeBlocks[best] = ti;
+            }
+            topk_indices[i] = sMergeBlocks[i];
+        }
+    }
+}
+
+// ===========================================================================
+// PyTorch binding
+// ===========================================================================
+
+static size_t align_up(size_t x, size_t a) { return (x + a - 1) & ~(a - 1); }
+
+void indexer_fp8_score_topk_cuda(
+    torch::Tensor q_bf16,         // (n_ih, ihd) BF16
+    torch::Tensor k_fp8,          // (n_comp, ihd) uint8/float8_e4m3fn
+    torch::Tensor k_scale,        // (n_comp,) FP32
+    torch::Tensor w_h,            // (n_ih,) BF16
+    torch::Tensor topk_indices,   // (top_k,) int32 output
+    int64_t n_ih, int64_t ihd, int64_t top_k
+) {
+    TORCH_CHECK(q_bf16.is_cuda() && q_bf16.scalar_type() == torch::kBFloat16);
+    TORCH_CHECK(k_fp8.is_cuda());
+    TORCH_CHECK(k_scale.is_cuda() && k_scale.scalar_type() == torch::kFloat32);
+    TORCH_CHECK(w_h.is_cuda() && w_h.scalar_type() == torch::kBFloat16);
+    TORCH_CHECK(topk_indices.is_cuda() && topk_indices.scalar_type() == torch::kInt32);
+    TORCH_CHECK(n_ih == 64 && ihd == 128, "B2 first pass is specialized to n_ih=64, ihd=128");
+    TORCH_CHECK(top_k > 0, "top_k must be positive");
+
+    int n_comp = k_fp8.size(0);
+    TORCH_CHECK(n_comp > 0, "n_comp must be positive");
+    TORCH_CHECK(k_fp8.size(1) == ihd, "k_fp8 must have shape (n_comp, ihd)");
+    TORCH_CHECK(k_scale.numel() >= n_comp, "k_scale must contain at least n_comp scales");
+    TORCH_CHECK(topk_indices.numel() >= top_k, "topk_indices is smaller than top_k");
+
+    auto k8 = k_fp8.dtype() == torch::kUInt8 ? k_fp8 : k_fp8.view(torch::kUInt8);
+
+    // Must exactly mirror kernel SMEM layout.  The previous B2 missed the score
+    // scratch allocation, which can corrupt following SMEM and manifest as a hang.
+    size_t smem = 0;
+    smem += 4;                                // sTmemBase
+    smem = align_up(smem, 16);
+    smem += 8;                                // sMbar
+    smem = align_up(smem, 128);
+    smem += 128 * 32; smem = align_up(smem, 128);  // sQ8
+    smem += 128 * 32; smem = align_up(smem, 128);  // sK8
+    smem += 128 * 4;  smem = align_up(smem, 128);  // sQ_scale
+    smem += 128 * 4;  smem = align_up(smem, 128);  // sW_h
+    smem += 2 * 128 * 4; smem = align_up(smem, 128); // sWarpScores
+    smem += (size_t)top_k * 4;                       // sMergeScores
+    smem += (size_t)top_k * 4;                       // sMergeBlocks
+    smem += 192 * INDEXER_LOCAL_K * 4;               // sCandScores
+    smem += 192 * INDEXER_LOCAL_K * 4;               // sCandBlocks
+
+    cudaFuncSetAttribute(indexer_fp8_score_topk_kernel<128>,
+                         cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
+
+    indexer_fp8_score_topk_kernel<128><<<1, 192, smem, c10::cuda::getCurrentCUDAStream()>>>(
+        reinterpret_cast<const bf16_t*>(q_bf16.data_ptr<at::BFloat16>()),
+        k8.data_ptr<uint8_t>(),
+        k_scale.data_ptr<float>(),
+        reinterpret_cast<const bf16_t*>(w_h.data_ptr<at::BFloat16>()),
+        topk_indices.data_ptr<int32_t>(),
+        n_comp, (int)n_ih, (int)ihd, (int)top_k);
+
+    C10_CUDA_CHECK(cudaGetLastError());
+}
+
+PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
+    m.def("indexer_fp8_score_topk", &indexer_fp8_score_topk_cuda,
+          "B2 FP8 tensor-core indexer scoring + weighted ReLU + top-k");
+}

dsv4/kernels/cuda/indexer_score_topk.cu

@@ -1,26 +1,87 @@
+// indexer_score_topk.cu — Fused score + ReLU + weighted-sum + top-k kernel.
+//
+// CSA Lightning Indexer (paper §2.3.1, eq. 16):
+//   I[t,s] = Σ_h w_h[t,h] · ReLU(q_I[t,h] · K^IComp[s,h])
+//   Selected = TopK(I[t,:], k=csa_top_k)
+//
+// One CTA per query token. Streams indexer keys from the paged pool,
+// computes per-head dot products in FP32, ReLU, weighted sum, top-k.
+//
+// Top-k strategy: each thread maintains a private top-k in registers
+// over its strided slice of entries, then a block-level merge via
+// bitonic sort on the shared heap. No in-loop barriers, no spinlocks.
+//
+// Phase 1 (this file): FP32 dot products via standard CUDA ops.
+// Phase 2 (future): swap to FP4 tcgen05 MMA for production throughput.
+
 #include <cuda.h>
-#include <cuda_fp8.h>
 #include <cuda_bf16.h>
+#include <cuda_fp8.h>
 #include <torch/extension.h>
 #include <c10/cuda/CUDAException.h>
+
 #include <limits>
 
+// FP4 E2M1 magnitude lookup (same as production)
+__constant__ float E2M1_LUT[8] = {0.0f, 0.5f, 1.0f, 1.5f, 2.0f, 3.0f, 4.0f, 6.0f};
+
 __device__ __forceinline__ float dequant_fp4_scalar(
-    uint8_t packed, int lane, float group_scale, float global_scale
+    uint8_t packed, int lane,
+    float group_scale, float global_scale
 ) {
     int nibble = (lane == 0) ? (packed & 0x0F) : (packed >> 4);
     int sign = (nibble >> 3) & 1;
     int mag_bits = nibble & 0x07;
-
-    // E2M1 LUT — must match Python dsv4/ops/quantize.py E2M1_MAGNITUDES
-    // 0b000=0, 0b001=0.5, 0b010=1, 0b011=1.5, 0b100=2, 0b101=3, 0b110=4, 0b111=6
-    constexpr float LUT[8] = {0.0f, 0.5f, 1.0f, 1.5f, 2.0f, 3.0f, 4.0f, 6.0f};
-    float magnitude = LUT[mag_bits];
+    float magnitude = E2M1_LUT[mag_bits];
     float val = magnitude * group_scale * global_scale;
     return sign ? -val : val;
 }
 
-__device__ void heap_insert(
+// ---- Per-thread local top-k ----
+// Each thread keeps LOCAL_K best scores in registers.
+// LOCAL_K is a tuning parameter: larger = more accurate merge,
+// smaller = less register pressure.
+// For top_k=1024 and 128 threads: LOCAL_K=8 means 128*8=1024 candidates
+// for the block-level merge, which is exact.
+// For top_k=512 and 128 threads: LOCAL_K=4 gives 512 candidates, also exact.
+// If top_k > n_threads * LOCAL_K, the merge is approximate (top-K of
+// n_threads*LOCAL_K candidates). Increase LOCAL_K or n_threads to compensate.
+
+#ifndef INDEXER_LOCAL_K
+#define INDEXER_LOCAL_K 8
+#endif
+
+__device__ __forceinline__ void local_heap_insert(
+    float* scores, int32_t* blocks,
+    float score, int32_t block_id, int k
+) {
+    if (score <= scores[0]) return;
+    scores[0] = score;
+    blocks[0] = block_id;
+    // Sift down
+    int root = 0;
+    while (root < (k >> 1)) {
+        int left = 2 * root + 1;
+        int right = 2 * root + 2;
+        int smallest = root;
+        if (left < k && scores[left] < scores[smallest]) smallest = left;
+        if (right < k && scores[right] < scores[smallest]) smallest = right;
+        if (smallest == root) break;
+        float ts = scores[root]; int32_t ti = blocks[root];
+        scores[root] = scores[smallest]; blocks[root] = blocks[smallest];
+        scores[smallest] = ts; blocks[smallest] = ti;
+        root = smallest;
+    }
+}
+
+// ---- Block-level merge: merge n_threads × LOCAL_K candidates ----
+// Each thread writes its local top-k to shared memory, then a single
+// thread (or warp) does a final top-k selection from the combined set.
+// Total candidates = n_threads * LOCAL_K.
+// For top_k <= total_candidates, this is exact.
+// For top_k > total_candidates, increase LOCAL_K.
+
+__device__ __forceinline__ void heap_insert_shared(
     float* heap_scores, int32_t* heap_blocks,
     float score, int32_t block_id, int k
 ) {
@@ -42,7 +103,11 @@ __device__ void heap_insert(
     }
 }
 
-__global__ void indexer_score_topk_kernel(
+// ===========================================================================
+// Main kernel
+// ===========================================================================
+
+__global__ void indexer_score_topk_fp32_kernel(
     const float* __restrict__ q_I,
     const float* __restrict__ w_h,
     const uint8_t* __restrict__ keys_fp4,
@@ -56,58 +121,61 @@ __global__ void indexer_score_topk_kernel(
 ) {
     int t = blockIdx.x;
     if (t >= gridDim.x) return;
+
     int tid = threadIdx.x;
     int n_threads = blockDim.x;
     int num_valid = valid_lens[t];
     int n_groups = head_dim / 16;
-    int total_groups = n_heads * n_groups;
     int n_bytes = head_dim / 2;
-    int total_bytes = n_heads * n_bytes;
 
-    // Per-thread heap in REGISTERS (top_k <= 1024, but for small k this works)
-    // Actually, use shared memory with a simple layout
-    __shared__ float s_heap_scores[1024];  // max top_k
-    __shared__ int32_t s_heap_blocks[1024];
-    __shared__ float s_w[64];  // max n_heads
-    __shared__ int s_lock;
+    // ---- Per-thread local top-k in registers ----
+    // LOCAL_K entries per thread. Min-heap (root = smallest of local best).
+    float local_scores[INDEXER_LOCAL_K];
+    int32_t local_blocks[INDEXER_LOCAL_K];
+    for (int i = 0; i < INDEXER_LOCAL_K; i++) {
+        local_scores[i] = -INFINITY;
+        local_blocks[i] = -1;
+    }
+
+    // ---- Load w_h into shared memory ----
+    extern __shared__ char smem[];
+    float* smem_w = reinterpret_cast<float*>(smem);
+    // The rest of smem is used for the merge phase (allocated after w_h)
+    // Layout: [w_h: n_heads floats] [merge_scores: top_k floats] [merge_blocks: top_k ints]
+    //         [per_thread_scores: n_threads * LOCAL_K floats] [per_thread_blocks: n_threads * LOCAL_K ints]
+    // But we allocate dynamically, so let's compute offsets.
 
-    // Load w_h
     for (int h = tid; h < n_heads; h += n_threads) {
-        s_w[h] = w_h[t * n_heads + h];
+        smem_w[h] = w_h[t * n_heads + h];
     }
-    // Init heap
-    for (int i = tid; i < top_k; i += n_threads) {
-        s_heap_scores[i] = -INFINITY;
-        s_heap_blocks[i] = -1;
-    }
-    if (tid == 0) s_lock = 0;
-    __syncthreads();
+    __syncthreads();  // safe — outside the strided loop
+
+    // ---- Stream over entries (strided, no barriers) ----
+    // Each thread handles entries s = tid, tid+n_threads, tid+2*n_threads, ...
+    // No __syncthreads() in this loop. No shared heap access.
+    // Each thread accumulates into its private register heap.
 
-    // Stream over entries
     for (int s = tid; s < num_valid; s += n_threads) {
         int logical_block = s / entries_per_block;
         int slot_in_block = s % entries_per_block;
         int phys_block = block_table[t * max_logical_blocks + logical_block];
-        int flat = phys_block * entries_per_block + slot_in_block;
+        int block_entry = phys_block * entries_per_block + slot_in_block;
 
-        float gs = key_gscale[phys_block];
+        float global_s = key_gscale[phys_block];
 
-        // Compute score
         float score = 0.0f;
         for (int h = 0; h < n_heads; h++) {
             float dot = 0.0f;
-            int h_byte_off = h * n_bytes;
-            int h_group_off = h * n_groups;
             for (int g = 0; g < n_groups; g++) {
-                uint8_t raw_sc = key_scale[flat * total_groups + h_group_off + g];
+                uint8_t raw_scale = key_scale[block_entry * n_groups + g];
                 __nv_fp8_e4m3 fp8_s;
-                fp8_s.__x = raw_sc;
-                float grp_s = (float)fp8_s * gs;
+                fp8_s.__x = raw_scale;
+                float group_s = (float)fp8_s * global_s;
 
                 for (int b = 0; b < 8; b++) {
-                    uint8_t packed = keys_fp4[flat * total_bytes + h_byte_off + g * 8 + b];
-                    float v0 = dequant_fp4_scalar(packed, 0, grp_s, 1.0f);
-                    float v1 = dequant_fp4_scalar(packed, 1, grp_s, 1.0f);
+                    uint8_t packed = keys_fp4[block_entry * n_bytes + g * 8 + b];
+                    float v0 = dequant_fp4_scalar(packed, 0, group_s, 1.0f);
+                    float v1 = dequant_fp4_scalar(packed, 1, group_s, 1.0f);
                     int d0 = g * 16 + 2 * b;
                     int d1 = d0 + 1;
                     dot += v0 * q_I[t * n_heads * head_dim + h * head_dim + d0];
@@ -115,52 +183,124 @@ __global__ void indexer_score_topk_kernel(
                 }
             }
             if (dot > 0.0f) {
-                score += s_w[h] * dot;
+                score += smem_w[h] * dot;
             }
         }
 
-        // Insert into shared heap (serialized via spinlock)
-        while (atomicCAS(&s_lock, 0, 1) != 0) {}
-        heap_insert(s_heap_scores, s_heap_blocks, score, s, top_k);
-        atomicExch(&s_lock, 0);
+        // Insert into per-thread local heap (registers, no sync needed)
+        local_heap_insert(local_scores, local_blocks, score, s, INDEXER_LOCAL_K);
     }
-    __syncthreads();
 
-    // Sort + write output
+    // ---- Block-level merge ----
+    // Each thread writes its LOCAL_K candidates to shared memory.
+    // Then one thread builds the final top-k from all candidates.
+    // Total candidates = n_threads * LOCAL_K.
+    // For top_k=1024, n_threads=128, LOCAL_K=8: 1024 candidates, exact merge.
+    // For top_k=512, n_threads=128, LOCAL_K=4: 512 candidates, exact merge.
+
+    float* merge_scores = smem_w + n_heads;
+    int32_t* merge_blocks = reinterpret_cast<int32_t*>(merge_scores + top_k);
+    float* per_thread_scores = reinterpret_cast<float*>(merge_blocks + top_k);
+    int32_t* per_thread_blocks = reinterpret_cast<int32_t*>(per_thread_scores + n_threads * INDEXER_LOCAL_K);
+
+    // Initialize merge heap
+    for (int i = tid; i < top_k; i += n_threads) {
+        merge_scores[i] = -INFINITY;
+        merge_blocks[i] = -1;
+    }
+
+    // Write local top-k to per-thread region in shared memory
+    int my_offset = tid * INDEXER_LOCAL_K;
+    for (int i = 0; i < INDEXER_LOCAL_K; i++) {
+        per_thread_scores[my_offset + i] = local_scores[i];
+        per_thread_blocks[my_offset + i] = local_blocks[i];
+    }
+    __syncthreads();  // wait for all threads to write their candidates
+
+    // Single thread builds the final top-k from all candidates
+    // This is O(n_threads * LOCAL_K * log(top_k)) — fast for reasonable sizes.
+    // For n_threads=128, LOCAL_K=8, top_k=1024: 1024 inserts, ~10K comparisons.
+    if (tid == 0) {
+        for (int i = 0; i < n_threads * INDEXER_LOCAL_K; i++) {
+            if (per_thread_scores[i] > -INFINITY) {
+                heap_insert_shared(merge_scores, merge_blocks,
+                                   per_thread_scores[i], per_thread_blocks[i], top_k);
+            }
+        }
+    }
+    __syncthreads();  // wait for merge to complete
+
+    // ---- Write top-k indices to global memory ----
+    // Sort the merge heap by score descending (selection sort, top_k <= 1024)
     if (tid == 0) {
         for (int i = 0; i < top_k; i++) {
             int best = i;
             for (int j = i + 1; j < top_k; j++) {
-                if (s_heap_scores[j] > s_heap_scores[best]) best = j;
+                if (merge_scores[j] > merge_scores[best] ||
+                    (merge_scores[j] == merge_scores[best] &&
+                     merge_blocks[j] < merge_blocks[best])) {
+                    best = j;
+                }
             }
             if (best != i) {
-                float ts = s_heap_scores[i]; int32_t ti = s_heap_blocks[i];
-                s_heap_scores[i] = s_heap_scores[best]; s_heap_blocks[i] = s_heap_blocks[best];
-                s_heap_scores[best] = ts; s_heap_blocks[best] = ti;
+                float ts = merge_scores[i]; int32_t ti = merge_blocks[i];
+                merge_scores[i] = merge_scores[best]; merge_blocks[i] = merge_blocks[best];
+                merge_scores[best] = ts; merge_blocks[best] = ti;
             }
-            topk_indices[t * top_k + i] = s_heap_blocks[i];
+            topk_indices[t * top_k + i] = merge_blocks[i];
         }
     }
 }
 
-void indexer_score_topk_cuda(
-    torch::Tensor q_I, torch::Tensor w_h,
-    torch::Tensor keys_fp4, torch::Tensor key_scale, torch::Tensor key_gscale,
-    torch::Tensor block_table, torch::Tensor valid_lens, torch::Tensor topk_indices,
-    int64_t n_heads, int64_t head_dim, int64_t top_k, int64_t entries_per_block
+
+// ===========================================================================
+// PyTorch binding
+// ===========================================================================
+
+void indexer_score_topk_fp32_cuda(
+    torch::Tensor q_I,
+    torch::Tensor w_h,
+    torch::Tensor keys_fp4,
+    torch::Tensor key_scale,
+    torch::Tensor key_gscale,
+    torch::Tensor block_table,
+    torch::Tensor valid_lens,
+    torch::Tensor topk_indices,
+    int64_t n_heads, int64_t head_dim, int64_t top_k,
+    int64_t entries_per_block
 ) {
     int T = q_I.size(0);
     int max_logical_blocks = block_table.size(1);
-    indexer_score_topk_kernel<<<T, 128>>>(
-        q_I.data_ptr<float>(), w_h.data_ptr<float>(),
-        keys_fp4.data_ptr<uint8_t>(), key_scale.data_ptr<uint8_t>(),
-        key_gscale.data_ptr<float>(), block_table.data_ptr<int32_t>(),
-        valid_lens.data_ptr<int32_t>(), topk_indices.data_ptr<int32_t>(),
-        (int)n_heads, (int)head_dim, (int)top_k, (int)entries_per_block, max_logical_blocks
+    int threads = 128;
+
+    // SMEM layout:
+    //   w_h: n_heads floats
+    //   merge_scores: top_k floats
+    //   merge_blocks: top_k ints
+    //   per_thread_scores: n_threads * INDEXER_LOCAL_K floats
+    //   per_thread_blocks: n_threads * INDEXER_LOCAL_K ints
+    int smem_bytes = n_heads * sizeof(float)
+                   + top_k * sizeof(float)
+                   + top_k * sizeof(int32_t)
+                   + threads * INDEXER_LOCAL_K * sizeof(float)
+                   + threads * INDEXER_LOCAL_K * sizeof(int32_t);
+
+    indexer_score_topk_fp32_kernel<<<T, threads, smem_bytes>>>(
+        q_I.data_ptr<float>(),
+        w_h.data_ptr<float>(),
+        keys_fp4.data_ptr<uint8_t>(),
+        key_scale.data_ptr<uint8_t>(),
+        key_gscale.data_ptr<float>(),
+        block_table.data_ptr<int32_t>(),
+        valid_lens.data_ptr<int32_t>(),
+        topk_indices.data_ptr<int32_t>(),
+        (int)n_heads, (int)head_dim, (int)top_k,
+        (int)entries_per_block, max_logical_blocks
     );
     C10_CUDA_CHECK(cudaGetLastError());
 }
 
 PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
-    m.def("indexer_score_topk", &indexer_score_topk_cuda);
+    m.def("indexer_score_topk_fp32", &indexer_score_topk_fp32_cuda,
+          "Indexer score + top-k (FP32 dot products, no-deadlock)");
 }

dsv4/kernels/cuda/kv_quantize.cu

@@ -0,0 +1,372 @@
+/**
+ * Quantize FP32 tensor to NVFP4.
+ *
+ * Same proven pattern as quantize_nvfp4.cu (which reads BF16),
+ * but takes FP32 input directly — avoids BF16 intermediate.
+ *
+ * This is the correct path for compressor output → NVFP4:
+ *   Compressor produces FP32 → this kernel → NVFP4 stored in KV cache
+ *   No BF16 anywhere in the pipeline.
+ *
+ * Two-kernel approach (proven correct in fused_amax_quantize.cu):
+ *   Kernel 1: amax_gsa_fp32 — compute per-row gsa from FP32 input (GPU-only)
+ *   Kernel 2: quantize_nvfp4_from_fp32 — quantize FP32 → NVFP4 using GPU gsa buffer
+ *
+ * Grid: (N/16, M, 1) — each CTA processes one 16-element block in one row.
+ * Block: 16 threads (1 thread per element, warp amax reduction).
+ */
+
+#include <cuda.h>
+#include <cuda_runtime.h>
+#include <cuda_fp8.h>
+#include <cuda_fp8.hpp>
+#include <ATen/ATen.h>
+#include <c10/cuda/CUDAStream.h>
+#include <torch/extension.h>
+#include <cstdint>
+#include <cfloat>
+
+__device__ __forceinline__ int half_step_to_e2m1(int hs) {
+    if (hs <= 4) return hs;
+    if (hs <= 5) return 4;
+    if (hs <= 7) return 5;
+    if (hs <= 10) return 6;
+    return 7;
+}
+
+// ===========================================================================
+// Kernel 1: Compute per-row amax → gsa from FP32 input
+// Same pattern as amax_gsa.cu but for FP32 (not BF16) input
+// ===========================================================================
+
+__global__ void compute_amax_gsa_fp32_kernel(
+    const float* __restrict__ input,
+    int M, int N,
+    float divisor,
+    float* __restrict__ out_gsa
+) {
+    int m = blockIdx.x;
+    if (m >= M) return;
+
+    float local_max = 0.0f;
+    for (int i = threadIdx.x; i < N; i += 256) {
+        float v = fabsf(input[m * N + i]);
+        local_max = fmaxf(local_max, v);
+    }
+
+    // Warp-level reduction
+    for (int offset = 128; offset > 0; offset >>= 1)
+        local_max = fmaxf(local_max, __shfl_down_sync(0xffffffff, local_max, offset));
+
+    // Block-level reduction using shared memory
+    __shared__ float s_max[8];
+    if (threadIdx.x % 32 == 0)
+        s_max[threadIdx.x / 32] = local_max;
+    __syncthreads();
+
+    if (threadIdx.x < 32) {
+        float v = (threadIdx.x < 8) ? s_max[threadIdx.x] : 0.0f;
+        for (int offset = 16; offset > 0; offset >>= 1)
+            v = fmaxf(v, __shfl_down_sync(0xffffffff, v, offset));
+        if (threadIdx.x == 0)
+            out_gsa[m] = v / divisor;
+    }
+}
+
+// ===========================================================================
+// Kernel 2: Quantize FP32 → NVFP4 using gsa from GPU buffer
+// Same proven pattern as quantize_nvfp4_from_buffer_kernel (fused_amax_quantize.cu)
+// but reads FP32 instead of BF16
+// ===========================================================================
+
+__global__ void quantize_nvfp4_from_fp32_kernel(
+    const float* __restrict__ input,
+    int M, int N,
+    const float* __restrict__ gsa_buffer,  // (M,) GPU buffer with per-row gsa
+    uint8_t* __restrict__ out_fp4,
+    uint8_t* __restrict__ out_sf
+) {
+    int m = blockIdx.y;
+    int n_block = blockIdx.x;
+    if (m >= M || n_block * 16 >= N) return;
+
+    float gsa = gsa_buffer[m];
+
+    float vals[16];
+    float block_amax = 0.0f;
+
+    // Step 1: Read 16 FP32 elements and compute block amax
+    for (int i = 0; i < 16; i++) {
+        int col = n_block * 16 + i;
+        if (col < N) {
+            vals[i] = input[m * N + col] / gsa;
+        } else {
+            vals[i] = 0;
+        }
+        block_amax = fmaxf(block_amax, fabsf(vals[i]));
+    }
+
+    // Step 2: Compute FP8 E4M3 block scale (with FP8 round-trip)
+    float bsf = block_amax / 6.0f;
+    if (block_amax < 6.0f * 0.001953125f) {
+        // Zero/underflow block
+        bsf = 0;
+        for (int i = 0; i < 16; i++) vals[i] = 0;
+    }
+    __nv_fp8_e4m3 bsf8_obj(bsf);
+    float bs = (float)bsf8_obj;  // FP8 round-trip — matches dequant
+    uint8_t bsf8 = *(uint8_t*)&bsf8_obj;
+
+    // Step 3: Quantize each value to FP4 E2M1
+    uint8_t nibbles[16];
+    for (int i = 0; i < 16; i++) {
+        if (bs < 1e-8f) { nibbles[i] = 0; continue; }
+        float s = vals[i] / bs;
+        int hs = __float2int_rn(fminf(fabsf(s), 6.0f) * 2.0f);
+        if (hs > 12) hs = 12;
+        int idx = half_step_to_e2m1(hs);
+        if (s < 0) idx += 8;
+        nibbles[i] = idx;
+    }
+
+    // Step 4: Pack pairs: (nibbles[1] << 4) | nibbles[0], etc.
+    for (int i = 0; i < 8; i++)
+        out_fp4[m * (N / 2) + n_block * 8 + i] = (nibbles[2*i+1] << 4) | nibbles[2*i];
+
+    // Step 5: Write FP8 block scale
+    out_sf[m * (N / 16) + n_block] = bsf8;
+}
+
+// ===========================================================================
+// FP32 GPT-J interleaved RoPE (for compressed KV — no BF16 intermediate)
+// Same math as rope_cuda.cu but operates on FP32 directly.
+// ===========================================================================
+
+__global__ void rope_fp32_kernel(
+    float* __restrict__ x,           // (M, 1, N) FP32 — modified in-place
+    const float* __restrict__ cos_c, // (max_pos, rope_dim/2) FP32
+    const float* __restrict__ sin_c, // (max_pos, rope_dim/2) FP32
+    const int64_t* __restrict__ pos, // (M,) positions
+    int N, int rope_dim, bool inverse
+) {
+    int m = blockIdx.x;
+    if (m >= gridDim.x) return;
+    int64_t p = pos[m];
+    int nope = N - rope_dim;
+    for (int i = threadIdx.x; i < rope_dim / 2; i += 256) {
+        float c = cos_c[p * (rope_dim / 2) + i];
+        float s = sin_c[p * (rope_dim / 2) + i];
+        int ev_idx = m * N + nope + 2 * i;
+        int od_idx = m * N + nope + 2 * i + 1;
+        float ev = x[ev_idx];
+        float od = x[od_idx];
+        if (inverse) {
+            x[ev_idx] = ev * c + od * s;
+            x[od_idx] = -ev * s + od * c;
+        } else {
+            x[ev_idx] = ev * c - od * s;
+            x[od_idx] = ev * s + od * c;
+        }
+    }
+}
+
+// ===========================================================================
+// FP8 E4M3 quantize FP32 → FP8 (for indexer keys — higher precision)
+// ===========================================================================
+
+__global__ void quantize_fp8_e4m3_from_fp32_kernel(
+    const float* __restrict__ input,
+    int M, int N,
+    float* __restrict__ out_scale,  // (M,) per-row scale
+    uint8_t* __restrict__ out_fp8   // (M, N) packed FP8 E4M3
+) {
+    int m = blockIdx.x;
+    if (m >= M) return;
+
+    // Per-row amax → scale = amax / 448.0 (E4M3 max = 448)
+    float local_max = 0.0f;
+    for (int i = threadIdx.x; i < N; i += 256) {
+        float v = fabsf(input[m * N + i]);
+        local_max = fmaxf(local_max, v);
+    }
+    for (int offset = 128; offset > 0; offset >>= 1)
+        local_max = fmaxf(local_max, __shfl_down_sync(0xffffffff, local_max, offset));
+    __shared__ float s_max[8];
+    if (threadIdx.x % 32 == 0) s_max[threadIdx.x / 32] = local_max;
+    __syncthreads();
+    if (threadIdx.x < 32) {
+        float v = (threadIdx.x < 8) ? s_max[threadIdx.x] : 0.0f;
+        for (int offset = 16; offset > 0; offset >>= 1)
+            v = fmaxf(v, __shfl_down_sync(0xffffffff, v, offset));
+        if (threadIdx.x == 0) {
+            float scale = v / 448.0f;
+            if (scale < 1e-8f) scale = 1e-8f;
+            out_scale[m] = scale;
+        }
+    }
+    __syncthreads();
+
+    // Quantize each element
+    float scale = out_scale[m];
+    float inv_scale = 1.0f / scale;
+    for (int i = threadIdx.x; i < N; i += 256) {
+        float v = input[m * N + i] * inv_scale;
+        v = fmaxf(v, -448.0f);
+        v = fminf(v, 448.0f);
+        __nv_fp8_e4m3 obj(v);
+        out_fp8[m * N + i] = *(uint8_t*)&obj;
+    }
+}
+
+// ===========================================================================
+// FP8 E4M3 dequant → BF16 (for indexer key gather)
+// ===========================================================================
+
+__global__ void dequant_fp8_e4m3_kernel(
+    const uint8_t* __restrict__ fp8_data,
+    const float* __restrict__ scale_data,
+    int M, int N,
+    __nv_bfloat16* __restrict__ output
+) {
+    int m = blockIdx.x;
+    if (m >= M) return;
+    float scale = scale_data[m];
+    for (int i = threadIdx.x; i < N; i += 256) {
+        uint8_t byte = fp8_data[m * N + i];
+        __nv_fp8_e4m3 val;
+        memcpy(&val, &byte, 1);
+        float v = (float)val * scale;
+        output[m * N + i] = __float2bfloat16(v);
+    }
+}
+
+__global__ void dequant_fp8_e4m3_selective_kernel(
+    const uint8_t* __restrict__ fp8_data,
+    const float* __restrict__ scale_data,
+    const int32_t* __restrict__ indices,
+    int K, int N,
+    __nv_bfloat16* __restrict__ output
+) {
+    int k = blockIdx.x;
+    if (k >= K) return;
+    int src_row = indices[k];
+    float scale = scale_data[src_row];
+    for (int i = threadIdx.x; i < N; i += 256) {
+        uint8_t byte = fp8_data[src_row * N + i];
+        __nv_fp8_e4m3 val;
+        memcpy(&val, &byte, 1);
+        float v = (float)val * scale;
+        output[k * N + i] = __float2bfloat16(v);
+    }
+}
+
+// ===========================================================================
+// PyTorch bindings
+// ===========================================================================
+
+torch::Tensor compute_amax_gsa_fp32_cuda(torch::Tensor input, double divisor) {
+    int M = input.size(0);
+    int N = input.size(1);
+    auto out_gsa = torch::zeros({M}, input.options().dtype(torch::kFloat32));
+    compute_amax_gsa_fp32_kernel<<<M, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        input.data_ptr<float>(), M, N, (float)divisor, out_gsa.data_ptr<float>());
+    return out_gsa;
+}
+
+std::tuple<torch::Tensor, torch::Tensor> quantize_nvfp4_from_fp32_cuda(
+    torch::Tensor input, torch::Tensor gsa_buffer
+) {
+    int M = input.size(0);
+    int N = input.size(1);
+    TORCH_CHECK(N % 16 == 0, "N must be a multiple of 16 for NVFP4 quantization");
+    TORCH_CHECK(gsa_buffer.size(0) == M, "gsa_buffer size must match M");
+    auto opts = input.options();
+    auto out_fp4 = torch::zeros({M, N / 2}, opts.dtype(torch::kUInt8));
+    auto out_sf = torch::zeros({M, N / 16}, opts.dtype(torch::kUInt8));
+    int nb = N / 16;
+    dim3 grid(nb, M);
+    dim3 block(16);
+    quantize_nvfp4_from_fp32_kernel<<<grid, block, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        input.data_ptr<float>(), M, N, gsa_buffer.data_ptr<float>(),
+        out_fp4.data_ptr<uint8_t>(), out_sf.data_ptr<uint8_t>()
+    );
+    return {out_fp4.view(torch::kFloat4_e2m1fn_x2), out_sf.view(torch::kFloat8_e4m3fn)};
+}
+
+std::tuple<torch::Tensor, torch::Tensor> quantize_fp8_e4m3_from_fp32_cuda(
+    torch::Tensor input
+) {
+    int M = input.size(0);
+    int N = input.size(1);
+    auto opts = input.options();
+    auto out_scale = torch::zeros({M}, opts.dtype(torch::kFloat32));
+    auto out_fp8 = torch::zeros({M, N}, opts.dtype(torch::kUInt8));
+    quantize_fp8_e4m3_from_fp32_kernel<<<M, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        input.data_ptr<float>(), M, N,
+        out_scale.data_ptr<float>(), out_fp8.data_ptr<uint8_t>()
+    );
+    return {out_fp8.view(torch::kFloat8_e4m3fn), out_scale};
+}
+
+torch::Tensor dequant_fp8_e4m3_cuda(
+    torch::Tensor fp8_data, torch::Tensor scale_data
+) {
+    int M = fp8_data.size(0);
+    int N = fp8_data.size(1);
+    auto output = torch::zeros({M, N}, fp8_data.options().dtype(torch::kBFloat16));
+    dequant_fp8_e4m3_kernel<<<M, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        fp8_data.data_ptr<uint8_t>(), scale_data.data_ptr<float>(), M, N,
+        reinterpret_cast<__nv_bfloat16*>(output.data_ptr<at::BFloat16>())
+    );
+    return output;
+}
+
+torch::Tensor dequant_fp8_e4m3_selective_cuda(
+    torch::Tensor fp8_data, torch::Tensor scale_data, torch::Tensor indices
+) {
+    int K = indices.size(0);
+    int N = fp8_data.size(1);
+    TORCH_CHECK(indices.scalar_type() == torch::kInt32, "indices must be int32");
+    auto output = torch::zeros({K, N}, fp8_data.options().dtype(torch::kBFloat16));
+    dequant_fp8_e4m3_selective_kernel<<<K, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        fp8_data.data_ptr<uint8_t>(), scale_data.data_ptr<float>(),
+        indices.data_ptr<int32_t>(), K, N,
+        reinterpret_cast<__nv_bfloat16*>(output.data_ptr<at::BFloat16>())
+    );
+    return output;
+}
+
+void rope_fp32_cuda(
+    torch::Tensor x,           // (M, N) FP32 — modified in-place
+    torch::Tensor positions,   // (M,) int64
+    torch::Tensor cos_cache,   // (max_pos, rope_dim/2) FP32
+    torch::Tensor sin_cache,   // (max_pos, rope_dim/2) FP32
+    int64_t rope_dim,
+    bool inverse
+) {
+    int M = x.size(0);
+    int N = x.size(1);
+    TORCH_CHECK(x.scalar_type() == torch::kFloat32, "x must be float32");
+    rope_fp32_kernel<<<M, 256, 0, c10::cuda::getCurrentCUDAStream()>>>(
+        x.data_ptr<float>(),
+        cos_cache.data_ptr<float>(),
+        sin_cache.data_ptr<float>(),
+        positions.data_ptr<int64_t>(),
+        N, (int)rope_dim, inverse
+    );
+}
+
+PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
+    m.def("compute_amax_gsa_fp32", &compute_amax_gsa_fp32_cuda,
+          "Compute per-row gsa from FP32 input (GPU-only, no CPU sync)");
+    m.def("quantize_nvfp4_from_fp32", &quantize_nvfp4_from_fp32_cuda,
+          "Quantize FP32 → NVFP4 using gsa from GPU buffer");
+    m.def("quantize_fp8_e4m3_from_fp32", &quantize_fp8_e4m3_from_fp32_cuda,
+          "Quantize FP32 → FP8 E4M3 (for indexer keys)");
+    m.def("dequant_fp8_e4m3", &dequant_fp8_e4m3_cuda,
+          "Dequant FP8 E4M3 → BF16");
+    m.def("dequant_fp8_e4m3_selective", &dequant_fp8_e4m3_selective_cuda,
+          "Selective dequant FP8 E4M3 → BF16 (for CSA indexer gather)");
+    m.def("rope_fp32", &rope_fp32_cuda,
+          "FP32 GPT-J interleaved RoPE (for compressed KV)");
+}

dsv4/kernels/cuda/loader.py

@@ -7,9 +7,10 @@ being called on every kernel invocation (was ~100ms per call, called ~500x per t
 Usage:
     from dsv4.kernels.cuda.loader import get_cuda_module
     mod = get_cuda_module("fused_amax_quantize", ["fused_amax_quantize.cu"])
-    result = mod.fused_amax_quantize_nvfp4(x, divisor)
+    result = mod.quantize_nvfp4_from_buffer(x, divisor)
 """
 import os
+import time
 import hashlib
 import torch
 from torch.utils.cpp_extension import load
@@ -18,6 +19,34 @@ _KERNEL_DIR = os.path.dirname(os.path.abspath(__file__))
 _CACHE_DIR = os.path.join(_KERNEL_DIR, "_build_cache")
 _LOADED_MODULES = {}
 
+# Maximum age of a stale lock file before we remove it (seconds).
+# torch.utils.cpp_extension.load creates a lock file during compilation.
+# If the process is killed during compilation, the lock remains and the
+# next process spins forever polling it. This timeout prevents that.
+_STALE_LOCK_TIMEOUT_S = 600  # 10 minutes
+
+
+def _cleanup_stale_lock():
+    """Remove stale lock files from the build cache directory.
+    
+    torch.utils.cpp_extension.load creates a 'lock' file in the build
+    directory during compilation. If the compiling process is killed
+    (OOM, timeout, user interrupt), the lock file is never removed and
+    subsequent processes spin forever waiting for it.
+    
+    This function checks if a lock file exists and is older than
+    _STALE_LOCK_TIMEOUT_S. If so, it removes it.
+    """
+    lock_path = os.path.join(_CACHE_DIR, "lock")
+    if os.path.exists(lock_path):
+        try:
+            lock_age = time.time() - os.path.getmtime(lock_path)
+            if lock_age > _STALE_LOCK_TIMEOUT_S:
+                os.remove(lock_path)
+                print(f"[loader] Removed stale lock file (age={lock_age:.0f}s)", flush=True)
+        except OSError:
+            pass  # Lock was removed between exists() and remove()
+
 
 def get_cuda_module(name, sources, extra_cuda_cflags=None):
     """Load a CUDA kernel module, compiling once and caching forever.
@@ -33,6 +62,9 @@ def get_cuda_module(name, sources, extra_cuda_cflags=None):
     if name in _LOADED_MODULES:
         return _LOADED_MODULES[name]
     
+    # Clean up stale lock files from crashed previous compilations
+    _cleanup_stale_lock()
+    
     source_paths = [os.path.join(_KERNEL_DIR, s) for s in sources]
     
     # Build a cache key from source file contents + compile flags
@@ -65,13 +97,4 @@ def get_cuda_module(name, sources, extra_cuda_cflags=None):
     return mod
 
 
-def preload_all():
-    """Preload all CUDA kernels at startup (before the hot path)."""
-    # amax_gsa — computes gsa on GPU (no .item())
-    get_cuda_module("amax_gsa", ["amax_gsa.cu"])
-    # quantize-from-buffer — reads gsa from GPU buffer (no .item())
-    get_cuda_module("fused_amax_quantize", ["fused_amax_quantize.cu"])
-    # Standalone quantize (for when gsa is known, not hot path)
-    get_cuda_module("quantize_nvfp4", ["quantize_nvfp4.cu"])
-    # Sampler
-    get_cuda_module("sampler", ["sampler.cu"])
+

dsv4/kernels/cuda/mhc_sinkhorn.cu

@@ -11,6 +11,11 @@
  *   1. softmax(logits, dim=-1) + eps
  *   2. column normalize
  *   3. (t_max - 1) alternating row/col normalize
+ *
+ * NVFP4 PATH: This kernel operates on the B_l (comb) matrix which must be
+ * doubly-stochastic for residual bounding. The residual |X| growth to 500-700
+ * at L60 indicates B was NOT properly doubly-stochastic at runtime. This kernel
+ * ensures it. No fallback to Python. If this kernel fails, the pipeline fails.
  */
 
 #include <cuda.h>
@@ -20,9 +25,12 @@
 #include <torch/extension.h>
 #include <cmath>
 
-// One thread per (t, i, j) element of the (T, n, n) matrix
-// For T=1, n=4: 16 threads total — trivial parallelism
-// For larger T, each batch element is independent
+// Max supported n — DSV4 uses n=4. Increase if needed.
+#define MHC_MAX_N 16
+
+// One block per batch element. n*n threads per block (for n=4: 16 threads).
+// Shared memory holds the (n, n) matrix + row/col sums.
+// All loops use fixed-size arrays (no VLA — CUDA requirement).
 
 __global__ void mhc_sinkhorn_kernel(
     const float* __restrict__ logits,  // (T, n, n)
@@ -31,69 +39,71 @@ __global__ void mhc_sinkhorn_kernel(
 ) {
     int t = blockIdx.x;
     if (t >= T) return;
-    
-    // Each block handles one batch element
-    // Use shared memory for the (n, n) matrix — n=4 → 16 floats = 64 bytes
+
+    // Shared memory layout: M (n, n) | row_max (MHC_MAX_N) | row_sum (MHC_MAX_N) | col_sum (MHC_MAX_N)
     extern __shared__ float smem[];
-    float* M = smem;           // (n, n) — current matrix
-    float* row_sum = smem + n * n;  // (n,) — row sums
-    float* col_sum = row_sum + n;    // (n,) — col sums
-    
+    float* M = smem;                                       // n*n floats
+    float* row_max = smem + n * n;                         // MHC_MAX_N floats
+    float* row_sum_arr = row_max + MHC_MAX_N;              // MHC_MAX_N floats
+    float* col_sum_arr = row_sum_arr + MHC_MAX_N;          // MHC_MAX_N floats
+
     int i = threadIdx.x / n;
     int j = threadIdx.x % n;
-    
+
     // Step 1: softmax(logits, dim=-1) + eps
-    // Each row's softmax is computed by threads [i*0..i*(n-1)]
     if (i < n && j < n) {
         M[i * n + j] = logits[t * n * n + i * n + j];
     }
     __syncthreads();
-    
+
     // Compute row max for numerical stability
-    float row_max[n];  // n=4, so this fits in registers
-    for (int ri = 0; ri < n; ri++) {
-        float mx = -INFINITY;
-        for (int rj = 0; rj < n; rj++) {
-            mx = fmaxf(mx, M[ri * n + rj]);
-        }
-        row_max[ri] = mx;
-    }
-    
-    // Apply softmax + eps
-    for (int ri = 0; ri < n; ri++) {
-        float exp_sum = 0.0f;
-        for (int rj = 0; rj < n; rj++) {
-            M[ri * n + rj] = expf(M[ri * n + rj] - row_max[ri]);
-            exp_sum += M[ri * n + rj];
-        }
-        for (int rj = 0; rj < n; rj++) {
-            M[ri * n + rj] = M[ri * n + rj] / exp_sum + eps;
-        }
-    }
-    
-    // Step 2: column normalize
-    for (int cj = 0; cj < n; cj++) {
-        float cs = 0.0f;
-        for (int ci = 0; ci < n; ci++) cs += M[ci * n + cj];
-        for (int ci = 0; ci < n; ci++) M[ci * n + cj] = M[ci * n + cj] / (cs + eps);
-    }
-    
-    // Step 3: (t_max - 1) alternating row/col normalize
-    for (int iter = 0; iter < t_max - 1; iter++) {
-        // Row normalize
+    // Thread 0 does all the work (n is tiny — 4)
+    if (threadIdx.x == 0) {
         for (int ri = 0; ri < n; ri++) {
-            float rs = 0.0f;
-            for (int rj = 0; rj < n; rj++) rs += M[ri * n + rj];
-            for (int rj = 0; rj < n; rj++) M[ri * n + rj] = M[ri * n + rj] / (rs + eps);
+            float mx = -INFINITY;
+            for (int rj = 0; rj < n; rj++) {
+                mx = fmaxf(mx, M[ri * n + rj]);
+            }
+            row_max[ri] = mx;
         }
-        // Column normalize
+
+        // Apply softmax + eps
+        for (int ri = 0; ri < n; ri++) {
+            float exp_sum = 0.0f;
+            for (int rj = 0; rj < n; rj++) {
+                M[ri * n + rj] = expf(M[ri * n + rj] - row_max[ri]);
+                exp_sum += M[ri * n + rj];
+            }
+            for (int rj = 0; rj < n; rj++) {
+                M[ri * n + rj] = M[ri * n + rj] / exp_sum + eps;
+            }
+        }
+
+        // Step 2: column normalize
         for (int cj = 0; cj < n; cj++) {
             float cs = 0.0f;
             for (int ci = 0; ci < n; ci++) cs += M[ci * n + cj];
             for (int ci = 0; ci < n; ci++) M[ci * n + cj] = M[ci * n + cj] / (cs + eps);
         }
+
+        // Step 3: (t_max - 1) alternating row/col normalize
+        for (int iter = 0; iter < t_max - 1; iter++) {
+            // Row normalize
+            for (int ri = 0; ri < n; ri++) {
+                float rs = 0.0f;
+                for (int rj = 0; rj < n; rj++) rs += M[ri * n + rj];
+                for (int rj = 0; rj < n; rj++) M[ri * n + rj] = M[ri * n + rj] / (rs + eps);
+            }
+            // Column normalize
+            for (int cj = 0; cj < n; cj++) {
+                float cs = 0.0f;
+                for (int ci = 0; ci < n; ci++) cs += M[ci * n + cj];
+                for (int ci = 0; ci < n; ci++) M[ci * n + cj] = M[ci * n + cj] / (cs + eps);
+            }
+        }
     }
-    
+    __syncthreads();
+
     // Write output
     if (i < n && j < n) {
         out[t * n * n + i * n + j] = M[i * n + j];
@@ -109,63 +119,25 @@ torch::Tensor mhc_sinkhorn_cuda(
     int T = logits.size(0);
     int n = logits.size(1);
     TORCH_CHECK(logits.size(2) == n, "logits must be square");
+    TORCH_CHECK(n <= MHC_MAX_N, "n must be <= MHC_MAX_N (16)");
     TORCH_CHECK(logits.scalar_type() == torch::kFloat32, "logits must be FP32");
 
     auto out = torch::empty_like(logits);
-    
+
     // One block per batch element, n*n threads per block
     int threads = n * n;
-    int smem_size = n * n * sizeof(float) + 2 * n * sizeof(float);
-    
+    // Shared memory: M (n*n) + row_max + row_sum + col_sum (3 * MHC_MAX_N)
+    int smem_size = (n * n + 3 * MHC_MAX_N) * sizeof(float);
+
     mhc_sinkhorn_kernel<<<T, threads, smem_size, c10::cuda::getCurrentCUDAStream()>>>(
         logits.data_ptr<float>(),
         out.data_ptr<float>(),
         T, n, t_max, (float)eps
     );
-    
+
     return out;
 }
 
-// Also: fused mHC dynamic params kernel
-// Computes A_l, B_l, C_l from X_flat in a single kernel launch.
-// Currently done in ~8 separate ops in _dynamic_params().
-
-__global__ void mhc_dynamic_params_kernel(
-    const __nv_bfloat16* __restrict__ X_flat,  // (T, K) BF16
-    const float* __restrict__ W_stacked,       // (N_proj, K) FP32
-    int T, int K, int n_hc,
-    float alpha_pre, float alpha_post, float alpha_comb,
-    const float* __restrict__ S_pre,   // (1, n_hc)
-    const float* __restrict__ S_post,  // (n_hc,)
-    const float* __restrict__ S_comb,  // (n_hc*n_hc,)
-    float eps,
-    __nv_bfloat16* __restrict__ A_l_out,   // (T, n_hc) BF16
-    float* __restrict__ B_l_out,            // (T, n_hc, n_hc) FP32
-    __nv_bfloat16* __restrict__ C_l_out,   // (T, n_hc) BF16
-    int t_max_sinkhorn
-) {
-    // This kernel is more complex — it needs to do:
-    // 1. RMSNorm on X_flat
-    // 2. GEMM: (T, K) × (N_proj, K)^T → (T, N_proj)
-    // 3. Split + apply constraints
-    // 4. Sinkhorn on comb
-    //
-    // The GEMM at T=1, K=28672, N=24 is small enough to do per-thread
-    // with shared memory tiling.
-    //
-    // For now, just do the post-GEMM part (steps 3-4) as a fused kernel.
-    // The GEMM stays in Python/CuTeDSL.
-    // TODO: Full fusion in a future iteration.
-    
-    // This kernel handles post-GEMM: split, apply constraints, Sinkhorn
-    int t = blockIdx.x;
-    if (t >= T) return;
-    
-    // Thread handles one element of the output
-    // Not implementing the full GEMM here — that stays in Python
-    // This is a placeholder for the fused post-GEMM kernel
-}
-
 PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
-    m.def("mhc_sinkhorn", &mhc_sinkhorn_cuda, "Fused mHC Sinkhorn-Knopp projection");
+    m.def("mhc_sinkhorn", &mhc_sinkhorn_cuda, "Fused mHC Sinkhorn-Knopp projection (NO FALLBACK)");
 }

dsv4/kernels/cuda/rope_cuda.cu

@@ -0,0 +1,92 @@
+/*
+ * rope_cuda.cu
+ *
+ * Fused forward/inverse partial RoPE kernel for DeepSeek V4.
+ * GPT-J style (interleaved) RoPE on last rope_dim=64 dims of each head.
+ *
+ * Replaces 5-6 PyTorch kernel launches per RoPE call with 1 CUDA kernel.
+ * Total savings: ~1000 launches/token → 183 launches/token (~0.8ms at 2µs/launch).
+ *
+ * C API for ctypes loading (no ATen/pybind11).
+ */
+
+#include <cuda.h>
+#include <cuda_bf16.h>
+#include <cstdint>
+#include <cmath>
+
+__global__ void apply_rope_kernel(
+    __nv_bfloat16* __restrict__ x,           // (T, n_h, hd) — modified in-place
+    const int64_t* __restrict__ positions,    // (T,) — token positions
+    const float* __restrict__ cos_cache,      // (max_pos, rope_dim//2)
+    const float* __restrict__ sin_cache,      // (max_pos, rope_dim//2)
+    const int T,
+    const int n_h,
+    const int hd,
+    const int nope_dim,                       // hd - rope_dim = 448
+    const int rope_dim,                       // 64
+    const bool inverse                        // true = inverse RoPE
+) {
+    const int idx = blockIdx.x * blockDim.x + threadIdx.x;
+    const int half_rope = rope_dim / 2;
+    const int total_pairs = T * n_h * half_rope;
+    
+    if (idx >= total_pairs) return;
+    
+    const int pair_idx = idx % half_rope;
+    const int head_idx = (idx / half_rope) % n_h;
+    const int token_idx = idx / (half_rope * n_h);
+    
+    // Get position and cos/sin values
+    int64_t pos = positions[token_idx];
+    float c = cos_cache[pos * half_rope + pair_idx];
+    float s = sin_cache[pos * half_rope + pair_idx];
+    
+    // Compute pointer to the two elements of the pair
+    const int even_offset = token_idx * n_h * hd + head_idx * hd + nope_dim + 2 * pair_idx;
+    const int odd_offset = even_offset + 1;
+    
+    // Load BF16 values, convert to FP32
+    float x_even = __bfloat162float(x[even_offset]);
+    float x_odd = __bfloat162float(x[odd_offset]);
+    
+    // Apply rotation
+    float rot_even, rot_odd;
+    if (inverse) {
+        rot_even = x_even * c + x_odd * s;
+        rot_odd = -x_even * s + x_odd * c;
+    } else {
+        rot_even = x_even * c - x_odd * s;
+        rot_odd = x_even * s + x_odd * c;
+    }
+    
+    // Store back as BF16
+    x[even_offset] = __float2bfloat16(rot_even);
+    x[odd_offset] = __float2bfloat16(rot_odd);
+}
+
+// C API for ctypes
+extern "C" {
+
+void apply_rope_launch(
+    void* x_ptr,
+    const int64_t* positions_ptr,
+    const float* cos_ptr,
+    const float* sin_ptr,
+    int T, int n_h, int hd,
+    int nope_dim, int rope_dim,
+    bool inverse,
+    int grid_size, int block_size,
+    void* stream_ptr
+) {
+    cudaStream_t stream = static_cast<cudaStream_t>(stream_ptr);
+    apply_rope_kernel<<<grid_size, block_size, 0, stream>>>(
+        static_cast<__nv_bfloat16*>(x_ptr),
+        positions_ptr,
+        cos_ptr,
+        sin_ptr,
+        T, n_h, hd, nope_dim, rope_dim, inverse
+    );
+}
+
+}  // extern "C"

dsv4/kernels/gemm/fused_swiglu.py

@@ -1285,6 +1285,10 @@ class FusedSwiGLUScaledGroupedGemmKernel:
         # ── Optional: NVFP4 per-expert global scales ──
         global_scale_a: Optional[cute.Tensor],
         global_scale_b: Optional[cute.Tensor],
+        # ── Fused SwiGLU epilogue outputs (replaces out when fused_swiglu=True) ──
+        fp4_out: Optional[cute.Tensor] = None,
+        sf_out: Optional[cute.Tensor] = None,
+        l2_global_scale: Optional[cute.Tensor] = None,
     ):
         """
         GPU device kernel for MoE Scaled Grouped GEMM with block scaling.
@@ -2133,7 +2137,7 @@ class FusedSwiGLUScaledGroupedGemmKernel:
                 if cutlass.const_expr(self.fused_swiglu):
                     silu_gate_buf = cute.make_rmem_tensor(tiled_copy_r2s.retile(tTR_rAcc).shape, self.c_dtype)
 
-                for subtile_idx in cutlass.range(subtile_cnt):
+                for subtile_idx in cutlass.range(subtile_cnt, unroll=1):  # unroll=1: SwiGLU + clamp needs cute.arch.fmin/fmax (impure for vectorizer)
                     real_subtile_idx = subtile_idx
                     if cutlass.const_expr(self.overlapping_accum):
                         if reverse_subtile:
@@ -2192,10 +2196,11 @@ class FusedSwiGLUScaledGroupedGemmKernel:
                             neg_acc = acc_vec * cutlass.Float32(-1.0)
                             exp_neg = cute.exp(neg_acc)
                             sigmoid = cutlass.Float32(1.0) / (cutlass.Float32(1.0) + exp_neg)
-                            silu_result = acc_vec * sigmoid
-                            # Paper §4.2.3: gate component capped at swiglu_limit
+                            # Paper §4.2.3: clamp raw gate BEFORE SiLU, not after
                             if cutlass.const_expr(self.swiglu_limit > 0.0):
-                                silu_result = cute.math.fmin(silu_result, cutlass.Float32(self.swiglu_limit))
+                                limit = cutlass.Float32(self.swiglu_limit)
+                                acc_vec = cute.where(acc_vec > limit, limit, acc_vec)
+                            silu_result = acc_vec * sigmoid
                             silu_result = silu_result.to(self.c_dtype)
                             silu_gate_buf.store(silu_result)
                             # Keep acc_vec in BF16 (same type as the up branch)
@@ -2203,7 +2208,8 @@ class FusedSwiGLUScaledGroupedGemmKernel:
                         if is_up:
                             # Paper §4.2.3: linear component clamped to [-swiglu_limit, swiglu_limit]
                             if cutlass.const_expr(self.swiglu_limit > 0.0):
-                                acc_vec = cute.math.fmin(cute.math.fmax(acc_vec, cutlass.Float32(-self.swiglu_limit)), cutlass.Float32(self.swiglu_limit))
+                                limit = cutlass.Float32(self.swiglu_limit)
+                                acc_vec = cute.where(acc_vec > limit, limit, cute.where(acc_vec < -limit, -limit, acc_vec))
                             # SwiGLU: silu(gate) * up
                             gate_vals = silu_gate_buf.load()
                             swiglu_result = (gate_vals * acc_vec.to(self.c_dtype))

dsv4/kernels/indexer/__init__.py

@@ -1,63 +1,5 @@
 """CSA indexer — Python API bridge.
 
-Wraps the CUDA indexer score+topk kernel with the interface that
-AttentionSubBlock expects.
-
-The indexer (paper §2.3.5, eq. 16) scores each query against
-compressed blocks via weighted ReLU MQA logits, then selects
-top-k blocks for sparse attention.
-
-Currently uses scalar FP32 CUDA cores after FP4 dequant.
-The FP4 tensor-core path (Stage F / E7) is a future optimization.
+See dsv4/kernels/cuda/indexer_score_topk.cu for the live CUDA kernel.
+The live inference path uses the inline indexer in single_shot_inference.py.
 """
-import torch
-from typing import TYPE_CHECKING
-
-if TYPE_CHECKING:
-    from dsv4.cache.handle import LayerCacheHandle
-
-
-def compute_index_scores_topk(
-    q_indexer: torch.Tensor,       # (T, n_I_h * c_I) BF16 — indexer query
-    w_indexer: torch.Tensor,       # (T, n_I_h) FP32 — per-head weights
-    cache: "LayerCacheHandle",     # provides FP4 indexer keys
-    top_k: int = 512,              # number of blocks to select
-) -> torch.Tensor:                 # (T, top_k) int64 — selected block indices
-    """CSA: score compressed entries and select top-k blocks.
-
-    Uses the CUDA indexer_score_topk kernel (raw CUDA, FP4 dequant + scalar
-    score + min-heap top-k). Returns entry indices for gather_compressed_kv.
-    """
-    from dsv4.kernels.indexer.score_topk import run_indexer_score_topk
-
-    # Read the indexer view from the cache
-    indexer_view = cache.read_indexer_view()
-
-    # c_I is the indexer head dimension from schema
-    n_I_h = cache.schema.indexer_entries_per_block  # This is entries, not heads
-    c_I = cache.schema.indexer_head_dim  # 128
-
-    # n_I_h (number of indexer heads) comes from the config, not the schema.
-    # We need to pass it through the handle or compute it.
-    # For DSV4: n_I_h = 64 (same for Flash and Pro)
-    # TODO: add indexer_num_heads to schema or handle
-    n_I_h = 64  # config.indexer_num_heads, hardcoded for now
-
-    # Reshape q_indexer from (T, n_I_h * c_I) to (T, n_I_h * c_I) — already flat
-    # The kernel expects q_I: [T, n_I_h * c_I] BF16
-    # and w_h: [T, n_I_h] FP32
-
-    entries_per_block = cache.schema.entries_per_block
-
-    indices = run_indexer_score_topk(
-        q_I=q_indexer,
-        w_h=w_indexer.float() if w_indexer.dtype != torch.float32 else w_indexer,
-        indexer_view=indexer_view,
-        num_heads=n_I_h,
-        head_dim=c_I,
-        top_k=top_k,
-        entries_per_block=entries_per_block,
-    )
-
-    # indices: (T, top_k) int32 → convert to int64 for gather_compressed_kv
-    return indices.to(torch.int64)

dsv4/kernels/indexer/gather_kv.cu

@@ -1,106 +0,0 @@
-// gather_kv.cu — Gather selected compressed entries into a dense BF16 tile.
-//
-// One CTA per (query token, key_group). Each CTA handles a contiguous
-// group of top-k entries for one query token. Reads from the FP8/BF16
-// split paged pool via block_table resolution, dequantizes FP8 → BF16,
-// concatenates the RoPE half, writes to the dense output.
-//
-// Pure bandwidth-bound kernel — no MMA, just load-multiply-store.
-// The output [T, top_k, head_dim] BF16 tile is what the FMHA kernel
-// consumes. Sparsity is hidden in the gather; FMHA sees dense tiles.
-
-#include <cuda.h>
-#include <cuda_fp8.h>
-#include <cuda_bf16.h>
-#include <torch/extension.h>
-#include <c10/cuda/CUDAException.h>
-
-
-__global__ void gather_kv_kernel(
-    // Inputs
-    const uint8_t* __restrict__ entries_fp8,        // [num_blocks, epb, fp8_dim]
-    const __nv_bfloat16* __restrict__ entries_rope, // [num_blocks, epb, rope_dim]
-    const float* __restrict__ inv_scale,            // [num_blocks, epb]
-    const int32_t* __restrict__ topk_indices,       // [T, top_k] — compressed entry indices
-    const int32_t* __restrict__ block_table,         // [T, max_logical_blocks]
-    // Output
-    __nv_bfloat16* __restrict__ output,              // [T, top_k, head_dim] BF16
-    // Geometry
-    int T, int top_k, int entries_per_block,
-    int head_dim, int rope_dim, int max_logical_blocks
-) {
-    int fp8_dim = head_dim - rope_dim;
-
-    // Each CTA handles one (query_token, topk_entry) pair.
-    int flat_idx = blockIdx.x;
-    int t = flat_idx / top_k;
-    int k = flat_idx % top_k;
-    if (t >= T) return;
-
-    // Resolve which compressed entry to gather.
-    int comp_idx = topk_indices[t * top_k + k];
-    if (comp_idx < 0) {
-        // Invalid entry — zero fill.
-        for (int d = threadIdx.x; d < head_dim; d += blockDim.x) {
-            output[t * top_k * head_dim + k * head_dim + d] = __float2bfloat16(0.0f);
-        }
-        return;
-    }
-
-    int logical_block = comp_idx / entries_per_block;
-    int slot_in_block = comp_idx % entries_per_block;
-    int phys_block = block_table[t * max_logical_blocks + logical_block];
-
-    int block_entry = phys_block * entries_per_block + slot_in_block;
-
-    // Dequantize and write FP8 half.
-    float s = inv_scale[block_entry];
-    for (int d = threadIdx.x; d < fp8_dim; d += blockDim.x) {
-        uint8_t raw = entries_fp8[block_entry * fp8_dim + d];
-        __nv_fp8_e4m3 fp8_val;
-        fp8_val.__x = raw;
-        float dequant = (float)fp8_val * s;
-        output[t * top_k * head_dim + k * head_dim + d] = __float2bfloat16(dequant);
-    }
-
-    // Copy BF16 RoPE half.
-    for (int d = threadIdx.x; d < rope_dim; d += blockDim.x) {
-        output[t * top_k * head_dim + k * head_dim + fp8_dim + d]
-            = entries_rope[block_entry * rope_dim + d];
-    }
-}
-
-
-void gather_kv_cuda(
-    torch::Tensor entries_fp8,
-    torch::Tensor entries_rope,
-    torch::Tensor inv_scale,
-    torch::Tensor topk_indices,
-    torch::Tensor block_table,
-    torch::Tensor output,
-    int64_t entries_per_block, int64_t rope_dim
-) {
-    int T = topk_indices.size(0);
-    int top_k = topk_indices.size(1);
-    int head_dim = entries_fp8.size(2) + entries_rope.size(2);
-    int max_logical_blocks = block_table.size(1);
-
-    int total_entries = T * top_k;
-    int threads = 128;
-    gather_kv_kernel<<<total_entries, threads>>>(
-        entries_fp8.data_ptr<uint8_t>(),
-        reinterpret_cast<const __nv_bfloat16*>(entries_rope.data_ptr<at::BFloat16>()),
-        inv_scale.data_ptr<float>(),
-        topk_indices.data_ptr<int32_t>(),
-        block_table.data_ptr<int32_t>(),
-        reinterpret_cast<__nv_bfloat16*>(output.data_ptr<at::BFloat16>()),
-        T, top_k, (int)entries_per_block,
-        (int)head_dim, (int)rope_dim, max_logical_blocks
-    );
-    C10_CUDA_CHECK(cudaGetLastError());
-}
-
-
-PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
-    m.def("gather_kv", &gather_kv_cuda, "Gather KV entries into dense tile");
-}

dsv4/kernels/indexer/indexer_score_topk.cu

@@ -1,292 +0,0 @@
-// indexer_score_topk.cu — Fused score + ReLU + weighted-sum + top-k kernel.
-//
-// CSA Lightning Indexer (paper §2.3.1, eq. 16):
-//   I[t,s] = Σ_h w_h[t,h] · ReLU(q_I[t,h] · K^IComp[s,h])
-//   Selected = TopK(I[t,:], k=csa_top_k)
-//
-// One CTA per query token. Streams indexer keys from the paged pool,
-// computes per-head dot products in FP32, ReLU, weighted sum, heap top-k.
-//
-// Phase 1 (this file): FP32 dot products via standard CUDA ops.
-// Phase 2 (future): swap to FP4 tcgen05 MMA for production throughput.
-// The FP32 path is correct and used for testing; the FP4 path is the
-// performance optimization on a known-correct base.
-//
-// Indexer keys are stored in the paged pool as FP4 (NVFP4 scheme).
-// This kernel dequantizes them to FP32 before the dot product.
-// The FP4 tcgen05 version will avoid this dequant and do FP4 MMA directly.
-
-#include <cuda.h>
-#include <cuda_bf16.h>
-#include <cuda_fp8.h>
-#include <torch/extension.h>
-#include <c10/cuda/CUDAException.h>
-
-#include <limits>
-
-// ---- FP4 dequantization (NVFP4 E2M1 scheme) ----
-// FP4 E2M1 format (1 sign + 2 exponent + 1 mantissa):
-//   nibble = s|e1|e0|m0
-//   value  = (-1)^s × 2^(e-1) × (1 + m×0.5)   for e > 0
-//          = 0                                   for e = 0, m = 0
-//          = ±6                                   for e = 3, m = 1 (largest finite)
-//
-// Magnitude lookup (bits[2:0] → value):
-//   0b000=0, 0b001=0.5, 0b010=1, 0b011=1.5, 0b100=2, 0b101=3, 0b110=4, 0b111=6
-//
-// Scale is per-16-element group (FP8 E4M3) × global scale (FP32).
-// Dequant: val = fp4_magnitude × group_scale × global_scale
-
-// Must match Python: dsv4/ops/quantize.py E2M1_MAGNITUDES
-__constant__ float E2M1_LUT[8] = {0.0f, 0.5f, 1.0f, 1.5f, 2.0f, 3.0f, 4.0f, 6.0f};
-
-__device__ __forceinline__ float dequant_fp4_scalar(
-    uint8_t packed, int lane,  // lane 0 = low nibble, lane 1 = high nibble
-    float group_scale, float global_scale
-) {
-    int nibble = (lane == 0) ? (packed & 0x0F) : (packed >> 4);
-    int sign = (nibble >> 3) & 1;
-    int mag_bits = nibble & 0x07;
-
-    float magnitude = E2M1_LUT[mag_bits];
-    float val = magnitude * group_scale * global_scale;
-    return sign ? -val : val;
-}
-
-// ---- Min-heap for top-k ----
-// Heap of (score, block_id) pairs. Root = smallest score.
-// Insert: if new score > root, replace root and sift down.
-// After all inserts, the heap contains the top-k entries.
-
-__device__ __forceinline__ void heap_insert(
-    float* __restrict__ heap_scores,
-    int32_t* __restrict__ heap_blocks,
-    float score, int32_t block_id,
-    int k
-) {
-    if (score <= heap_scores[0]) return;  // doesn't beat min
-    heap_scores[0] = score;
-    heap_blocks[0] = block_id;
-    // Sift down
-    int root = 0;
-    while (root < (k >> 1)) {
-        int left = 2 * root + 1;
-        int right = 2 * root + 2;
-        int smallest = root;
-        if (left < k && (heap_scores[left] < heap_scores[smallest] ||
-                         (heap_scores[left] == heap_scores[smallest] &&
-                          heap_blocks[left] > heap_blocks[smallest]))) {
-            smallest = left;
-        }
-        if (right < k && (heap_scores[right] < heap_scores[smallest] ||
-                          (heap_scores[right] == heap_scores[smallest] &&
-                           heap_blocks[right] > heap_blocks[smallest]))) {
-            smallest = right;
-        }
-        if (smallest == root) break;
-        float ts = heap_scores[root]; int32_t ti = heap_blocks[root];
-        heap_scores[root] = heap_scores[smallest]; heap_blocks[root] = heap_blocks[smallest];
-        heap_scores[smallest] = ts; heap_blocks[smallest] = ti;
-        root = smallest;
-    }
-}
-
-// ===========================================================================
-// Main kernel
-// ===========================================================================
-
-__global__ void indexer_score_topk_fp32_kernel(
-    // Query inputs (FP32 — dequantized from FP4 in the launcher or here)
-    const float* __restrict__ q_I,         // [T, n_heads, head_dim] FP32
-    const float* __restrict__ w_h,         // [T, n_heads] FP32
-    // Indexer keys from cache (FP4 packed)
-    const uint8_t* __restrict__ keys_fp4,  // [num_phys_blocks, epb, hd/2]
-    const uint8_t* __restrict__ key_scale, // [num_phys_blocks, epb, hd/16] FP8 E4M3
-    const float* __restrict__ key_gscale,  // [num_phys_blocks] FP32
-    // Block table
-    const int32_t* __restrict__ block_table, // [T, max_logical_blocks]
-    const int32_t* __restrict__ valid_lens,   // [T] int32 — total valid entries per query
-    // Output
-    int32_t* __restrict__ topk_indices,     // [T, top_k] int32
-    // Geometry
-    int n_heads, int head_dim, int top_k,
-    int entries_per_block, int max_logical_blocks
-) {
-    int t = blockIdx.x;  // one CTA per query token
-    if (t >= gridDim.x) return;
-
-    int tid = threadIdx.x;
-    int n_threads = blockDim.x;
-    int num_valid = valid_lens[t];
-    int n_groups = head_dim / 16;  // FP4 group count per entry
-    int n_bytes = head_dim / 2;    // FP4 packed bytes per entry
-
-    // ---- Load w_h[t, :] into shared memory ----
-    extern __shared__ char smem[];
-    float* smem_w = reinterpret_cast<float*>(smem);
-    float* smem_heap_scores = smem_w + n_heads;
-    int32_t* smem_heap_blocks = reinterpret_cast<int32_t*>(smem_heap_scores + top_k);
-
-    // Load w_h
-    for (int h = tid; h < n_heads; h += n_threads) {
-        smem_w[h] = w_h[t * n_heads + h];
-    }
-
-    // Init heap to -inf
-    for (int i = tid; i < top_k; i += n_threads) {
-        smem_heap_scores[i] = -INFINITY;
-        smem_heap_blocks[i] = -1;
-    }
-    __syncthreads();
-
-    // ---- Stream over all valid compressed entries ----
-    // Each entry is a candidate block s.
-    // I[t,s] = Σ_h w_h[h] * ReLU( <q_I[t,h,:], K[s,h,:]> )
-    //
-    // We parallelize over entries: each thread handles a subset of entries,
-    // computes the full score, then inserts into the shared heap.
-    // For S=250K and 128 threads, each thread handles ~2K entries.
-
-    for (int s = tid; s < num_valid; s += n_threads) {
-        // Resolve physical location of entry s
-        int logical_block = s / entries_per_block;
-        int slot_in_block = s % entries_per_block;
-        int phys_block = block_table[t * max_logical_blocks + logical_block];
-        int block_entry = phys_block * entries_per_block + slot_in_block;
-
-        float global_s = key_gscale[phys_block];
-
-        // Compute score = Σ_h w_h[h] * ReLU( <q_I[h,:], K[s,h,:]> )
-        float score = 0.0f;
-
-        for (int h = 0; h < n_heads; h++) {
-            float dot = 0.0f;
-            // Dequantize FP4 key and compute dot product with q_I
-            for (int g = 0; g < n_groups; g++) {
-                // Read group scale (FP8 E4M3)
-                uint8_t raw_scale = key_scale[block_entry * n_groups + g];
-                __nv_fp8_e4m3 fp8_s;
-                fp8_s.__x = raw_scale;
-                float group_s = (float)fp8_s * global_s;
-
-                // Read 8 packed bytes = 16 FP4 values
-                for (int b = 0; b < 8; b++) {
-                    uint8_t packed = keys_fp4[block_entry * n_bytes + g * 8 + b];
-                    float v0 = dequant_fp4_scalar(packed, 0, group_s, 1.0f);
-                    float v1 = dequant_fp4_scalar(packed, 1, group_s, 1.0f);
-                    // q_I values (FP32, already dequantized)
-                    int d0 = g * 16 + 2 * b;
-                    int d1 = d0 + 1;
-                    dot += v0 * q_I[t * n_heads * head_dim + h * head_dim + d0];
-                    dot += v1 * q_I[t * n_heads * head_dim + h * head_dim + d1];
-                }
-            }
-            // ReLU + weighted sum
-            if (dot > 0.0f) {
-                score += smem_w[h] * dot;
-            }
-        }
-
-        // Insert into heap
-        // Must be serialized — use a critical section per CTA.
-        // For correctness, one thread at a time inserts.
-        // This is the simple approach; a lock-free heap is an optimization.
-        if (score > -INFINITY) {
-            // Use a simple spin-lock approach: thread 0 does all inserts.
-            // Each thread writes its (score, s) to a staging area.
-            // Then thread 0 iterates through the staging area.
-            // For now, just serialize via atomicMax on a flag.
-            // Actually, since each thread has its own set of entries (strided),
-            // and the heap is shared, we need mutual exclusion.
-            // Simplest: one thread handles all its entries, then next thread.
-            // We do this by having each thread wait for its turn.
-            // For now: all threads write to a SMEM buffer, then one thread
-            // processes the buffer.
-
-            // Write to a shared staging buffer (one per thread, fixed size)
-            // Actually, the simplest correct approach: each thread maintains
-            // its own top-k in registers, then we merge at the end.
-            // But register top-k for k=1024 is too large.
-            //
-            // Practical approach: use atomicCAS on a SMEM lock.
-            // Only one thread inserts at a time.
-            __shared__ int heap_lock;
-            if (tid == 0) heap_lock = 0;
-            __syncthreads();
-
-            while (atomicCAS(&heap_lock, 0, 1) != 0) {}  // acquire
-            heap_insert(smem_heap_scores, smem_heap_blocks, score, s, top_k);
-            atomicExch(&heap_lock, 0);  // release
-        }
-    }
-
-    __syncthreads();
-
-    // ---- Write top-k indices to global memory ----
-    // Sort heap by score descending for deterministic output.
-    // Simple selection sort on the small heap (top_k <= 1024).
-    if (tid == 0) {
-        for (int i = 0; i < top_k; i++) {
-            // Find max among remaining
-            int best = i;
-            for (int j = i + 1; j < top_k; j++) {
-                if (smem_heap_scores[j] > smem_heap_scores[best] ||
-                    (smem_heap_scores[j] == smem_heap_scores[best] &&
-                     smem_heap_blocks[j] < smem_heap_blocks[best])) {
-                    best = j;
-                }
-            }
-            if (best != i) {
-                float ts = smem_heap_scores[i]; int32_t ti = smem_heap_blocks[i];
-                smem_heap_scores[i] = smem_heap_scores[best]; smem_heap_blocks[i] = smem_heap_blocks[best];
-                smem_heap_scores[best] = ts; smem_heap_blocks[best] = ti;
-            }
-            topk_indices[t * top_k + i] = smem_heap_blocks[i];
-        }
-    }
-}
-
-
-// ===========================================================================
-// PyTorch binding
-// ===========================================================================
-
-void indexer_score_topk_fp32_cuda(
-    torch::Tensor q_I,          // [T, n_heads, head_dim] FP32
-    torch::Tensor w_h,          // [T, n_heads] FP32
-    torch::Tensor keys_fp4,     // [num_blocks, epb, hd/2] uint8
-    torch::Tensor key_scale,    // [num_blocks, epb, hd/16] uint8 (FP8 E4M3)
-    torch::Tensor key_gscale,   // [num_blocks] FP32
-    torch::Tensor block_table,  // [T, max_logical_blocks] int32
-    torch::Tensor valid_lens,   // [T] int32
-    torch::Tensor topk_indices, // [T, top_k] int32 (output)
-    int64_t n_heads, int64_t head_dim, int64_t top_k,
-    int64_t entries_per_block
-) {
-    int T = q_I.size(0);
-    int max_logical_blocks = block_table.size(1);
-    int threads = 128;
-
-    // SMEM: w_h (n_heads floats) + heap_scores (top_k floats) + heap_blocks (top_k ints)
-    int smem_bytes = n_heads * sizeof(float) + top_k * sizeof(float) + top_k * sizeof(int32_t);
-
-    indexer_score_topk_fp32_kernel<<<T, threads, smem_bytes>>>(
-        q_I.data_ptr<float>(),
-        w_h.data_ptr<float>(),
-        keys_fp4.data_ptr<uint8_t>(),
-        key_scale.data_ptr<uint8_t>(),
-        key_gscale.data_ptr<float>(),
-        block_table.data_ptr<int32_t>(),
-        valid_lens.data_ptr<int32_t>(),
-        topk_indices.data_ptr<int32_t>(),
-        (int)n_heads, (int)head_dim, (int)top_k,
-        (int)entries_per_block, max_logical_blocks
-    );
-    C10_CUDA_CHECK(cudaGetLastError());
-}
-
-
-PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
-    m.def("indexer_score_topk_fp32", &indexer_score_topk_fp32_cuda,
-          "Indexer score + top-k (FP32 dot products)");
-}

dsv4/layers/linear.py

@@ -113,7 +113,7 @@ class Nvfp4Linear:
         ).view(torch.float4_e2m1fn_x2)
 
         self._expert_offsets_buf = torch.zeros(1, dtype=torch.int32, device=self.device)
-        self._gsa_buf = torch.zeros(1, dtype=torch.float32, device=self.device)
+        self._gsa_buf = torch.full((1,), self._activation_global_scale, dtype=torch.float32, device=self.device)
 
     def _ensure_initialized(self):
         if self._mat_b is None:
@@ -176,8 +176,13 @@ class Nvfp4Linear:
             x_fp4, x_sf, gsa_gpu = quantize_nvfp4_gpu_fused(hidden_states)
             self._gsa_buf.copy_(gsa_gpu[:1].reshape(1))  # GPU → GPU, no sync
         else:
+            # P2 FIX: No per-call fill_(). The _gsa_buf already has the correct
+            # value — set either during initialization (via _ensure_buffer_size)
+            # or by the first GPU compute when _use_runtime_gsa was True.
+            # Old path: self._gsa_buf.fill_(self._activation_global_scale)
+            #   — H2D transfer every call (~5µs each × 244 calls = ~1.2ms/token).
+            # New path: zero H2D transfers on the hot path.
             from dsv4.ops.quantize import quantize_nvfp4_gpu
-            self._gsa_buf.fill_(self._activation_global_scale)
             x_fp4, x_sf = quantize_nvfp4_gpu(hidden_states, self._activation_global_scale)
 
         # Scatter x_fp4 into padded buffer
@@ -208,5 +213,65 @@ class Nvfp4Linear:
 
         return out[:num_tokens]
 
+    def run_from_quantized(self, quant: 'QuantizedActivation') -> torch.Tensor:
+        """Run GEMM with pre-quantized activation (skip quantize step).
+        
+        Used when the input has already been quantized by a fused
+        RMSNorm+quantize kernel. Saves 2 kernel launches per call.
+        
+        Args:
+            quant: QuantizedActivation with x_fp4, x_sf, gsa
+        """
+        from dsv4.ops.quantize import QuantizedActivation
+        assert isinstance(quant, QuantizedActivation)
+        
+        self._ensure_initialized()
+        num_tokens = quant.num_tokens
+        padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+        self._ensure_buffer_size(num_tokens)
+
+        # Scatter pre-quantized x_fp4 into padded buffer
+        padded_x_fp4 = self._padded_x_fp4_buf
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[:quant.x_fp4.shape[0]] = quant.x_fp4.view(torch.uint8)
+
+        # Assemble A-side scales from pre-quantized sf
+        scale_a = self._assemble_scales_single_group(quant.x_sf)
+
+        # Expert offsets
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.fill_(padded_rows)
+
+        # Global scales — the CuTeDSL NVFP4 GEMM expects global_scale_a as a
+        # per-expert scalar (shape (1,) for single linear). The fused
+        # rmsnorm/mhc kernels compute per-row gsa, but we must reduce to a
+        # scalar. Using max reduction: gsa = max(per_row_gsa) ensures no
+        # E4M3 block scale overflow (rows with smaller magnitude get slightly
+        # less FP4 precision, but all rows stay within E4M3 range).
+        #
+        # For M=1 decode: per-row gsa is already scalar, no reduction needed.
+        # For M>1 prefill: reduce per-row gsa to a single scalar (max).
+        if quant.gsa.shape[0] == 1:
+            gsa = quant.gsa[:1].reshape(1)  # Already scalar
+        else:
+            # Reduce per-row gsa to scalar (max) for GEMM compatibility.
+            # Per-row gsa is mathematically more precise, but the GEMM only
+            # supports a single global scale per expert.
+            gsa = quant.gsa.max().reshape(1)
+        self._gsa_buf.copy_(gsa)
+
+        # Run GEMM
+        out = run_nvfp4_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._mat_b,
+            scale_a=scale_a,
+            scale_b=self._scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=self._gsa_buf,
+            global_scale_b=self._gsb,
+        )
+
+        return out[:num_tokens]
+
     def __call__(self, hidden_states: torch.Tensor) -> torch.Tensor:
         return self.run(hidden_states)

dsv4/layers/mhc.py

@@ -91,25 +91,12 @@ def sinkhorn_knopp(
       3. column-normalize
       4. (t_max - 1) alternating row/col normalizations
     
-    Uses fused CUDA kernel when available (1 launch instead of 38).
-    Falls back to Python for correctness verification.
+    NO PYTHON FALLBACK. If the CUDA kernel fails, the pipeline dies.
+    The kernel MUST compile and run correctly. Period.
     """
-    # Try fused CUDA kernel first
-    try:
-        from dsv4.kernels.cuda.loader import get_cuda_module
-        mod = get_cuda_module("mhc_sinkhorn", ["mhc_sinkhorn.cu"])
-        return mod.mhc_sinkhorn(logits.float(), t_max, eps)
-    except Exception as e:
-        import sys; print(f"mhc_sinkhorn CUDA kernel failed: {e}, falling back to Python", file=sys.stderr, flush=True)
-        pass  # Fall back to Python
-    
-    # Python fallback
-    M = torch.softmax(logits, dim=-1) + eps               # (T, n, n)
-    M = M / (M.sum(dim=-2, keepdim=True) + eps)            # T_c (col)
-    for _ in range(t_max - 1):
-        M = M / (M.sum(dim=-1, keepdim=True) + eps)        # T_r (row)
-        M = M / (M.sum(dim=-2, keepdim=True) + eps)        # T_c (col)
-    return M
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("mhc_sinkhorn", ["mhc_sinkhorn.cu"])
+    return mod.mhc_sinkhorn(logits.float(), t_max, eps)
 
 
 # ---------------------------------------------------------------------------

dsv4/layers/moe.py

@@ -104,6 +104,10 @@ class Nvfp4MoE:
         """Set the swiglu_limit for activation clamping."""
         self._swiglu_limit = limit
 
+    def set_fused_swiglu(self, enabled: bool):
+        """Enable fused L1 GEMM + SwiGLU kernel (saves 240+ BF16 kernel launches per token)."""
+        self._fused_swiglu = enabled
+
     def _fill_token_indices(self):
         """Fill _token_indices with [0,0,..0, 1,1,..1, ...] (each token repeated top_k times).
         
@@ -508,10 +512,11 @@ class Nvfp4MoE:
             l1_deil = deinterleave_l1_weights(l1_out_real.unsqueeze(0).contiguous())[0]
             gate = l1_deil[:, :self.intermediate_size]
             up = l1_deil[:, self.intermediate_size:]
-            gate_silu = torch.nn.functional.silu(gate)
+            # Paper §4.2.3: clamp raw gate BEFORE SiLU, not after
             if self._swiglu_limit is not None:
-                gate_silu = gate_silu.clamp(max=self._swiglu_limit)
+                gate = gate.clamp(max=self._swiglu_limit)
                 up = up.clamp(min=-self._swiglu_limit, max=self._swiglu_limit)
+            gate_silu = torch.nn.functional.silu(gate)
             activated = gate_silu * up
             _, _, l2_gs = quantize_to_nvfp4(activated)
         
@@ -647,10 +652,11 @@ class Nvfp4MoE:
             l1_deil = deinterleave_l1_weights(l1_out_real.unsqueeze(0).contiguous())[0]
             gate = l1_deil[:, :self.intermediate_size]
             up = l1_deil[:, self.intermediate_size:]
-            gate_silu = torch.nn.functional.silu(gate)
+            # Paper §4.2.3: clamp raw gate BEFORE SiLU, not after
             if self._swiglu_limit is not None:
-                gate_silu = gate_silu.clamp(max=self._swiglu_limit)
+                gate = gate.clamp(max=self._swiglu_limit)
                 up = up.clamp(min=-self._swiglu_limit, max=self._swiglu_limit)
+            gate_silu = torch.nn.functional.silu(gate)
             activated = gate_silu * up
 
         # Compute runtime gsa for L2 from activated output (non-fused path)

dsv4/layers/shared_expert.py

@@ -26,10 +26,14 @@ from dsv4.ops.quantize import (
 )
 from dsv4.ops.layouts import (
     make_b_k_major,
+    interleave_l1_weights,
+    deinterleave_l1_weights,
 )
 from dsv4.ops.gemm_runner import (
     run_nvfp4_grouped_gemm,
+    run_fused_swiglu_grouped_gemm,
 )
+from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
 from dsv4.kernels.gemm.grouped import (
     ceil_div as cutedsl_ceil_div,
     pad_and_swizzle_single,
@@ -62,6 +66,7 @@ class Nvfp4SharedExpert:
         self.max_num_tokens = max_num_tokens
         self.device = device
         self.swiglu_limit = swiglu_limit
+        self._fused_swiglu = False  # Set via set_fused_swiglu()
 
         # Weights (set after construction, then call finalize_weights)
         self.l1_fp4 = None
@@ -99,6 +104,10 @@ class Nvfp4SharedExpert:
     def set_swiglu_limit(self, limit: float):
         self.swiglu_limit = limit
 
+    def set_fused_swiglu(self, enabled: bool):
+        """Enable fused L1 GEMM + SwiGLU kernel (1-group variant of MoE fused kernel)."""
+        self._fused_swiglu = enabled
+
     def finalize_weights(self):
         """Process weights for CuTeDSL GEMM. Must be called after setting l1/l2 weights."""
         # Convert uint8 checkpoint weights to float4_e2m1fn_x2 view
@@ -107,6 +116,11 @@ class Nvfp4SharedExpert:
         # Checkpoint weight is (N_packed, K_packed), make_b_k_major expects (E, K_packed, N_packed)
         l1_stacked = torch.stack(l1_view).permute(0, 2, 1).contiguous()
         l2_stacked = torch.stack(l2_view).permute(0, 2, 1).contiguous()
+        # P1: Interleave L1 gate/up weights for fused SwiGLU kernel compatibility.
+        # The fused kernel's SwiGLU epilogue expects granularity-8 interleaved gate/up.
+        # The unfused path (if _fused_swiglu=False) deinterleaves the GEMM output before splitting.
+        if self._fused_swiglu:
+            l1_stacked = interleave_l1_weights(l1_stacked, granularity_bf16=8)
         # Stack weights and convert to K-major
         self._l1_mat_b = make_b_k_major(l1_stacked)  # (1, K_packed, N_packed)
         self._l2_mat_b = make_b_k_major(l2_stacked)
@@ -230,6 +244,53 @@ class Nvfp4SharedExpert:
 
 
 
+    def _run_l1_fused(self, hidden_states: torch.Tensor) -> torch.Tensor:
+        """Fused L1 GEMM + SwiGLU + clamp — single kernel launch (1-group variant of MoE fused kernel)."""
+        num_tokens = hidden_states.shape[0]
+        x_bf16 = hidden_states.reshape(num_tokens, self.hidden_size)
+
+        # Quantize activation to NVFP4 (fused amax + quantize)
+        if getattr(self, '_use_runtime_gsa', False):
+            from dsv4.ops.quantize import quantize_nvfp4_gpu_fused
+            x_fp4, x_sf, gsa_l1_gpu = quantize_nvfp4_gpu_fused(x_bf16)
+            self._l1_gsa_buf.copy_(gsa_l1_gpu[:1].reshape(1))  # GPU → GPU
+        else:
+            from dsv4.ops.quantize import quantize_activation_nvfp4
+            x_fp4, x_sf = quantize_activation_nvfp4(x_bf16, self._l1_activation_global_scale)
+
+        # Padded buffer setup for 1-group GEMM
+        padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
+        padded_x_fp4 = self._padded_x_fp4_buf_l1
+        padded_x_fp4.view(torch.uint8).zero_()
+        padded_x_fp4.view(torch.uint8)[:num_tokens] = x_fp4.view(torch.uint8)
+
+        # Assemble A-side scales
+        scale_a = self._assemble_scales_single_group(x_sf, num_tokens, self._padded_x_sf_buf_l1)
+
+        # Expert offsets: [padded_rows] for 1 group (int32, pre-allocated)
+        expert_offsets = self._expert_offsets_buf
+        expert_offsets.fill_(padded_rows)
+
+        # Global scales — GPU-computed gsa already in _l1_gsa_buf (no CPU sync)
+        gsa = self._l1_gsa_buf
+
+        # Run fused GEMM + SwiGLU
+        l1_out = run_fused_swiglu_grouped_gemm(
+            mat_a=padded_x_fp4,
+            mat_b=self._l1_mat_b,
+            scale_a=scale_a,
+            scale_b=self._l1_scale_b,
+            expert_offsets=expert_offsets,
+            global_scale_a=gsa,
+            global_scale_b=self._l1_gsb,
+            swiglu_limit=self.swiglu_limit if self.swiglu_limit is not None else 0.0,
+        )
+        l1_out_real = l1_out[:num_tokens]  # (num_tokens, 2*intermediate) BF16, interleaved [silu(gate), silu(gate)*up]
+        # Deinterleave to separate gate and up, then take up half (SwiGLU result)
+        l1_deil = deinterleave_l1_weights(l1_out_real.unsqueeze(0).contiguous())[0]  # (num_tokens, 2*intermediate) deinterleaved
+        intermediate = l1_deil[:, self.intermediate_size:]  # up half = silu(gate)*up
+        return intermediate  # (num_tokens, intermediate_size) BF16
+
     def _run_l1(self, hidden_states: torch.Tensor) -> torch.Tensor:
         """L1 GEMM: activation × gate_up_weight → BF16."""
         num_tokens = hidden_states.shape[0]
@@ -276,6 +337,10 @@ class Nvfp4SharedExpert:
 
     def _run_l2(self, intermediate: torch.Tensor) -> torch.Tensor:
         """L2 GEMM: intermediate × down_weight → BF16."""
+        # The intermediate from fused SwiGLU deinterleave is a column slice
+        # (non-contiguous). quantize_nvfp4_gpu_fused requires contiguous input.
+        if not intermediate.is_contiguous():
+            intermediate = intermediate.contiguous()
         num_tokens = intermediate.shape[0]
         padded_rows = cutedsl_ceil_div(num_tokens, 128) * 128
 
@@ -325,21 +390,24 @@ class Nvfp4SharedExpert:
         """Actual implementation — called via custom autograd to be torch.compile-safe."""
         self._ensure_initialized()
 
-        l1_out = self._run_l1(hidden_states)
-        if l1_out.shape[1] < 2 * self.intermediate_size:
-            print(f"  WARNING: l1_out shape {l1_out.shape} < expected (N, {2*self.intermediate_size})", flush=True)
+        if self._fused_swiglu:
+            # P1: Fused L1 GEMM + SwiGLU + clamp in one kernel launch
+            intermediate = self._run_l1_fused(hidden_states)
+        else:
+            l1_out = self._run_l1(hidden_states)
+            if l1_out.shape[1] < 2 * self.intermediate_size:
+                print(f"  WARNING: l1_out shape {l1_out.shape} < expected (N, {2*self.intermediate_size})", flush=True)
 
-        gate = l1_out[:, :self.intermediate_size]
-        up = l1_out[:, self.intermediate_size:]
-        if torch.isnan(l1_out).any():
-            print(f"  SE L1 NaN: l1_out nan at {torch.isnan(l1_out).sum().item()} / {l1_out.numel()} positions, shape={l1_out.shape}", flush=True)
-        if torch.isnan(gate).any() or torch.isnan(up).any():
-            print(f"  SE gate nan={torch.isnan(gate).any().item()} up nan={torch.isnan(up).any().item()}", flush=True)
-        if self.swiglu_limit is not None:
-            # Match SiluAndMulWithClamp: clamp gate BEFORE silu, clamp up to [-limit, limit]
-            gate = gate.clamp(max=self.swiglu_limit)
-            up = up.clamp(min=-self.swiglu_limit, max=self.swiglu_limit)
-        intermediate = torch.nn.functional.silu(gate) * up
+            gate = l1_out[:, :self.intermediate_size]
+            up = l1_out[:, self.intermediate_size:]
+            if torch.isnan(l1_out).any():
+                print(f"  SE L1 NaN: l1_out nan at {torch.isnan(l1_out).sum().item()} / {l1_out.numel()} positions, shape={l1_out.shape}", flush=True)
+            if torch.isnan(gate).any() or torch.isnan(up).any():
+                print(f"  SE gate nan={torch.isnan(gate).any().item()} up nan={torch.isnan(up).any().item()}", flush=True)
+            if self.swiglu_limit is not None:
+                gate = gate.clamp(max=self.swiglu_limit)
+                up = up.clamp(min=-self.swiglu_limit, max=self.swiglu_limit)
+            intermediate = torch.nn.functional.silu(gate) * up
 
         output = self._run_l2(intermediate)
         return output

dsv4/ops/quantize.py

@@ -315,6 +315,9 @@ def quantize_nvfp4_gpu_fused(x_bf16, divisor=6.0 * 448.0):
         x_sf: (M, N//16) float8_e4m3fn
         gsa: (M,) float32 GPU tensor — per-row global scale for GEMM
     """
+    # CUDA kernels require contiguous input — column slices from deinterleave are non-contiguous
+    if not x_bf16.is_contiguous():
+        x_bf16 = x_bf16.contiguous()
     from dsv4.kernels.cuda.loader import get_cuda_module
     amax_mod = get_cuda_module("amax_gsa", ["amax_gsa.cu"])
     gsa_gpu = amax_mod.compute_amax_gsa(x_bf16, divisor)  # scalar GPU tensor
@@ -349,3 +352,102 @@ def quantize_nvfp4_gpu(x_bf16, global_scale):
     from dsv4.kernels.cuda.loader import get_cuda_module
     mod = get_cuda_module("quantize_nvfp4", ["quantize_nvfp4.cu"])
     return mod.quantize_nvfp4(x_bf16, global_scale)
+
+
+class QuantizedActivation:
+    """Pre-quantized NVFP4 activation tensor.
+    
+    Carries the FP4 data, block scales, and per-row global scale
+    so downstream Nvfp4Linear calls can skip quantization and go
+    straight to GEMM.
+    
+    Created by rmsnorm_quantize_nvfp4() or quantize_nvfp4_gpu_fused().
+    Consumed by Nvfp4Linear.run_from_quantized().
+    """
+    __slots__ = ['x_fp4', 'x_sf', 'gsa', 'inv_rms', 'num_tokens']
+    
+    def __init__(self, x_fp4, x_sf, gsa, inv_rms=None):
+        self.x_fp4 = x_fp4  # (M, N//2) FP4
+        self.x_sf = x_sf    # (M, N//16) E4M3
+        self.gsa = gsa      # (M,) FP32
+        self.inv_rms = inv_rms  # (M,) FP32, optional
+        self.num_tokens = x_fp4.shape[0]
+
+
+def dequantize_nvfp4(x_fp4, x_sf, gsa, shape=None):
+    """Dequantize NVFP4 → BF16 using the CUDA dequant kernel.
+    
+    Args:
+        x_fp4: (M, N//2) FP4 packed
+        x_sf: (M, N//16) E4M3 block scales
+        gsa: (M,) or (M, 1) or (1,) FP32 global scale per row
+        shape: unused, kept for API compat
+    
+    Returns:
+        (M, N) BF16 tensor
+    """
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("dequant_nvfp4", ["dequant_nvfp4.cu"])
+    if gsa.dim() == 2:
+        gsa = gsa.squeeze(1)  # (M, 1) → (M,)
+    # dequant kernel expects uint8 for both fp4 and sf
+    if x_fp4.dtype != torch.uint8:
+        x_fp4 = x_fp4.view(torch.uint8)
+    if x_sf.dtype != torch.uint8:
+        x_sf = x_sf.view(torch.uint8)
+    return mod.dequant_nvfp4(x_fp4, x_sf, gsa)
+
+
+def mhc_rmsnorm_quantize_nvfp4(X_l, A_l, norm_weight, eps=1e-6, divisor=6.0 * 448.0):
+    """Fused mHC pre_block + RMSNorm + NVFP4 quantize: 2 kernel launches total.
+    
+    Replaces: bmm (1 launch) + rmsnorm (4+ launches) + quantize (2 launches)
+    Total unfused: 7+ launches per site × 122 sites = 854+ launches/token
+    Fused: 2 launches per site × 122 sites = 244 launches → 610 launches saved/token.
+    
+    Args:
+        X_l: (M, n_hc, N) BF16 tensor. n_hc must be <= 4, N multiple of 16.
+        A_l: (M, n_hc) BF16 tensor. Softmax weights from mHC._dynamic_params.
+        norm_weight: (N,) FP32 RMSNorm weight.
+        eps: RMSNorm epsilon (default 1e-6).
+        divisor: gsa = amax / divisor. Default 6.0 * 448.0 = 2688.0.
+    
+    Returns:
+        QuantizedActivation with x_fp4, x_sf, gsa, inv_rms
+    """
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("fused_mhc_rmsnorm_quantize", ["fused_mhc_rmsnorm_quantize.cu"])
+    x_fp4, x_sf, gsa, inv_rms = mod.mhc_rmsnorm_quantize_nvfp4(X_l, A_l, norm_weight, eps, divisor)
+    return QuantizedActivation(x_fp4, x_sf, gsa, inv_rms)
+
+
+def rmsnorm_quantize_nvfp4(x_bf16, norm_weight, eps=1e-6, divisor=6.0 * 448.0):
+    """Fused RMSNorm + amax + NVFP4 quantize: 2 kernel launches total.
+    
+    Replaces the unfused path:
+      rmsnorm(x, weight) → 4+ BF16 launches
+      quantize_nvfp4_gpu_fused(rmsnormed) → 2 kernel launches + amax
+    Total unfused: 6+ launches per call × 122 calls/layer-step = 732+ launches/token
+    
+    Fused: 2 kernel launches per call × 122 calls = 244 launches → 488 launches saved/token.
+    
+    Two-kernel approach (correct cross-CTA reduction):
+      Kernel 1: compute RMS + amax of normalized output → gsa per row (GPU buffer)
+      Kernel 2: normalize + quantize using gsa from GPU buffer (no CPU sync)
+    
+    Args:
+        x_bf16: (M, N) BF16 tensor. N must be a multiple of 16.
+        norm_weight: (N,) FP32 RMSNorm weight.
+        eps: RMSNorm epsilon (default 1e-6).
+        divisor: gsa = amax / divisor. Default 6.0 * 448.0 = 2688.0.
+    
+    Returns:
+        x_fp4: (M, N//2) FP4 packed (uint8 view of float4_e2m1fn_x2)
+        x_sf: (M, N//16) E4M3 block scales
+        gsa: (M,) FP32 per-row global scale for GEMM
+        inv_rms: (M,) FP32 per-row 1/RMS (useful for downstream if needed)
+    """
+    from dsv4.kernels.cuda.loader import get_cuda_module
+    mod = get_cuda_module("fused_rmsnorm_quantize", ["fused_rmsnorm_quantize.cu"])
+    x_fp4, x_sf, gsa, inv_rms = mod.rmsnorm_quantize_nvfp4(x_bf16, norm_weight, eps, divisor)
+    return QuantizedActivation(x_fp4, x_sf, gsa, inv_rms)

dsv4/ops/rope_cuda.py

@@ -0,0 +1,93 @@
+"""CUDA RoPE kernel — 1 kernel launch per call instead of 5-6 PyTorch ops.
+
+Uses ctypes to call the compiled kernel directly (no ATen/pybind11).
+Same pattern as fmha_multitile_op.py and other production kernels.
+"""
+
+import torch
+import ctypes
+import subprocess
+from pathlib import Path
+
+_LIB = None
+
+def _compile_and_load():
+    global _LIB
+    if _LIB is not None:
+        return _LIB
+    
+    cu_path = Path(__file__).parent.parent / "kernels" / "cuda" / "rope_cuda.cu"
+    assert cu_path.exists(), f"rope_cuda.cu not found at {cu_path}"
+    
+    # Compile to shared library
+    build_dir = Path(__file__).parent / "cuda" / "_build_cache"
+    build_dir.mkdir(parents=True, exist_ok=True)
+    so_path = build_dir / "librope_cuda.so"
+    
+    if not so_path.exists() or cu_path.stat().st_mtime > so_path.stat().st_mtime:
+        nvcc = "/usr/local/cuda/bin/nvcc"
+        cmd = [
+            nvcc, "-shared", "-o", str(so_path), str(cu_path),
+            "-arch=sm_100a",
+            "--generate-code=arch=compute_100a,code=[sm_100a,compute_100a]",
+            "-use_fast_math", "-O3",
+            "-Xcompiler", "-fPIC",
+        ]
+        result = subprocess.run(cmd, capture_output=True, text=True, timeout=120)
+        if result.returncode != 0:
+            raise RuntimeError(f"rope_cuda.cu compilation failed:\n{result.stderr}")
+    
+    _LIB = ctypes.CDLL(str(so_path))
+    return _LIB
+
+
+def apply_rope(x, positions, cos_cache, sin_cache, rope_dim, inverse=False):
+    """Apply forward or inverse RoPE in-place using a single CUDA kernel.
+    
+    Args:
+        x: (T, n_h, hd) BF16 — modified in-place
+        positions: (T,) int64 — token positions  
+        cos_cache: (max_pos, rope_dim//2) float32
+        sin_cache: (max_pos, rope_dim//2) float32
+        rope_dim: 64
+        inverse: True for inverse RoPE
+    
+    Returns:
+        x (modified in-place)
+    """
+    lib = _compile_and_load()
+    T, n_h, hd = x.shape
+    nope_dim = hd - rope_dim
+    half_rope = rope_dim // 2
+    
+    # Ensure types and devices
+    pos = positions.to(device=x.device, dtype=torch.int64)
+    assert x.dtype == torch.bfloat16
+    assert cos_cache.dtype == torch.float32
+    assert sin_cache.dtype == torch.float32
+    
+    # Launch parameters
+    total_pairs = T * n_h * half_rope
+    threads = 256
+    blocks = (total_pairs + threads - 1) // threads
+    
+    # Get raw CUDA stream
+    stream = torch.cuda.current_stream().cuda_stream
+    
+    # Call the kernel
+    lib.apply_rope_launch(
+        ctypes.c_void_p(x.data_ptr()),
+        ctypes.c_void_p(pos.data_ptr()),
+        ctypes.c_void_p(cos_cache.data_ptr()),
+        ctypes.c_void_p(sin_cache.data_ptr()),
+        ctypes.c_int(T),
+        ctypes.c_int(n_h),
+        ctypes.c_int(hd),
+        ctypes.c_int(nope_dim),
+        ctypes.c_int(rope_dim),
+        ctypes.c_bool(inverse),
+        ctypes.c_int(blocks),
+        ctypes.c_int(threads),
+        ctypes.c_void_p(stream),
+    )
+    return x

encoding/__init__.py

@@ -0,0 +1 @@
+# encoding package

encoding/deepseek_v4_encoding.py

@@ -0,0 +1,757 @@
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
+# ruff: noqa
+# fmt: off
+
+"""
+DeepSeek-V4 Encoding
+
+A self-contained implementation for encoding/decoding DeepSeek-V4 chat messages
+with tool calling, thinking mode, and quick instruction task support.
+"""
+
+from typing import Any, Dict, List, Union, Optional, Tuple
+import copy
+import json
+
+import regex as re
+
+# ============================================================
+# Special Tokens
+# ============================================================
+
+bos_token: str = "<｜begin▁of▁sentence｜>"
+eos_token: str = "<｜end▁of▁sentence｜>"
+thinking_start_token: str = "<think>"
+thinking_end_token: str = "</think>"
+dsml_token: str = "｜DSML｜"
+
+USER_SP_TOKEN = "<｜User｜>"
+ASSISTANT_SP_TOKEN = "<｜Assistant｜>"
+LATEST_REMINDER_SP_TOKEN = "<｜latest_reminder｜>"
+
+# Task special tokens for internal classification tasks
+DS_TASK_SP_TOKENS = {
+    "action": "<｜action｜>",
+    "query": "<｜query｜>",
+    "authority": "<｜authority｜>",
+    "domain": "<｜domain｜>",
+    "title": "<｜title｜>",
+    "read_url": "<｜read_url｜>",
+}
+VALID_TASKS = set(DS_TASK_SP_TOKENS.keys())
+
+# ============================================================
+# Templates
+# ============================================================
+
+system_msg_template: str = "{content}"
+user_msg_template: str = "{content}"
+latest_reminder_msg_template: str = "{content}"
+assistant_msg_template: str = "{reasoning}{content}{tool_calls}" + eos_token
+assistant_msg_wo_eos_template: str = "{reasoning}{content}{tool_calls}"
+thinking_template: str = "{reasoning}"
+
+response_format_template: str = (
+    "## Response Format:\n\nYou MUST strictly adhere to the following schema to reply:\n{schema}"
+)
+tool_call_template: str = (
+    "<{dsml_token}invoke name=\"{name}\">\n{arguments}\n</{dsml_token}invoke>"
+)
+tool_calls_template = (
+    "<{dsml_token}{tc_block_name}>\n{tool_calls}\n</{dsml_token}{tc_block_name}>"
+)
+tool_calls_block_name: str = "tool_calls"
+
+tool_output_template: str = (
+    "<tool_result>{content}</tool_result>"
+)
+
+REASONING_EFFORT_MAX = (
+    "Reasoning Effort: Absolute maximum with no shortcuts permitted.\n"
+    "You MUST be very thorough in your thinking and comprehensively decompose the problem to resolve the root cause, rigorously stress-testing your logic against all potential paths, edge cases, and adversarial scenarios.\n"
+    "Explicitly write out your entire deliberation process, documenting every intermediate step, considered alternative, and rejected hypothesis to ensure absolutely no assumption is left unchecked.\n\n"
+)
+
+TOOLS_TEMPLATE = """## Tools
+
+You have access to a set of tools to help answer the user's question. You can invoke tools by writing a "<{dsml_token}tool_calls>" block like the following:
+
+<{dsml_token}tool_calls>
+<{dsml_token}invoke name="$TOOL_NAME">
+<{dsml_token}parameter name="$PARAMETER_NAME" string="true|false">$PARAMETER_VALUE</{dsml_token}parameter>
+...
+</{dsml_token}invoke>
+<{dsml_token}invoke name="$TOOL_NAME2">
+...
+</{dsml_token}invoke>
+</{dsml_token}tool_calls>
+
+String parameters should be specified as is and set `string="true"`. For all other types (numbers, booleans, arrays, objects), pass the value in JSON format and set `string="false"`.
+
+If thinking_mode is enabled (triggered by {thinking_start_token}), you MUST output your complete reasoning inside {thinking_start_token}...{thinking_end_token} BEFORE any tool calls or final response.
+
+Otherwise, output directly after {thinking_end_token} with tool calls or final response.
+
+### Available Tool Schemas
+
+{tool_schemas}
+
+You MUST strictly follow the above defined tool name and parameter schemas to invoke tool calls.
+"""
+
+# ============================================================
+# Utility Functions
+# ============================================================
+
+def to_json(value: Any) -> str:
+    """Serialize a value to JSON string."""
+    try:
+        return json.dumps(value, ensure_ascii=False)
+    except Exception:
+        return json.dumps(value, ensure_ascii=True)
+
+
+def tools_from_openai_format(tools):
+    """Extract function definitions from OpenAI-format tool list."""
+    return [tool["function"] for tool in tools]
+
+
+def tool_calls_from_openai_format(tool_calls):
+    """Convert OpenAI-format tool calls to internal format."""
+    return [
+        {
+            "name": tool_call["function"]["name"],
+            "arguments": tool_call["function"]["arguments"],
+        }
+        for tool_call in tool_calls
+    ]
+
+
+def tool_calls_to_openai_format(tool_calls):
+    """Convert internal tool calls to OpenAI format."""
+    return [
+        {
+            "type": "function",
+            "function": {
+                "name": tool_call["name"],
+                "arguments": tool_call["arguments"],
+            }
+        }
+        for tool_call in tool_calls
+    ]
+
+
+def encode_arguments_to_dsml(tool_call: Dict[str, Any]) -> str:
+    """
+    Encode tool call arguments into DSML parameter format.
+
+    Args:
+        tool_call: Dict with "name" and "arguments" keys.
+
+    Returns:
+        DSML-formatted parameter string.
+    """
+    p_dsml_template = '<{dsml_token}parameter name="{key}" string="{is_str}">{value}</{dsml_token}parameter>'
+    P_dsml_strs = []
+
+    if isinstance(tool_call["arguments"], str):
+        arguments = json.loads(tool_call["arguments"])
+    else:
+        arguments = tool_call["arguments"]
+
+    for k, v in arguments.items():
+        p_dsml_str = p_dsml_template.format(
+            dsml_token=dsml_token,
+            key=k,
+            is_str="true" if isinstance(v, str) else "false",
+            value=v if isinstance(v, str) else to_json(v),
+        )
+        P_dsml_strs.append(p_dsml_str)
+
+    return "\n".join(P_dsml_strs)
+
+
+def decode_dsml_to_arguments(tool_name: str, tool_args: Dict[str, Tuple[str, str]]) -> Dict[str, str]:
+    """
+    Decode DSML parameters back to a tool call dict.
+
+    Args:
+        tool_name: Name of the tool.
+        tool_args: Dict mapping param_name -> (value, is_string_flag).
+
+    Returns:
+        Dict with "name" and "arguments" (JSON string) keys.
+    """
+    def _decode_value(key: str, value: str, string: str):
+        if string == "true":
+            value = to_json(value)
+        return f"{to_json(key)}: {value}"
+
+    tool_args_json = "{" + ", ".join([_decode_value(k, v, string=is_str) for k, (v, is_str) in tool_args.items()]) + "}"
+    return dict(name=tool_name, arguments=tool_args_json)
+
+
+def render_tools(tools: List[Dict[str, Union[str, Dict[str, Any]]]]) -> str:
+    """
+    Render tool schemas into the system prompt format.
+
+    Args:
+        tools: List of tool schema dicts (each with name, description, parameters).
+
+    Returns:
+        Formatted tools section string.
+    """
+    tools_json = [to_json(t) for t in tools]
+
+    return TOOLS_TEMPLATE.format(
+        tool_schemas="\n".join(tools_json),
+        dsml_token=dsml_token,
+        thinking_start_token=thinking_start_token,
+        thinking_end_token=thinking_end_token,
+    )
+
+
+def find_last_user_index(messages: List[Dict[str, Any]]) -> int:
+    """Find the index of the last user/developer message."""
+    last_user_index = -1
+    for idx in range(len(messages) - 1, -1, -1):
+        if messages[idx].get("role") in ["user", "developer"]:
+            last_user_index = idx
+            break
+    return last_user_index
+
+
+# ============================================================
+# Message Rendering
+# ============================================================
+
+def render_message(index: int, messages: List[Dict[str, Any]], thinking_mode: str, drop_thinking: bool = True, reasoning_effort: Optional[str] = None) -> str:
+    """
+    Render a single message at the given index into its encoded string form.
+
+    This is the core function that converts each message in the conversation
+    into the DeepSeek-V4 format.
+
+    Args:
+        index: Index of the message to render.
+        messages: Full list of messages in the conversation.
+        thinking_mode: Either "chat" or "thinking".
+        drop_thinking: Whether to drop reasoning content from earlier turns.
+        reasoning_effort: Optional reasoning effort level ("max", "high", or None).
+
+    Returns:
+        Encoded string for this message.
+    """
+    assert 0 <= index < len(messages)
+    assert thinking_mode in ["chat", "thinking"], f"Invalid thinking_mode `{thinking_mode}`"
+
+    prompt = ""
+    msg = messages[index]
+    last_user_idx = find_last_user_index(messages)
+
+    role = msg.get("role")
+    content = msg.get("content")
+    tools = msg.get("tools")
+    response_format = msg.get("response_format")
+    tool_calls = msg.get("tool_calls")
+    reasoning = msg.get("reasoning")
+    wo_eos = msg.get("wo_eos", False)
+
+    if tools:
+        tools = tools_from_openai_format(tools)
+    if tool_calls:
+        tool_calls = tool_calls_from_openai_format(tool_calls)
+
+    # Reasoning effort prefix (only at index 0 in thinking mode with max effort)
+    assert reasoning_effort in ['max', None, 'high'], f"Invalid reasoning effort: {reasoning_effort}"
+    if index == 0 and thinking_mode == "thinking" and reasoning_effort == 'max':
+        prompt += REASONING_EFFORT_MAX
+
+    if role == "system":
+        prompt += system_msg_template.format(content=content or "")
+        if tools:
+            prompt += "\n\n" + render_tools(tools)
+        if response_format:
+            prompt += "\n\n" + response_format_template.format(schema=to_json(response_format))
+
+    elif role == "developer":
+        assert content, f"Invalid message for role `{role}`: {msg}"
+
+        content_developer = USER_SP_TOKEN
+        content_developer += content
+
+        if tools:
+            content_developer += "\n\n" + render_tools(tools)
+        if response_format:
+            content_developer += "\n\n" + response_format_template.format(schema=to_json(response_format))
+
+        prompt += user_msg_template.format(content=content_developer)
+
+    elif role == "user":
+        prompt += USER_SP_TOKEN
+
+        # Handle content blocks (tool results mixed with text)
+        content_blocks = msg.get("content_blocks")
+        if content_blocks:
+            parts = []
+            for block in content_blocks:
+                block_type = block.get("type")
+                if block_type == "text":
+                    parts.append(block.get("text", ""))
+                elif block_type == "tool_result":
+                    tool_content = block.get("content", "")
+                    if isinstance(tool_content, list):
+                        text_parts = []
+                        for b in tool_content:
+                            if b.get("type") == "text":
+                                text_parts.append(b.get("text", ""))
+                            else:
+                                text_parts.append(f"[Unsupported {b.get('type')}]")
+                        tool_content = "\n\n".join(text_parts)
+                    parts.append(tool_output_template.format(content=tool_content))
+                else:
+                    parts.append(f"[Unsupported {block_type}]")
+            prompt += "\n\n".join(parts)
+        else:
+            prompt += content or ""
+
+    elif role == "latest_reminder":
+        prompt += LATEST_REMINDER_SP_TOKEN + latest_reminder_msg_template.format(content=content)
+
+    elif role == "tool":
+        raise NotImplementedError("deepseek_v4 merges tool messages into user; please preprocess with merge_tool_messages()")
+
+    elif role == "assistant":
+        thinking_part = ""
+        tc_content = ""
+
+        if tool_calls:
+            tc_list = [
+                tool_call_template.format(
+                    dsml_token=dsml_token,
+                    name=tc.get("name"),
+                    arguments=encode_arguments_to_dsml(tc)
+                )
+                for tc in tool_calls
+            ]
+            tc_content += '\n\n' + tool_calls_template.format(
+                dsml_token=dsml_token,
+                tool_calls="\n".join(tc_list),
+                tc_block_name=tool_calls_block_name,
+            )
+
+        summary_content = content or ""
+        reasoning = reasoning or ""
+
+        # Check if previous message has a task - if so, this is a task output (no thinking)
+        prev_has_task = index - 1 >= 0 and messages[index - 1].get("task") is not None
+
+        if thinking_mode == "thinking" and not prev_has_task:
+            if not drop_thinking or index > last_user_idx:
+                thinking_part = thinking_template.format(reasoning=reasoning) + thinking_end_token
+            else:
+                thinking_part = ""
+
+        if wo_eos:
+            prompt += assistant_msg_wo_eos_template.format(
+                reasoning=thinking_part,
+                content=summary_content,
+                tool_calls=tc_content,
+            )
+        else:
+            prompt += assistant_msg_template.format(
+                reasoning=thinking_part,
+                content=summary_content,
+                tool_calls=tc_content,
+            )
+    else:
+        raise NotImplementedError(f"Unknown role: {role}")
+
+    # Append transition tokens based on what follows
+    if index + 1 < len(messages) and messages[index + 1].get("role") not in ["assistant", "latest_reminder"]:
+        return prompt
+
+    task = messages[index].get("task")
+    if task is not None:
+        # Task special token for internal classification tasks
+        assert task in VALID_TASKS, f"Invalid task: '{task}'. Valid tasks are: {list(VALID_TASKS)}"
+        task_sp_token = DS_TASK_SP_TOKENS[task]
+
+        if task != "action":
+            # Non-action tasks: append task sp token directly after the message
+            prompt += task_sp_token
+        else:
+            # Action task: append Assistant + thinking token + action sp token
+            prompt += ASSISTANT_SP_TOKEN
+            prompt += thinking_end_token if thinking_mode != "thinking" else thinking_start_token
+            prompt += task_sp_token
+
+    elif messages[index].get("role") in ["user", "developer"]:
+        # Normal generation: append Assistant + thinking token
+        prompt += ASSISTANT_SP_TOKEN
+        if not drop_thinking and thinking_mode == "thinking":
+            prompt += thinking_start_token
+        elif drop_thinking and thinking_mode == "thinking" and index >= last_user_idx:
+            prompt += thinking_start_token
+        else:
+            prompt += thinking_end_token
+
+    return prompt
+
+
+# ============================================================
+# Preprocessing
+# ============================================================
+
+def merge_tool_messages(messages: List[Dict[str, Any]]) -> List[Dict[str, Any]]:
+    """
+    Merge tool messages into the preceding user message using content_blocks format.
+
+    DeepSeek-V4 does not have a standalone "tool" role; instead, tool results
+    are encoded as <tool_result> blocks within user messages.
+
+    This function converts a standard OpenAI-format conversation (with separate
+    "tool" role messages) into V4 format where tool results are merged into
+    user messages.
+
+    Args:
+        messages: List of message dicts in OpenAI format.
+
+    Returns:
+        Processed message list with tool messages merged into user messages.
+    """
+    merged: List[Dict[str, Any]] = []
+
+    for msg in messages:
+        msg = copy.deepcopy(msg)
+        role = msg.get("role")
+
+        if role == "tool":
+            # Convert tool message to a user message with tool_result block
+            tool_block = {
+                "type": "tool_result",
+                "tool_use_id": msg.get("tool_call_id", ""),
+                "content": msg.get("content", ""),
+            }
+            # Merge into previous message if it's already a user (merged tool)
+            if merged and merged[-1].get("role") == "user" and "content_blocks" in merged[-1]:
+                merged[-1]["content_blocks"].append(tool_block)
+            else:
+                merged.append({
+                    "role": "user",
+                    "content_blocks": [tool_block],
+                })
+        elif role == "user":
+            text_block = {"type": "text", "text": msg.get("content", "")}
+            if merged and merged[-1].get("role") == "user" and "content_blocks" in merged[-1] and merged[-1].get("task") is None:
+                merged[-1]["content_blocks"].append(text_block)
+            else:
+                new_msg = {
+                    "role": "user",
+                    "content": msg.get("content", ""),
+                    "content_blocks": [text_block],
+                }
+                # Preserve extra fields (task, wo_eos, mask, etc.)
+                for key in ("task", "wo_eos", "mask"):
+                    if key in msg:
+                        new_msg[key] = msg[key]
+                merged.append(new_msg)
+        else:
+            merged.append(msg)
+
+    return merged
+
+
+def sort_tool_results_by_call_order(messages: List[Dict[str, Any]]) -> List[Dict[str, Any]]:
+    """
+    Sort tool_result blocks within user messages by the order of tool_calls
+    in the preceding assistant message.
+
+    Args:
+        messages: Preprocessed message list (after merge_tool_messages).
+
+    Returns:
+        Message list with sorted tool result blocks.
+    """
+    last_tool_call_order: Dict[str, int] = {}
+
+    for msg in messages:
+        role = msg.get("role")
+        if role == "assistant" and msg.get("tool_calls"):
+            last_tool_call_order = {}
+            for idx, tc in enumerate(msg["tool_calls"]):
+                tc_id = tc.get("id") or tc.get("function", {}).get("id", "")
+                if tc_id:
+                    last_tool_call_order[tc_id] = idx
+
+        elif role == "user" and msg.get("content_blocks"):
+            tool_blocks = [b for b in msg["content_blocks"] if b.get("type") == "tool_result"]
+            if len(tool_blocks) > 1 and last_tool_call_order:
+                sorted_blocks = sorted(
+                    tool_blocks,
+                    key=lambda b: last_tool_call_order.get(b.get("tool_use_id", ""), 0)
+                )
+                sorted_idx = 0
+                new_blocks = []
+                for block in msg["content_blocks"]:
+                    if block.get("type") == "tool_result":
+                        new_blocks.append(sorted_blocks[sorted_idx])
+                        sorted_idx += 1
+                    else:
+                        new_blocks.append(block)
+                msg["content_blocks"] = new_blocks
+
+    return messages
+
+
+# ============================================================
+# Main Encoding Function
+# ============================================================
+
+def encode_messages(
+    messages: List[Dict[str, Any]],
+    thinking_mode: str,
+    context: Optional[List[Dict[str, Any]]] = None,
+    drop_thinking: bool = True,
+    add_default_bos_token: bool = True,
+    reasoning_effort: Optional[str] = None,
+) -> str:
+    """
+    Encode a list of messages into the DeepSeek-V4 prompt format.
+
+    This is the main entry point for encoding conversations. It handles:
+    - BOS token insertion
+    - Thinking mode with optional reasoning content dropping
+    - Tool message merging into user messages
+    - Multi-turn conversation context
+
+    Args:
+        messages: List of message dicts to encode.
+        thinking_mode: Either "chat" or "thinking".
+        context: Optional preceding context messages (already encoded prefix).
+        drop_thinking: If True, drop reasoning from earlier assistant turns
+                      (only keep reasoning for messages after the last user message).
+        add_default_bos_token: Whether to prepend BOS token at conversation start.
+        reasoning_effort: Optional reasoning effort level ("max", "high", or None).
+
+    Returns:
+        The encoded prompt string.
+    """
+    context = context if context else []
+
+    # Preprocess: merge tool messages and sort tool results
+    messages = merge_tool_messages(messages)
+    messages = sort_tool_results_by_call_order(context + messages)[len(context):]
+    if context:
+        context = merge_tool_messages(context)
+        context = sort_tool_results_by_call_order(context)
+
+    full_messages = context + messages
+
+    prompt = bos_token if add_default_bos_token and len(context) == 0 else ""
+
+    # Resolve drop_thinking: if any message has tools defined, don't drop thinking
+    effective_drop_thinking = drop_thinking
+    if any(m.get("tools") for m in full_messages):
+        effective_drop_thinking = False
+
+    if thinking_mode == "thinking" and effective_drop_thinking:
+        full_messages = _drop_thinking_messages(full_messages)
+        # After dropping, recalculate how many messages to render
+        # (context may have shrunk too)
+        num_to_render = len(full_messages) - len(_drop_thinking_messages(context))
+        context_len = len(full_messages) - num_to_render
+    else:
+        num_to_render = len(messages)
+        context_len = len(context)
+
+    for idx in range(num_to_render):
+        prompt += render_message(
+            idx + context_len,
+            full_messages,
+            thinking_mode=thinking_mode,
+            drop_thinking=effective_drop_thinking,
+            reasoning_effort=reasoning_effort,
+        )
+
+    return prompt
+
+
+def _drop_thinking_messages(messages: List[Dict[str, Any]]) -> List[Dict[str, Any]]:
+    """
+    Drop reasoning and non-essential messages before the last user message.
+
+    Behavior:
+    - Messages with role in ["user", "system", "tool", "latest_reminder"] are always kept.
+    - Messages at or after the last user index are always kept.
+    - Assistant messages before the last user get reasoning removed.
+    - Developer messages before the last user are dropped entirely.
+    """
+    last_user_idx = find_last_user_index(messages)
+    result = []
+    keep_roles = {"user", "system", "tool", "latest_reminder", "direct_search_results"}
+
+    for idx, msg in enumerate(messages):
+        role = msg.get("role")
+        if role in keep_roles or idx >= last_user_idx:
+            result.append(msg)
+        elif role == "assistant":
+            msg = copy.copy(msg)
+            msg.pop("reasoning", None)
+            result.append(msg)
+        # developer and other roles before last_user_idx are dropped
+
+    return result
+
+
+# ============================================================
+# Parsing (Decoding model output)
+# ============================================================
+
+def _read_until_stop(index: int, text: str, stop: List[str]) -> Tuple[int, str, Optional[str]]:
+    """
+    Read text from index until one of the stop strings is found.
+
+    Returns:
+        Tuple of (new_index, content_before_stop, matched_stop_string_or_None).
+    """
+    min_pos = len(text)
+    matched_stop = None
+
+    for s in stop:
+        pos = text.find(s, index)
+        if pos != -1 and pos < min_pos:
+            min_pos = pos
+            matched_stop = s
+
+    if matched_stop:
+        content = text[index:min_pos]
+        return min_pos + len(matched_stop), content, matched_stop
+    else:
+        content = text[index:]
+        return len(text), content, None
+
+
+def parse_tool_calls(index: int, text: str) -> Tuple[int, Optional[str], List[Dict[str, str]]]:
+    """
+    Parse DSML tool calls from text starting at the given index.
+
+    Args:
+        index: Starting position in text.
+        text: The full text to parse.
+
+    Returns:
+        Tuple of (new_index, last_stop_token, list_of_tool_call_dicts).
+        Each tool call dict has "name" and "arguments" keys.
+    """
+    tool_calls: List[Dict[str, Any]] = []
+    stop_token = None
+    tool_calls_end_token = f"</{dsml_token}{tool_calls_block_name}>"
+
+    while index < len(text):
+        index, content_before, stop_token = _read_until_stop(index, text, [f"<{dsml_token}invoke", tool_calls_end_token])
+        if content_before != ">\n":
+            raise ValueError(f"Tool call format error: expected '>\\n' but got '{content_before}'")
+
+        if stop_token == tool_calls_end_token:
+            break
+
+        if stop_token is None:
+            raise ValueError("Missing special token in tool calls")
+
+        index, tool_name_content, stop_token = _read_until_stop(index, text, [f"<{dsml_token}parameter", f"</{dsml_token}invoke"])
+
+        p_tool_name = re.findall(r'^\s*name="(.*?)">\n$', tool_name_content, flags=re.DOTALL)
+        if len(p_tool_name) != 1:
+            raise ValueError(f"Tool name format error: '{tool_name_content}'")
+        tool_name = p_tool_name[0]
+
+        tool_args: Dict[str, Tuple[str, str]] = {}
+        while stop_token == f"<{dsml_token}parameter":
+            index, param_content, stop_token = _read_until_stop(index, text, [f"/{dsml_token}parameter"])
+
+            param_kv = re.findall(r'^ name="(.*?)" string="(true|false)">(.*?)<$', param_content, flags=re.DOTALL)
+            if len(param_kv) != 1:
+                raise ValueError(f"Parameter format error: '{param_content}'")
+            param_name, string, param_value = param_kv[0]
+
+            if param_name in tool_args:
+                raise ValueError(f"Duplicate parameter name: '{param_name}'")
+            tool_args[param_name] = (param_value, string)
+
+            index, content, stop_token = _read_until_stop(index, text, [f"<{dsml_token}parameter", f"</{dsml_token}invoke"])
+            if content != ">\n":
+                raise ValueError(f"Parameter format error: expected '>\\n' but got '{content}'")
+
+        tool_call = decode_dsml_to_arguments(tool_name=tool_name, tool_args=tool_args)
+        tool_calls.append(tool_call)
+
+    return index, stop_token, tool_calls
+
+
+def parse_message_from_completion_text(text: str, thinking_mode: str) -> Dict[str, Any]:
+    """
+    Parse a model completion text into a structured assistant message.
+
+    This function takes the raw text output from the model (a single assistant turn)
+    and extracts:
+    - reasoning (thinking block)
+    - content (summary/response)
+    - tool_calls (if any)
+
+    NOTE: This function is designed to parse only correctly formatted strings and
+    will raise ValueError for malformed output.
+
+    Args:
+        text: The raw completion text (including EOS token).
+        thinking_mode: Either "chat" or "thinking".
+
+    Returns:
+        Dict with keys: "role", "content", "reasoning", "tool_calls".
+        tool_calls are in OpenAI format.
+    """
+    summary_content, reasoning = "", ""
+    tool_calls: List[Dict[str, str]] = []
+    index, stop_token = 0, None
+    tool_calls_start_token = f"\n\n<{dsml_token}{tool_calls_block_name}"
+
+    is_thinking = thinking_mode == "thinking"
+    is_tool_calling = False
+
+    if is_thinking:
+        index, content_delta, stop_token = _read_until_stop(index, text, [thinking_end_token, tool_calls_start_token])
+        reasoning = content_delta
+        if stop_token != thinking_end_token:
+            raise ValueError("Invalid thinking format: missing </think>")
+
+    index, content_delta, stop_token = _read_until_stop(index, text, [eos_token, tool_calls_start_token])
+    summary_content = content_delta
+    if stop_token == tool_calls_start_token:
+        is_tool_calling = True
+    else:
+        if stop_token != eos_token:
+            raise ValueError("Invalid format: missing EOS token")
+
+    if is_tool_calling:
+        index, stop_token, tool_calls = parse_tool_calls(index, text)
+
+        index, tool_ends_text, stop_token = _read_until_stop(index, text, [eos_token])
+        if tool_ends_text:
+            raise ValueError("Unexpected content after tool calls")
+
+    if len(text) != index or stop_token not in [eos_token, None]:
+        raise ValueError("Unexpected content at end")
+
+    for sp_token in [bos_token, eos_token, thinking_start_token, thinking_end_token, dsml_token]:
+        if sp_token in summary_content or sp_token in reasoning:
+            raise ValueError(f"Unexpected special token '{sp_token}' in content")
+
+    return {
+        "role": "assistant",
+        "content": summary_content,
+        "reasoning": reasoning,
+        "tool_calls": tool_calls_to_openai_format(tool_calls)
+    }
+
+# fmt: on

helpers/import_closure.py

@@ -0,0 +1,38 @@
+# helpers/import_closure.py — list dsv4 modules NOT reachable from the entry points.
+# Usage: python3 helpers/import_closure.py  (run from repo root)
+# NOTE: handles lazy imports inside functions (single_shot uses these heavily)
+import ast, pathlib, sys
+ROOT = pathlib.Path(__file__).resolve().parent.parent
+ENTRYPOINTS = ["single_shot_inference.py"]  # vLLM has 0 imports of dsv4 (Step 0 confirmed)
+
+def module_to_path(mod):
+    p = ROOT / (mod.replace(".", "/") + ".py")
+    if p.exists(): return p
+    p = ROOT / mod.replace(".", "/") / "__init__.py"
+    return p if p.exists() else None
+
+def imports_of(path):
+    """Parse ALL imports including lazy ones inside functions."""
+    tree = ast.parse(path.read_text())
+    out = set()
+    for n in ast.walk(tree):
+        if isinstance(n, ast.Import):
+            out |= {a.name for a in n.names}
+        elif isinstance(n, ast.ImportFrom) and n.module:
+            out.add(n.module)
+    return {m for m in out if m.startswith("dsv4")}
+
+seen, stack = set(), list(ENTRYPOINTS)
+stack = [ (ROOT / e) for e in stack ]
+while stack:
+    f = stack.pop()
+    if f in seen or f is None or not f.exists(): continue
+    seen.add(f)
+    for m in imports_of(f):
+        mp = module_to_path(m)
+        if mp and mp not in seen: stack.append(mp)
+
+all_py = set((ROOT / "dsv4").rglob("*.py"))
+dead = sorted(p.relative_to(ROOT) for p in all_py - seen if "__pycache__" not in str(p))
+print("REACHABLE:", len(seen), " | DEAD CANDIDATES:", len(dead))
+for d in dead: print("  ", d)

reference/README.md

@@ -0,0 +1,49 @@
+# Reference Implementations
+
+This directory contains **read-only** reference implementations from official sources.
+Do not modify these files — they exist to cross-check our production pipeline.
+
+## Directory Layout
+
+```
+reference/
+├── vllm/                        # vLLM project reference (Apache-2.0)
+│   ├── tokenizers/
+│   │   ├── deepseek_v4.py           # Tokenizer wrapper — apply_chat_template for DSV4
+│   │   └── deepseek_v4_encoding.py  # Official prompt encoder (canonical source)
+│   ├── reasoning/
+│   │   ├── deepseek_v3_reasoning_parser.py   # Thinking-mode dispatcher
+│   │   └── deepseek_r1_reasoning_parser.py   # ）/） reasoning token parser
+│   └── tool_parsers/
+│       ├── deepseekv4_tool_parser.py         # DSML tool call parser (V4)
+│       └── deepseekv32_tool_parser.py        # DSML tool call parser (V3.2 base)
+│
+└── official_inference/          # Original weight's reference inference code
+    ├── generate.py                  # Official generate loop + encode_messages usage
+    ├── model.py                     # BF16/FP8 model implementation
+    ├── kernel.py                    # Reference CUDA kernels
+    ├── convert.py                   # Weight conversion
+    └── config.json                  # Model config (small variant)
+```
+
+## Key Files for Our Pipeline
+
+1. **`vllm/tokenizers/deepseek_v4_encoding.py`** — Canonical prompt encoder.
+   Already copied to `encoding/deepseek_v4_encoding.py` in the repo root (our live import).
+   If vLLM updates this file, diff and sync.
+
+2. **`vllm/tokenizers/deepseek_v4.py`** — Shows how vLLM wraps the tokenizer
+   to add `apply_chat_template` support. Key insight: it calls
+   `encode_messages(messages, thinking_mode=..., ...)` then
+   `tokenizer.encode(prompt_str, add_special_tokens=False)`.
+   This is exactly what our single_shot does.
+
+3. **`official_inference/generate.py`** — The original weight's inference entry point.
+   Uses `tokenizer.encode(encode_messages(messages, thinking_mode="chat"))`
+   (default `add_special_tokens=True`) and `parse_message_from_completion_text()`
+   for output parsing.
+
+4. **`vllm/reasoning/`** — How vLLM detects thinking mode boundaries
+   (`）、` start, `）/）` end). Useful when we integrate streaming.
+
+5. **`vllm/tool_parsers/`** — DSML tool call parsing for future tool-use support.