9e98c067ab
test: Layout D TMEM read using 32x32b.x8 format, 4 warps
2026-05-28 10:07:15 +00:00
68d1a7920c
test: M=64 in both desc and idesc
2026-05-28 10:04:17 +00:00
0f51fda0da
test: try N=8 in idesc
2026-05-28 10:02:52 +00:00
4f7c9649fd
test: clean UMMA QK test, debug 4x factor, 8KB padding, 128 TMEM cols
2026-05-28 10:01:39 +00:00
ac65ece33b
test: TMEM 2-store with fence outside wid guard, 64 threads
2026-05-28 09:59:43 +00:00
2c89eea6be
test: fence+sync between 2 tmem_stores
2026-05-28 09:58:51 +00:00
24c5afe1dc
test: 64 threads, 2 stores to col 0
2026-05-28 09:57:53 +00:00
987f2c8917
test: 2 tmem_stores to SAME column 0
2026-05-28 09:57:07 +00:00
494149f034
test: 32 threads (1 warp), no guards, all participate
2026-05-28 09:56:17 +00:00
f0cb71da5c
test: TMEM 2-col with fence+sync between stores, separate wid==0 blocks
2026-05-28 09:54:19 +00:00
b69a538ab1
test: add fence+sync between 2 tmem_stores
2026-05-28 09:53:10 +00:00
7a21fa4bd8
test: add 2nd tmem_store to column 1
2026-05-28 09:52:05 +00:00
4b129c146e
test: add 1 tmem_load back
2026-05-28 09:51:21 +00:00
61f19ce891
test: skip tmem_load, only store+dealloc
2026-05-28 09:50:48 +00:00
2513e1a692
test: use 64 threads, fence outside warp guard, 1 store
2026-05-28 09:50:09 +00:00
abfe9dbaa1
test: only 1 tmem_store to verify single column works
2026-05-28 09:49:21 +00:00
5795589abc
test: TMEM 4 columns, individual store calls + loop load
2026-05-28 09:48:27 +00:00
8a428f6127
test: TMEM column addressing test (128 cols, store+load)
2026-05-28 09:46:49 +00:00
ee3fe6d6b2
test: tmem_load column 1 only
2026-05-28 09:45:34 +00:00
6c38c6e442
test: read 8 TMEM columns individually (no loop)
2026-05-28 09:44:30 +00:00
bcc6ed114d
test: add 8KB padding after sQ to prevent MMA read overrun
2026-05-28 09:43:17 +00:00
764ed01d6f
test: try M=64 in descriptor + idesc to debug 4x factor
2026-05-28 09:41:50 +00:00
4cb656e583
test: try idesc=0 (same as gau-nernst)
2026-05-28 09:40:19 +00:00
cfba8484da
test: try idesc with N=128 (full extent) + 128 TMEM cols
2026-05-28 09:39:19 +00:00
30f0056b11
test: clean rewrite with SMEM Q/K verification and dot product check
2026-05-28 09:38:26 +00:00
7eb85a71fc
test: add Q SMEM verification output + bf16_to_f32_host
2026-05-28 09:37:07 +00:00
8f23c2aaf6
test: verify SMEM Q layout by reading back canonical data
2026-05-28 09:35:58 +00:00
004046a6a8
test: read only 1 TMEM column after MMA
2026-05-28 09:35:02 +00:00
41128122e3
test: clean rewrite, 32 TMEM cols, MMA N=32, tmem_load loop
2026-05-28 09:33:45 +00:00
58be79957d
test: 32 TMEM cols, add MMA call with N=32, read S from TMEM
2026-05-28 09:32:33 +00:00
22fb861447
test: 2 tmem_stores with syncwarp between
2026-05-28 09:30:37 +00:00
a87f20a4ae
test: just 1 tmem_store, no fence, no loop
2026-05-28 09:29:46 +00:00
2b57f28968
test: zero 128 TMEM columns, skip fence
2026-05-28 09:29:14 +00:00
25c9b70591
test: zero 2 TMEM columns
2026-05-28 09:28:31 +00:00
01c4097ccc
test: zero 32 TMEM columns
2026-05-28 09:27:59 +00:00
3694f63ba4
test: re-enable full TMEM zeroing (128 columns)
2026-05-28 09:27:25 +00:00
c3b6c3a5e6
test: minimal tmem_store debug (1 column + sentinels)
2026-05-28 09:26:52 +00:00
f1aaa50326
test: re-enable TMEM zeroing with tmem_base debug
2026-05-28 09:26:16 +00:00
a7f81331f8
test: skip TMEM zeroing again, alloc+dealloc only
2026-05-28 09:25:37 +00:00
3f5dcd481e
test: zero only 32 TMEM columns
2026-05-28 09:25:05 +00:00
2b1c8ce7df
test: re-enable all TMEM ops (alloc, zero, dealloc)
2026-05-28 09:24:28 +00:00
acc7424a48
test: skip TMEM zeroing, just alloc+dealloc
2026-05-28 09:23:48 +00:00
ca419c52f3
test: re-enable TMEM alloc + zero
2026-05-28 09:23:10 +00:00
09e8ea5933
test: fix compile error, skip TMEM read
2026-05-28 09:22:17 +00:00
69bbc21300
test: skip all TMEM ops, just test SMEM layout + descriptor
2026-05-28 09:21:52 +00:00
a6c0ce51a2
test: skip MMA, just test descriptor values
2026-05-28 09:20:59 +00:00
ea6b42e649
test_umma_qk: add descriptor debug output
2026-05-28 09:20:12 +00:00
0f6907b001
UMMA: fix descriptor + idesc — use gau-nernst tutorial values
...
- LBO = BLOCK_MN * 16 (bytes), SBO = 128 (bytes) for K-major NONE
- Canonical SMEM layout: column-major interleaving of core matrices
- idesc is SEPARATE 32-bit value (was using desc_a>>32 = WRONG)
- idesc encodes dtype/atype/btype/MMA_M/MMA_N
- This was the root cause of 'misaligned address' errors
2026-05-28 09:18:45 +00:00
9b458d2a6c
test_umma_qk: clean rewrite, hardcoded HD=16, explicit core-matrix layout writes
2026-05-28 09:16:37 +00:00
427410d94a
UMMA: Rewrite fmha_umma_desc.cuh with correct K-major core-matrix layout + minimal QK GEMM test
...
- Core-matrix layout: each 8x8 BF16 tile (128B) contiguous in SMEM
- K-major NONE descriptor: LBO=1 (16B), SBO=block_k/8, lbo_mode=0
- MMA K-tiling: tcgen05.mma uses K=16 per call, tile for hd>16
- write_smem_kmajor: converts row-major to core-matrix layout
- write_smem_ktile: extracts single K-tile in core-matrix layout
- test_umma_qk.cu: minimal hd=16, sk=128 test (single MMA call)
- Previous UMMA descriptors were wrong (row-major SMEM, wrong LBO/SBO)
2026-05-28 09:15:40 +00:00
