677245fc5c
fix: LayoutEnum import from cutlass.utils
2026-05-23 06:35:03 +00:00
bd968db5d4
fix import path for tcgen05
2026-05-23 06:34:30 +00:00
afec55ad72
D1.2: TMEM budget probe script for hd=64,128,256,512
2026-05-23 06:33:26 +00:00
5012703bad
fix: add SwiGLU clamping to fused kernel (paper §4.2.3, CG-1)
...
The fused SwiGLU kernel stored swiglu_limit but never applied it.
Paper §4.2.3: gate capped at swiglu_limit, linear clamped to [-limit, +limit].
Non-fused reference path already applies clamping correctly.
Fix: add fmin/fmax clamping in FP32 before BF16 conversion.
2026-05-23 06:32:54 +00:00
580d2f6999
STAGE_D.md: restructure with correctness gaps, TMEM budget, execution order
2026-05-23 06:31:37 +00:00
df43c3232d
D1.1: Fix make_fragment_A — use sP for SMEM source pv_mma
2026-05-23 06:04:44 +00:00
80434d0284
D1.1: Fix PV A-operand construction — compile-time branch for TMEM vs SMEM
2026-05-23 06:03:27 +00:00
d36b727898
D1.1: Add SMEM-P path behind use_smem_p flag (stub: zero sP)
2026-05-23 06:01:02 +00:00
bd0b56dddd
D1.0: Replace HEAD_DIM=64 with self.head_dim constructor parameter
2026-05-23 05:55:03 +00:00
249a581d8a
Add STAGE_D.md: step-by-step runbook and todo list for D1-D5
2026-05-23 05:52:03 +00:00
bfacfeca7b
Rename FmhaV3StageC → FmhaKernel — no dev stage artifacts in production API
2026-05-23 05:45:58 +00:00
787a25516d
Update README: reflect Stage C migration, built indexer/router/compressor, SMEM-P path, CuTeDSL scoping lesson
2026-05-23 05:42:44 +00:00
b39301ebc6
Migrate Stage C kernel (proven cos 0.97) into module - exact copy, no modifications
2026-05-23 05:36:22 +00:00
6c9a9d72f1
Fix TMEM-P offset calc: match Stage C with p_cols_fp32 from pv_mma_tiler[2]
2026-05-23 05:18:37 +00:00
03748c4215
Add missing TMEM fence after P store in TMEM-P path
2026-05-23 05:17:45 +00:00
9c93d655de
Fix p_cols_fp32: use pv_mma_tiler[2] (K-dim) not [1] (N-dim)
2026-05-23 05:16:19 +00:00
32ae44d97d
Fix PV A-operand major mode: K for TMEM-P, a_major for SMEM-P
2026-05-23 05:14:08 +00:00
7df67d5237
Fix CuTeDSL scoping: hoist P store vars out of if block
2026-05-23 05:12:30 +00:00
2addbeed7d
Fix O rescale: use Stage C proven correction_rescale pattern
2026-05-23 05:10:46 +00:00
86f3e9cf32
Fix tOrP0 indexing: 3-dim slice (None,None,kb) not 4-dim
2026-05-23 05:09:19 +00:00
75fec90eef
Fix CuTeDSL scoping: unconditionally define tOrP0 and tCrP
2026-05-23 05:08:10 +00:00
fd157cf38e
Fix CuTeDSL variable scoping: define tOrP0 and tCrP in both branches
2026-05-23 05:07:30 +00:00
2cc9786491
Fix p_tmem_s: use ComposedLayout from make_smem_layout_a, pass as kernel arg
2026-05-23 05:06:45 +00:00
d0869054d5
Consolidate FMHA stages A/B/C into unified kernel module with SMEM-P stub
2026-05-23 05:04:43 +00:00
5af491cd73
WIP: make_tiled_copy_C for P→SMEM
2026-05-23 03:56:56 +00:00
cf080ccf00
fix: cpasync.CopyOp for reg→SMEM
2026-05-23 03:54:49 +00:00
a18c639021
fix: CopyAtomUniversalOp
2026-05-23 03:52:47 +00:00
f869f31625
WIP: tiled copy for P→SMEM (zero fill)
2026-05-23 03:51:58 +00:00
6ac61b69c8
fix: cute.copy(dst, src) order
2026-05-23 03:51:00 +00:00
99f13cf52e
fix: BFloat16 not Float32 for bf16 reg
2026-05-23 03:50:09 +00:00
748873a58c
WIP: P→SMEM write stub (zero fill, proper mapping TODO)
2026-05-23 03:49:05 +00:00
469665f69a
fix: partition_A not partition_S
2026-05-23 03:47:53 +00:00
3ee330a84c
fix: make_smem_layout_epi not make_epilogue_smem_layout
2026-05-23 03:47:09 +00:00
1d8b4aaab3
WIP: SMEM P path for PV (compiles but P write not implemented)
2026-05-23 03:46:01 +00:00
4c3239b9c0
debug: hd=64 with CUDA_LAUNCH_BLOCKING
2026-05-23 03:42:53 +00:00
2e2ac4eb1f
D1: P store as BF16 using PV A-fragment layout (tOrP0)
...
Reverted tP to p_tmem_s.outer (needed for make_fragment_A profile).
P store now writes BF16 to TMEM using tOrP0's layout, matching PV A-fragment reads.
This fixes the layout mismatch at hd>64 where QK C-fragment composition
writes to different TMEM columns than PV A-fragment reads.
2026-05-23 03:42:07 +00:00
902bda5c31
D1: align P store and PV A-fragment layouts via tP
...
Key insight: tP (PV A-fragment base) used p_tmem_s.outer layout,
but P store used QK C-fragment composition layout. These diverge at hd>64.
Fix: tP now uses the same QK C-fragment composition layout (tStP_layout)
as the P store. PV A-fragment is derived from tP, so it automatically
uses the same layout. No double-offset since tP includes P offset.
2026-05-23 03:40:10 +00:00
95cf4159f2
D1: P store as BF16 using PV A-fragment layout
...
- Changed P store from FP32 QK C-fragment layout to BF16 PV A-fragment layout
- rP_bf16_reg stores directly to TMEM using tOrP0 layout
- Ensures softmax writes P to same TMEM columns that PV GEMM reads
2026-05-23 03:38:24 +00:00
e33f582436
D1: P store uses tOrP0.layout (PV A-fragment TMEM layout)
2026-05-23 03:36:40 +00:00
063783dd6b
D1 fix: P store uses PV A-fragment layout (p_tmem_s.outer)
...
CRITICAL BUG: P was stored using QK C-fragment composition layout, but PV
A-fragment reads using p_tmem_s.outer (PV A-operand layout). These layouts
match at hd=64 (cos 0.999998) but diverge at hd>64 (cos 0.784 at hd=128).
The fix: tStP0 and tScP now use p_tmem_s.outer instead of
composition(tStS.layout, (128, p_cols_fp32)). This ensures the softmax
writes P in the same layout that the PV GEMM expects.
2026-05-23 03:35:49 +00:00
4df5dafcc9
D1: test raw unnormalized output via epilogue_tma_store
2026-05-23 03:33:59 +00:00
6dfc06cdef
test: paired atoms epilog from old commit 6ee28d8
2026-05-23 03:32:53 +00:00
e1fc4cee60
D1: paired atoms epilogue (no TMEM round-trip)
...
Replace NO-OP round-trip + normalize + epilogue_tma_store with:
- get_tmem_load_op + get_smem_store_op paired atoms
- One-way TMEM→reg (normalize) →SMEM→GMEM
- Eliminates ~3% error from TMEM layout mismatch
- O rescale disabled (single KV tile only for now)
- Pre-computed TMA partitions outside if blocks
2026-05-23 03:29:51 +00:00
32481f8a2b
d1: sweep hd=64,128,256
2026-05-23 03:26:10 +00:00
3ec7f36e62
fix: use mV.iterator
2026-05-23 03:25:29 +00:00
73f359b565
fix: use mQ not q for LayoutEnum
2026-05-23 03:24:58 +00:00
4203d6ad20
d1: add diagnostic script
2026-05-23 03:24:16 +00:00
b249b8f135
D1: N-tile support for HEAD_DIM>256
...
- pv_n_tile = min(head_dim, 256) — MMA instruction N limit
- n_pv_tiles = head_dim // pv_n_tile — outer loop count
- V FMHA layout uses pv_n_tile (not head_dim) for N-tile slicing
- Test loops over N-tiles at Python level, kernel processes (128, pv_n_tile)
- For hd=512: 2 kernel launches with V[:,0:256] and V[:,256:512]
2026-05-23 03:22:23 +00:00
f2dced88a3
d1: add hd=512 test
2026-05-23 03:20:46 +00:00
06c3df8aad
d1: add quick regression test (hd=64 only)
2026-05-23 03:20:12 +00:00
