test: full FMHA HD=16 with PV GEMM (separate TMEM for P and O)
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@@ -1,6 +1,9 @@
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/**
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* UMMA FMHA — QK + Softmax only, HD=16
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* Stripped down: no V, no PV. Just verify QK→softmax pipeline.
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* Full UMMA FMHA — HD=16, SK=128, T=1 (decode)
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* Q×K^T → softmax → P×V → epilogue
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*
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* TMEM layout: columns 0-127 = P (attention weights), columns 128-159 = O (output)
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* Total TMEM alloc: 256 columns (power of 2, covers both P and O)
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*/
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#include <cuda_runtime.h>
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@@ -17,41 +20,66 @@ using namespace dsv4::kernels::attention;
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static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
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static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
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constexpr int HD = 16, SK = 128, BLOCK_MN = 128;
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constexpr int HD = 16, SK = 128, BLOCK_MN = 128, CORES_MN = 16;
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constexpr int VKT = SK / MMA_K_BF16; // 8 PV K-tiles
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constexpr int V_TILE_SZ = MMA_K_BF16 * HD; // 256 BF16 per V K-tile
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constexpr int TMEM_P_COLS = 128; // P needs 128 columns (128×128)
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constexpr int TMEM_O_COLS = 32; // O needs 16, round up to 32 (power of 2, min 32)
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constexpr int TMEM_TOTAL = 256; // P(128) + O(32) → 256
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__global__ void __launch_bounds__(128)
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test_fmha_softmax_hd16(const bf16_t* q, const bf16_t* k,
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bf16_t* p_out, float* p_scalar, float scale)
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test_fmha_hd16(const bf16_t* q, const bf16_t* k, const bf16_t* v,
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bf16_t* o_out, float* o_scalar, float scale)
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{
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const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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bf16_t* sQ = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
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bf16_t* sK = sQ + 128 * 16 + 4096; // Same padding as working QK test
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float* sQ_row = (float*)(sK + 128 * 16);
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bf16_t* sK = sQ + 128 * 16 + 4096;
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bf16_t* sV_base = sK + 128 * 16; // V K-tiles start here
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float* sQ_row = (float*)(sV_base + VKT * V_TILE_SZ);
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for (int d = tid; d < HD; d += 128) sQ_row[d] = bf16_to_f32(q[d]);
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128);
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// TMEM alloc — 256 columns
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_TOTAL);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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uint32_t tb_o = tb + TMEM_P_COLS; // O starts at column 128
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// Load Q, K
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write_q_to_smem<HD>(sQ, q);
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write_k_to_smem<SK, HD>(sK, k);
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bf16_t* sQ_pad = sQ + 128 * 16;
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for (int i = tid; i < 4096; i += 128) sQ_pad[i] = 0;
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// Load V K-tiles: each (16, 16) canonical
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for (int i = tid; i < VKT * V_TILE_SZ; i += 128) sV_base[i] = 0;
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for (int kt = 0; kt < VKT; kt++) {
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bf16_t* sv = sV_base + kt * V_TILE_SZ;
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for (int i = tid; i < MMA_K_BF16 * HD; i += 128) {
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int r = i / HD, d = i % HD;
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int ck = d / 8, lc = d % 8;
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int tmn = r / 8, lr = r % 8;
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sv[ck * 2 * 64 + tmn * 64 + lr * 8 + lc] = v[d * SK + kt * MMA_K_BF16 + r];
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}
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}
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__syncthreads();
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// QK GEMM
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// ================================================================
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// STEP 1: QK GEMM — Q × K^T → S in TMEM (columns 0-127)
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// ================================================================
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uint64_t desc_q = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ), BLOCK_MN);
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uint64_t desc_k = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK), BLOCK_MN);
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uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
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if (lane == 0) umma_ss_f16(tb, desc_q, desc_k, idesc, false);
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uint32_t idesc_qk = make_idesc(BLOCK_MN, BLOCK_MN);
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if (lane == 0) umma_ss_f16(tb, desc_q, desc_k, idesc_qk, false);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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// Softmax
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// ================================================================
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// STEP 2: Softmax — S (TMEM 0-127) → P (TMEM 0-127)
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// ================================================================
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if (wid == 0) {
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float s_vals[SK], row_max = -INFINITY;
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for (int n = 0; n < SK / 8; n++) {
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@@ -66,7 +94,7 @@ test_fmha_softmax_hd16(const bf16_t* q, const bf16_t* k,
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row_sum = wsum(row_sum);
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if (lane == 0) for (int j=0;j<SK;j++) s_vals[j] /= row_sum;
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// Write P back using 32x32b.x8 stores
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// Write P back to TMEM columns 0-127
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for (int n = 0; n < SK / 8; n++) {
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float p0=(lane==0)?s_vals[n*8+0]:0, p1=(lane==0)?s_vals[n*8+1]:0;
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float p2=(lane==0)?s_vals[n*8+2]:0, p3=(lane==0)?s_vals[n*8+3]:0;
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@@ -78,16 +106,39 @@ test_fmha_softmax_hd16(const bf16_t* q, const bf16_t* k,
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}
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__syncthreads();
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// Read P back
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// ================================================================
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// STEP 3: PV GEMM — P (TMEM 0-127) × V (SMEM) → O (TMEM 128-159)
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// For each PV K-tile kt (K=16):
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// A = P[:, 16*kt:16*kt+16] from TMEM at tb + 16*kt
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// B = V[16*kt:16*kt+16, :] from SMEM at sV_base + kt * V_TILE_SZ
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// C = O (128, 16) accumulated in TMEM at tb_o (column 128)
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// ================================================================
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uint32_t idesc_pv = make_idesc(BLOCK_MN, HD); // M=128, N=16
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for (int kt = 0; kt < VKT; kt++) {
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bf16_t* sv = sV_base + kt * V_TILE_SZ;
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uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sv), MMA_K_BF16);
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uint32_t tmem_a = tb + kt * MMA_K_BF16; // P's K-tile in TMEM
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if (tid == 0) umma_ts_f16(tb_o, tmem_a, dv, idesc_pv, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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}
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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// ================================================================
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// STEP 4: Epilogue — O (TMEM 128-159) → read row 0 → BF16 → GMEM
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// ================================================================
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if (wid == 0) {
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float p_vals[SK];
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for (int n = 0; n < SK / 8; n++) {
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float o_vals[HD];
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for (int n = 0; n < HD / 8; n++) { // 2 iterations for HD=16
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb + n*8));
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb_o + n*8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) for (int c=0;c<8;c++) p_vals[n*8+c] = tmp[c];
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if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c];
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}
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if (lane == 0) for (int j=0;j<SK;j++) p_out[j] = f32_to_bf16(p_vals[j]);
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if (lane == 0) for (int d=0;d<HD;d++) o_out[d] = f32_to_bf16(o_vals[d]);
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}
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__syncthreads();
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@@ -103,57 +154,66 @@ test_fmha_softmax_hd16(const bf16_t* q, const bf16_t* k,
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for (int j=0;j<SK;j++) mx = fmaxf(mx, s[j]);
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float sm = 0.0f;
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for (int j=0;j<SK;j++) { s[j] = expf(s[j]-mx); sm += s[j]; }
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for (int j=0;j<SK;j++) p_scalar[j] = s[j] / sm;
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for (int j=0;j<SK;j++) s[j] /= sm;
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for (int d=0;d<HD;d++) {
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float ov = 0.0f;
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for (int j=0;j<SK;j++) ov += s[j] * bf16_to_f32(v[d*SK+j]);
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o_scalar[d] = ov;
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}
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}
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if (wid == 0) tmem_dealloc(tb, 128);
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if (wid == 0) tmem_dealloc(tb, TMEM_TOTAL);
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}
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int main() {
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printf("=== UMMA FMHA Softmax HD=16 ===\n");
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printf("=== Full UMMA FMHA HD=16 ===\n");
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const float SCALE = 1.0f / sqrtf((float)HD);
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bf16_t* h_q = (bf16_t*)malloc(HD*sizeof(bf16_t));
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bf16_t* h_k = (bf16_t*)malloc(SK*HD*sizeof(bf16_t));
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bf16_t* h_p = (bf16_t*)calloc(SK, sizeof(bf16_t));
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float* h_p_scalar = (float*)calloc(SK, sizeof(float));
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bf16_t* h_v = (bf16_t*)malloc(HD*SK*sizeof(bf16_t));
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bf16_t* h_o = (bf16_t*)calloc(HD, sizeof(bf16_t));
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float* h_o_scalar = (float*)calloc(HD, sizeof(float));
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srand(42);
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for (int d=0;d<HD;d++) h_q[d] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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for (int i=0;i<HD*SK;i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
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bf16_t *d_q,*d_k,*d_p; float *d_p_scalar;
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bf16_t *d_q,*d_k,*d_v,*d_o; float *d_o_scalar;
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cudaMalloc(&d_q, HD*sizeof(bf16_t));
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cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
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cudaMalloc(&d_p, SK*sizeof(bf16_t));
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cudaMalloc(&d_p_scalar, SK*sizeof(float));
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cudaMalloc(&d_v, HD*SK*sizeof(bf16_t));
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cudaMalloc(&d_o, HD*sizeof(bf16_t));
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cudaMalloc(&d_o_scalar, HD*sizeof(float));
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cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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cudaMemcpy(d_v, h_v, HD*SK*sizeof(bf16_t), cudaMemcpyHostToDevice);
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int smem = (4 + 16 + 128*16*2 + 4096*2 + 128*16*2 + 16*4 + 256 + 127) & ~127;
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test_fmha_softmax_hd16<<<1, 128, smem>>>(d_q, d_k, d_p, d_p_scalar, SCALE);
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int smem = (4+16 + 128*16*2+4096 + 128*16*2 + VKT*V_TILE_SZ*2 + 16*4 + 256 + 127) & ~127;
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printf("SMEM: %d bytes (%d KB)\n", smem, smem/1024);
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test_fmha_hd16<<<1, 128, smem>>>(d_q, d_k, d_v, d_o, d_o_scalar, SCALE);
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
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cudaMemcpy(h_p, d_p, SK*sizeof(bf16_t), cudaMemcpyDeviceToHost);
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cudaMemcpy(h_p_scalar, d_p_scalar, SK*sizeof(float), cudaMemcpyDeviceToHost);
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cudaMemcpy(h_o, d_o, HD*sizeof(bf16_t), cudaMemcpyDeviceToHost);
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cudaMemcpy(h_o_scalar, d_o_scalar, HD*sizeof(float), cudaMemcpyDeviceToHost);
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printf("P[0,0..7] MMA: "); for(int j=0;j<8;j++) printf("%.6f ",bf16_to_f32_host(h_p[j])); printf("\n");
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printf("P[0,0..7] ref: "); for(int j=0;j<8;j++) printf("%.6f ",h_p_scalar[j]); printf("\n");
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printf("O[0..15] MMA: "); for(int d=0;d<HD;d++) printf("%.6f ",bf16_to_f32_host(h_o[d])); printf("\n");
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printf("O[0..15] ref: "); for(int d=0;d<HD;d++) printf("%.6f ",h_o_scalar[d]); printf("\n");
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float max_diff=0, max_val=0;
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for (int j=0;j<SK;j++) {
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max_diff = fmaxf(max_diff, fabsf(bf16_to_f32_host(h_p[j]) - h_p_scalar[j]));
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max_val = fmaxf(max_val, fabsf(h_p_scalar[j]));
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for (int d=0;d<HD;d++) {
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max_diff = fmaxf(max_diff, fabsf(bf16_to_f32_host(h_o[d]) - h_o_scalar[d]));
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max_val = fmaxf(max_val, fabsf(h_o_scalar[d]));
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}
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float rel_err = max_val>0 ? max_diff/max_val : max_diff;
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float p_sum = 0.0f;
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for (int j=0;j<SK;j++) p_sum += bf16_to_f32_host(h_p[j]);
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printf("Max rel err: %.8f | sum: %.6f\n", rel_err, p_sum);
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printf("Test %s\n", (rel_err < 0.01f && fabsf(p_sum-1.0f) < 0.01f) ? "PASSED" : "FAILED");
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printf("Max rel err: %.8f\n", rel_err);
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printf("Test %s\n", rel_err < 0.05f ? "PASSED" : "FAILED");
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cudaFree(d_q); cudaFree(d_k); cudaFree(d_p); cudaFree(d_p_scalar);
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free(h_q); free(h_k); free(h_p); free(h_p_scalar);
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return (rel_err < 0.01f && fabsf(p_sum-1.0f) < 0.01f) ? 0 : 1;
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cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_o_scalar);
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free(h_q); free(h_k); free(h_v); free(h_o); free(h_o_scalar);
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return rel_err < 0.05f ? 0 : 1;
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}
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