From f62772992bdd287e492e5188160019fed5fbf35d Mon Sep 17 00:00:00 2001 From: biondizzle Date: Thu, 28 May 2026 13:05:27 +0000 Subject: [PATCH] test: full FMHA HD=16 with PV GEMM (separate TMEM for P and O) --- tests/unit/test_fmha_hd16.cu | 146 ++++++++++++++++++++++++----------- 1 file changed, 103 insertions(+), 43 deletions(-) diff --git a/tests/unit/test_fmha_hd16.cu b/tests/unit/test_fmha_hd16.cu index b08e21cd..c407c0d8 100644 --- a/tests/unit/test_fmha_hd16.cu +++ b/tests/unit/test_fmha_hd16.cu @@ -1,6 +1,9 @@ /** - * UMMA FMHA — QK + Softmax only, HD=16 - * Stripped down: no V, no PV. Just verify QK→softmax pipeline. + * Full UMMA FMHA — HD=16, SK=128, T=1 (decode) + * Q×K^T → softmax → P×V → epilogue + * + * TMEM layout: columns 0-127 = P (attention weights), columns 128-159 = O (output) + * Total TMEM alloc: 256 columns (power of 2, covers both P and O) */ #include @@ -17,41 +20,66 @@ using namespace dsv4::kernels::attention; static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); } static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; } -constexpr int HD = 16, SK = 128, BLOCK_MN = 128; +constexpr int HD = 16, SK = 128, BLOCK_MN = 128, CORES_MN = 16; +constexpr int VKT = SK / MMA_K_BF16; // 8 PV K-tiles +constexpr int V_TILE_SZ = MMA_K_BF16 * HD; // 256 BF16 per V K-tile +constexpr int TMEM_P_COLS = 128; // P needs 128 columns (128×128) +constexpr int TMEM_O_COLS = 32; // O needs 16, round up to 32 (power of 2, min 32) +constexpr int TMEM_TOTAL = 256; // P(128) + O(32) → 256 __global__ void __launch_bounds__(128) -test_fmha_softmax_hd16(const bf16_t* q, const bf16_t* k, - bf16_t* p_out, float* p_scalar, float scale) +test_fmha_hd16(const bf16_t* q, const bf16_t* k, const bf16_t* v, + bf16_t* o_out, float* o_scalar, float scale) { const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32; extern __shared__ char sbuf[]; uint32_t* sTmemBase = (uint32_t*)sbuf; bf16_t* sQ = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15); - bf16_t* sK = sQ + 128 * 16 + 4096; // Same padding as working QK test - float* sQ_row = (float*)(sK + 128 * 16); + bf16_t* sK = sQ + 128 * 16 + 4096; + bf16_t* sV_base = sK + 128 * 16; // V K-tiles start here + float* sQ_row = (float*)(sV_base + VKT * V_TILE_SZ); for (int d = tid; d < HD; d += 128) sQ_row[d] = bf16_to_f32(q[d]); - if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128); + // TMEM alloc — 256 columns + if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_TOTAL); __syncthreads(); uint32_t tb = *sTmemBase; + uint32_t tb_o = tb + TMEM_P_COLS; // O starts at column 128 + // Load Q, K write_q_to_smem(sQ, q); write_k_to_smem(sK, k); bf16_t* sQ_pad = sQ + 128 * 16; for (int i = tid; i < 4096; i += 128) sQ_pad[i] = 0; + + // Load V K-tiles: each (16, 16) canonical + for (int i = tid; i < VKT * V_TILE_SZ; i += 128) sV_base[i] = 0; + for (int kt = 0; kt < VKT; kt++) { + bf16_t* sv = sV_base + kt * V_TILE_SZ; + for (int i = tid; i < MMA_K_BF16 * HD; i += 128) { + int r = i / HD, d = i % HD; + int ck = d / 8, lc = d % 8; + int tmn = r / 8, lr = r % 8; + sv[ck * 2 * 64 + tmn * 64 + lr * 8 + lc] = v[d * SK + kt * MMA_K_BF16 + r]; + } + } __syncthreads(); - // QK GEMM + // ================================================================ + // STEP 1: QK GEMM — Q × K^T → S in TMEM (columns 0-127) + // ================================================================ uint64_t desc_q = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ), BLOCK_MN); uint64_t desc_k = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK), BLOCK_MN); - uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN); - if (lane == 0) umma_ss_f16(tb, desc_q, desc_k, idesc, false); + uint32_t idesc_qk = make_idesc(BLOCK_MN, BLOCK_MN); + if (lane == 0) umma_ss_f16(tb, desc_q, desc_k, idesc_qk, false); asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory"); __syncthreads(); - // Softmax + // ================================================================ + // STEP 2: Softmax — S (TMEM 0-127) → P (TMEM 0-127) + // ================================================================ if (wid == 0) { float s_vals[SK], row_max = -INFINITY; for (int n = 0; n < SK / 8; n++) { @@ -66,7 +94,7 @@ test_fmha_softmax_hd16(const bf16_t* q, const bf16_t* k, row_sum = wsum(row_sum); if (lane == 0) for (int j=0;j 0); + asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory"); + __syncthreads(); + } + asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory"); + __syncthreads(); + + // ================================================================ + // STEP 4: Epilogue — O (TMEM 128-159) → read row 0 → BF16 → GMEM + // ================================================================ if (wid == 0) { - float p_vals[SK]; - for (int n = 0; n < SK / 8; n++) { + float o_vals[HD]; + for (int n = 0; n < HD / 8; n++) { // 2 iterations for HD=16 float tmp[8]; - asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb + n*8)); + asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb_o + n*8)); asm volatile("tcgen05.wait::ld.sync.aligned;"); - if (lane == 0) for (int c=0;c<8;c++) p_vals[n*8+c] = tmp[c]; + if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c]; } - if (lane == 0) for (int j=0;j>>(d_q, d_k, d_p, d_p_scalar, SCALE); + int smem = (4+16 + 128*16*2+4096 + 128*16*2 + VKT*V_TILE_SZ*2 + 16*4 + 256 + 127) & ~127; + printf("SMEM: %d bytes (%d KB)\n", smem, smem/1024); + + test_fmha_hd16<<<1, 128, smem>>>(d_q, d_k, d_v, d_o, d_o_scalar, SCALE); cudaError_t err = cudaDeviceSynchronize(); if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; } - cudaMemcpy(h_p, d_p, SK*sizeof(bf16_t), cudaMemcpyDeviceToHost); - cudaMemcpy(h_p_scalar, d_p_scalar, SK*sizeof(float), cudaMemcpyDeviceToHost); + cudaMemcpy(h_o, d_o, HD*sizeof(bf16_t), cudaMemcpyDeviceToHost); + cudaMemcpy(h_o_scalar, d_o_scalar, HD*sizeof(float), cudaMemcpyDeviceToHost); - printf("P[0,0..7] MMA: "); for(int j=0;j<8;j++) printf("%.6f ",bf16_to_f32_host(h_p[j])); printf("\n"); - printf("P[0,0..7] ref: "); for(int j=0;j<8;j++) printf("%.6f ",h_p_scalar[j]); printf("\n"); + printf("O[0..15] MMA: "); for(int d=0;d0 ? max_diff/max_val : max_diff; - float p_sum = 0.0f; - for (int j=0;j