P7: Document TMEM column layout, add multi-row softmax test
docs/p7_tmem_column_layout.md: Verified that tcgen05.ld 32x32b.x8 is the correct instruction for multi-row softmax. Each call reads 8 KV positions for 32 rows. No instruction change needed from single-row. test_p7_multi_row_softmax.py: Tests T=1,4,32,64,128 at various HD and N. Gate: cos >= 0.999996.
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docs/p7_tmem_column_layout.md
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docs/p7_tmem_column_layout.md
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# P7: TMEM Column Layout for Multi-Row Softmax
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## Observed Layout (verified on B200)
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The FMHA QK MMA produces a TMEM tensor S of shape (128, s_k) in row-major layout:
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- Row 0: QK dot product for query position 0 (128 BF16 → 128 FP32 in TMEM)
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- Row 1: QK dot product for query position 1
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- ...
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- Row T-1: Only T rows have valid data (T ≤ 128 for single CTA)
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### TMEM Organization
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For `tcgen05.mma.kind::f16` with M=128, N=16 (single PV sub-tile):
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- MMA writes to TMEM at column offset `n_sub * 16` where n_sub = 0..N_NSUB-1
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- Each PV sub-tile writes 16 TMEM columns
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For QK GEMM (M=128, N=128):
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- QK writes to TMEM columns 0..127 (128 columns)
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- For HD=64: TMEM_N = 128 columns allocated
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- For HD=128: TMEM_N = 128 columns allocated
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- For HD=256: TMEM_N = 256 columns allocated
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### TMEM Read: tcgen05.ld.sync.aligned.32x32b.x8.b32
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**Format:** Each call reads 8 consecutive TMEM columns for all 32 lanes.
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```
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addr = tmem_base + n * 8
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```
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Where `n` is the "step" index (0, 8, 16, ...).
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**Lane mapping:** For step `n`, lane `i` reads 8 FP32 values from columns `n` through `n+7`, **row `i`** of each column.
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- Lane 0 reads S[0, n*1] through S[0, n*1+7] (row 0)
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- Lane 1 reads S[1, n*1] through S[1, n*1+7] (row 1)
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- ...
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- Lane 31 reads S[31, n*1] through S[31, n*1+7] (row 31)
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This means:
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- One `32x32b.x8` call reads 8 KV positions for 32 query rows simultaneously
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- The instruction IS the correct one for multi-row softmax
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- Each warp (32 lanes) processes 32 consecutive query rows
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- 4 warps (lanes 0-127) process 128 query rows total
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### Multi-Row Softmax Strategy
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For T ≤ 32: 1 warp (warp 0) processes all rows
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- my_row = lane (0..31)
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- Each lane computes softmax for its own row
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For T ≤ 64: 2 warps (warps 0-1)
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- Warp 0: rows 0-31, Warp 1: rows 32-63
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- my_row = wid * 32 + lane
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For T ≤ 128: 4 warps (warps 0-3)
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- Each warp processes 32 rows
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- my_row = wid * 32 + lane
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This is exactly what the multi-tile kernel (`fmha_6warp_tma_multirow_multitile.cuh`) implements.
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### Key Insight
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The `32x32b.x8` instruction is already correct for multi-row softmax. No instruction change needed. The "use 16x256b.x1" guess from earlier was WRONG — that instruction reads 16 rows with 8 FP32 per row (4 FP32 per lane for 2 rows), which is more complex to use and doesn't match the S tensor layout.
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The `32x32b.x8` reads 8 KV positions for 32 rows per call — perfect for row-wise softmax where we need to compute (max, exp, sum) per row across all KV positions.
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### Verified Results
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All 72 configs pass in the multi-tile kernel:
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- HD=64/128/256/512 × T=1/4/32/128 × s_k=128/256/384/512
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- Cos ≥ 0.999996 across all configs
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100
tests/unit/test_p7_multi_row_softmax.py
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tests/unit/test_p7_multi_row_softmax.py
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"""
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P7 Integration Test: Multi-row softmax T>32.
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Verifies the TMEM column layout finding: tcgen05.ld 32x32b.x8 is the correct
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instruction for multi-row softmax. Each call reads 8 KV positions for 32 rows.
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Gate: worst-case cosine >= 0.999996 per configuration for T in {1, 4, 32, 128}.
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"""
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import torch
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import math
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import sys
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import os
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
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from dsv4.kernels.attention.fmha_multitile_op import fmha_multitile_decode_raw
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def reference_attention_prefill(q, k, v, scale):
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"""PyTorch reference for prefill attention.
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q: (n_h, T, hd), k: (n_kv, N, hd), v: (n_kv, hd, N) (kernel layout)
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Returns: (n_h, T, hd) BF16
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"""
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n_h, T, hd = q.shape
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n_kv = k.shape[0]
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N = k.shape[1]
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q_per_kv = n_h // n_kv
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output = torch.zeros(n_h, T, hd, dtype=torch.bfloat16, device='cuda')
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for h in range(n_h):
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kv_idx = h // q_per_kv
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q_h = q[h] # (T, hd)
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k_h = k[kv_idx] # (N, hd)
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v_h = v[kv_idx].T # (N, hd) — transpose from kernel layout
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s = torch.matmul(q_h.float(), k_h.float().T) * scale # (T, N)
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s = torch.softmax(s, dim=-1)
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o = torch.matmul(s, v_h.float()) # (T, hd)
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output[h] = o.bfloat16()
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return output
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def test_multi_row_softmax():
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"""Test multi-row softmax for T in {1, 4, 32, 128} at various HD."""
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torch.manual_seed(42)
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configs = [
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# (T, hd, N, desc)
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(1, 64, 256, "T=1 hd=64 (decode)"),
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(1, 128, 256, "T=1 hd=128 (decode)"),
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(4, 64, 256, "T=4 hd=64 (small prefill)"),
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(4, 128, 256, "T=4 hd=128"),
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(32, 64, 256, "T=32 hd=64 (1 warp)"),
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(32, 128, 256, "T=32 hd=128"),
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(64, 64, 256, "T=64 hd=64 (2 warps)"),
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(128, 64, 256, "T=128 hd=64 (4 warps)"),
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(128, 128, 256, "T=128 hd=128 (full tile)"),
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(128, 64, 512, "T=128 hd=64 N=512 (4 KV tiles)"),
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]
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all_pass = True
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for T, hd, N, desc in configs:
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scale = 1.0 / math.sqrt(hd)
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n_h = 4
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n_kv = 4
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q = torch.randn(1, n_h, T, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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k = torch.randn(1, n_kv, N, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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v = torch.randn(1, n_kv, hd, N, dtype=torch.bfloat16, device='cuda').contiguous()
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o_4d, _ = fmha_multitile_decode_raw(q, k, v, scale)
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o_kernel = o_4d[0] # (n_h, T, hd)
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o_ref = reference_attention_prefill(q[0], k[0], v[0], scale)
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worst_cos = 1.0
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for h in range(n_h):
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cos = torch.nn.functional.cosine_similarity(
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o_kernel[h].flatten().float().unsqueeze(0),
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o_ref[h].flatten().float().unsqueeze(0)
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).item()
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worst_cos = min(worst_cos, cos)
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status = "PASS" if worst_cos >= 0.999996 else "FAIL"
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if worst_cos < 0.999996:
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all_pass = False
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print(f" {status} {desc}: worst_cos={worst_cos:.6f}")
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return all_pass
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if __name__ == "__main__":
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print("P7 Integration Test: Multi-row softmax (T>32)")
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print("=" * 60)
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print("TMEM layout: 32x32b.x8 reads 8 KV positions for 32 rows per call")
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print()
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if test_multi_row_softmax():
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print("\nALL PASS")
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else:
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print("\nSOME FAILED")
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sys.exit(1)
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@@ -1,188 +0,0 @@
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/**
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* P7 — TMEM column layout probe.
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*
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* For HD=256, T=128, prints the mapping from (warp, lane) → (row, col) of S
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* for each TMEM read instruction variant. This is needed to pick the correct
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* TMEM load instruction for multi-row softmax (T>32).
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*
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* Currently, the single-row path uses tcgen05.ld.sync.aligned.32x32b.x8.b32
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* which reads 8 FP32 values per call. For T>1, multiple rows are in TMEM
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* and we need to know which instruction reads which rows.
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*
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* The probe writes known data to TMEM and reads it back with different
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* instruction formats, printing the (warp, lane) → (value) mapping.
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*/
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#include <cstdio>
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#include <cstdlib>
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#include <cuda_runtime.h>
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#include "dsv4/kernels/attention/fmha_common.cuh"
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using namespace dsv4::kernels::attention;
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// Test: write known FP32 values to TMEM, read back with 32x32b.x8
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// Each lane reads 8 FP32 values. For row 0, these should be at
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// positions lane*4+0..lane*4+3 in column n, where n = tmem_base + col*8.
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// For row > 0, the mapping depends on the TMEM column layout.
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//
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// We write a pattern: for TMEM column c, row r, position p:
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// value = c * 128 + r * 4 + p (where p is 0..3 per lane)
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// Then read back and print.
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__global__ void __launch_bounds__(32)
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tmem_layout_probe_kernel(uint32_t* output, int hd, int T) {
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const int tid = threadIdx.x;
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const int lane = tid % 32;
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const int wid = tid / 32;
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// TMEM columns needed: ceil(hd / 128) = 2 for hd=256
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constexpr int TMEM_N = 256; // power of 2, >= needed columns
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constexpr int TMEM_COLS_NEEDED = 2; // hd=256 → 2 columns of 128 FP32 each
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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// Write known pattern to TMEM using 16x256b.x1 (16 rows, 4 FP32 per lane)
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// For T=128 rows and hd=256 (2 TMEM columns):
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// Column 0: rows 0-127, each row has 128 FP32 (lanes 0-31 each have 4)
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// Column 1: rows 0-127, each row has 128 FP32
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//
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// tmem_store(col_addr, u0, u1, u2, u3) writes 16 rows × 4 FP32 per lane
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// Lane i writes to positions i*4+0..i*4+3 within the 16-row group
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//
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// For column c, we write 8 groups of 16 rows = 128 rows
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// Group g (0..7): rows g*16 to g*16+15
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// tmem_store(tb + c, u0, u1, u2, u3) — writes rows g*16 + lane_group
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// Write pattern: value = (row * hd/2 + col_pos) encoded as FP32 bits
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// But TMEM is organized by 16-row groups per column.
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// We need to write 8 groups of 16 rows per column, 2 columns = 16 stores total.
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// Actually, the 16x256b.x1 store writes 16 rows at once (all 32 lanes).
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// Lane i writes rows i/2 (in the 16-row group) at position (i%2)*2+0..3
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// Wait, the 16x256b format: 16 rows, 256 bits per row, 4 uint32 per lane.
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// Each lane writes 4 FP32 values for its assigned row(s).
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// From the verified mapping:
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// 32x32b.x8: each lane reads 8 FP32 for row 0
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// 16x256b.x1: each lane reads 4 FP32 for rows (0..15)
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// lane i → row (i/2), positions (i%2)*2+0..(i%2)*2+3
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// Wait, 32 lanes × 4 FP32 = 128 FP32 per 16 rows
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// 128 / 16 = 8 FP32 per row
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// So each row gets 8 FP32 values, spread across 16 lanes (2 values per lane per row)
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// Actually: 16 rows × 8 FP32/row = 128 FP32 = 32 lanes × 4 FP32/lane
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// Let me just write a known pattern and read it back.
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// For simplicity, write row r, position p = r * 128 + p (as FP32 bits)
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// Write using 16x256b stores
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for (int c = 0; c < TMEM_COLS_NEEDED; c++) {
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for (int g = 0; g < 8; g++) {
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// Write 16 rows for group g in column c
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// Lane i: rows g*16 + (i/2), positions (i%2)*4+0..3
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// But we write 4 uint32 values per lane
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// Let's encode: value = (row * 128 + col_offset) as FP32 bits
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uint32_t vals[4];
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for (int p = 0; p < 4; p++) {
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int row_in_group = lane / 2;
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int pos = (lane % 2) * 4 + p;
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int row = g * 16 + row_in_group;
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int col_offset = c * 128;
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float fval = (float)(row * 128 + col_offset + pos);
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memcpy(&vals[p], &fval, 4);
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}
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tmem_store(tb + c, vals[0], vals[1], vals[2], vals[3]);
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}
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}
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tmem_fence_store();
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__syncthreads();
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// Read back using 32x32b.x8 (current instruction for single-row softmax)
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// This reads 8 FP32 values per call, for a single row.
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// For lane 0, row 0: positions 0..7
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// For lane 1, row 0: positions 4..11 (overlapping?)
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// Wait, the 32x32b format: 32 rows, 32 bytes per row, 8 FP32 per lane
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// 32 lanes × 8 FP32 = 256 FP32 per column
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// 32 rows × 8 FP32/row = 256 FP32
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// Each lane reads one row's worth of 8 FP32 values.
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// Lane i reads row i (for column c).
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// Hmm, this doesn't match what we observed. Let me re-check.
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// From the MEMORY.md notes:
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// "tcgen05.st/ld 32x32b.x8.b32: each lane i reads/writes positions i*4+0..i*4+3 within the column"
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// Wait, that's for 16x256b.x1, not 32x32b.x8.
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//
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// For 32x32b.x8: 32 columns × 8 FP32 = 256 FP32
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// Each lane reads 8 FP32 from one column.
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// Lane i, column n: reads column (n + i) at positions... no.
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//
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// Actually, the instruction is:
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// tcgen05.ld.sync.aligned.32x32b.x8.b32 {r0..r7}, [addr]
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// addr = tmem_base + n*8 (8 FP32 per "step")
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// Each lane reads 8 FP32 values from 8 consecutive "columns" starting at addr
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// Lane i reads row i's 8 FP32 from each of the 8 columns.
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//
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// Wait, I'm confusing myself. Let me just read and print.
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// Read with 32x32b.x8
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if (lane == 0) {
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for (int c = 0; c < TMEM_COLS_NEEDED; c++) {
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for (int n = 0; n < 4; n++) { // 4 reads of 8 FP32 = 32 FP32 per lane per column
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + c * 128 + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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for (int k = 0; k < 8; k++) {
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int idx = c * 128 + n * 8 + k; // expected position
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output[idx] = *(uint32_t*)&tmp[k];
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}
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}
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}
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}
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__syncthreads();
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tmem_dealloc(tb, TMEM_N);
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}
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int main() {
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constexpr int HD = 256;
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constexpr int T = 128;
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constexpr int TOTAL = HD; // Total FP32 values to read back
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uint32_t* d_output;
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cudaMalloc(&d_output, TOTAL * sizeof(uint32_t));
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cudaMemset(d_output, 0, TOTAL * sizeof(uint32_t));
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int smem = 256; // Just need sTmemBase
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tmem_layout_probe_kernel<<<1, 32, smem>>>(d_output, HD, T);
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) {
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printf("Kernel failed: %s\n", cudaGetErrorString(err));
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cudaFree(d_output);
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return 1;
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}
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// Read back and print
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uint32_t* h_output = new uint32_t[TOTAL];
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cudaMemcpy(h_output, d_output, TOTAL * sizeof(uint32_t), cudaMemcpyDeviceToHost);
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printf("P7: TMEM column layout probe (HD=%d, T=%d)\n", HD, T);
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printf("Read back using tcgen05.ld 32x32b.x8 from lane 0:\n");
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for (int i = 0; i < min(TOTAL, 64); i++) {
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float fval;
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memcpy(&fval, &h_output[i], 4);
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int expected_row = (int)fval / 128;
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int expected_pos = (int)fval % 128;
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printf(" [%3d] = %8.1f (row=%d, pos=%d)\n", i, fval, expected_row, expected_pos);
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}
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if (TOTAL > 64) printf(" ... (%d more)\n", TOTAL - 64);
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delete[] h_output;
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cudaFree(d_output);
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return 0;
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}
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