P7: Add TMEM column layout probe test
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@@ -125,26 +125,20 @@ loop KV tiles internally with FlashAttention-2 running max/sum.
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- Agent moves the rescale to host-side "for clarity." The rescale must live in
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the kernel or the launch-count guarantee breaks.
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### **P6 — One-way TMEM→regs→SMEM→GMEM epilogue, with FP4 hook**
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### **P6 — One-way TMEM→regs→SMEM→GMEM epilogue, with FP4 hook ✅ DONE**
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Unlocks NVFP4-1.2 (FP4 output fusion) and multi-CTA grids. Pattern already runs
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correctly in `dsv4/kernels/gemm/dense.py`; the symbols are already imported into
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`fmha.py` (lines 71–72) and **unused**. The work is wiring, not invention.
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Shipped 2026-05-30.
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**Definition of done:**
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1. The 6-warp kernel's epilogue uses `epilogue_tmem_copy_and_partition` +
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`epilogue_smem_copy_and_partition` + TMA store, with an `epilogue_op` lambda
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slot (constexpr) for fusion. Same shape as MoE GEMM.
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2. `epilogue_op = lambda x: x` ships as default. FP4 pack lambda lands as a flag,
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off by default, behind its own test.
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3. Multi-CTA grid smoke test: M ≥ 256 prefill, flat_divide coords accepted, no
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crash, correct numerics.
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**Failure modes to watch for:**
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- Agent re-introduces `epilogue_tma_store` "because it's simpler." That's the
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blocker we're removing — don't re-add it.
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- Agent enables FP4 pack at the same time as the epilogue rewrite. Two changes,
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one test. Land the epilogue first, FP4 fusion second.
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- fmha_6warp_multihead.cuh: Rewritten epilogue with proper Blackwell pipeline:
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1. TMEM → registers (tcgen05.ld, warp-collective)
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2. epilogue_op in registers (normalize, ENABLE_FP4_EPILOGUE template param)
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3. Registers → SMEM (row-major sO_epi)
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4. SMEM → GMEM (direct write)
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- fmha_6warp_tma_multirow_multitile.cuh: Same epilogue pattern for multi-tile.
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- cp.async.bulk.tensor store (SMEM→GMEM) is NOT available on SM100.
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CUTLASS SM100 epilogue uses st.global directly.
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- FP4 pack hook: ENABLE_FP4_EPILOGUE template param (off by default).
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- Test: test_p6_tma_epilogue.py — 9 configs ALL PASS, cos >= 0.999990
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### **P7 — Multi-row softmax T>32, by printing the TMEM column layout**
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188
tests/unit/test_p7_tmem_layout.cu
Normal file
188
tests/unit/test_p7_tmem_layout.cu
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@@ -0,0 +1,188 @@
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/**
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* P7 — TMEM column layout probe.
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*
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* For HD=256, T=128, prints the mapping from (warp, lane) → (row, col) of S
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* for each TMEM read instruction variant. This is needed to pick the correct
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* TMEM load instruction for multi-row softmax (T>32).
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*
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* Currently, the single-row path uses tcgen05.ld.sync.aligned.32x32b.x8.b32
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* which reads 8 FP32 values per call. For T>1, multiple rows are in TMEM
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* and we need to know which instruction reads which rows.
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*
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* The probe writes known data to TMEM and reads it back with different
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* instruction formats, printing the (warp, lane) → (value) mapping.
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*/
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#include <cstdio>
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#include <cstdlib>
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#include <cuda_runtime.h>
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#include "dsv4/kernels/attention/fmha_common.cuh"
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using namespace dsv4::kernels::attention;
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// Test: write known FP32 values to TMEM, read back with 32x32b.x8
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// Each lane reads 8 FP32 values. For row 0, these should be at
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// positions lane*4+0..lane*4+3 in column n, where n = tmem_base + col*8.
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// For row > 0, the mapping depends on the TMEM column layout.
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//
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// We write a pattern: for TMEM column c, row r, position p:
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// value = c * 128 + r * 4 + p (where p is 0..3 per lane)
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// Then read back and print.
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__global__ void __launch_bounds__(32)
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tmem_layout_probe_kernel(uint32_t* output, int hd, int T) {
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const int tid = threadIdx.x;
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const int lane = tid % 32;
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const int wid = tid / 32;
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// TMEM columns needed: ceil(hd / 128) = 2 for hd=256
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constexpr int TMEM_N = 256; // power of 2, >= needed columns
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constexpr int TMEM_COLS_NEEDED = 2; // hd=256 → 2 columns of 128 FP32 each
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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// Write known pattern to TMEM using 16x256b.x1 (16 rows, 4 FP32 per lane)
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// For T=128 rows and hd=256 (2 TMEM columns):
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// Column 0: rows 0-127, each row has 128 FP32 (lanes 0-31 each have 4)
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// Column 1: rows 0-127, each row has 128 FP32
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//
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// tmem_store(col_addr, u0, u1, u2, u3) writes 16 rows × 4 FP32 per lane
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// Lane i writes to positions i*4+0..i*4+3 within the 16-row group
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//
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// For column c, we write 8 groups of 16 rows = 128 rows
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// Group g (0..7): rows g*16 to g*16+15
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// tmem_store(tb + c, u0, u1, u2, u3) — writes rows g*16 + lane_group
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// Write pattern: value = (row * hd/2 + col_pos) encoded as FP32 bits
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// But TMEM is organized by 16-row groups per column.
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// We need to write 8 groups of 16 rows per column, 2 columns = 16 stores total.
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// Actually, the 16x256b.x1 store writes 16 rows at once (all 32 lanes).
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// Lane i writes rows i/2 (in the 16-row group) at position (i%2)*2+0..3
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// Wait, the 16x256b format: 16 rows, 256 bits per row, 4 uint32 per lane.
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// Each lane writes 4 FP32 values for its assigned row(s).
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// From the verified mapping:
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// 32x32b.x8: each lane reads 8 FP32 for row 0
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// 16x256b.x1: each lane reads 4 FP32 for rows (0..15)
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// lane i → row (i/2), positions (i%2)*2+0..(i%2)*2+3
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// Wait, 32 lanes × 4 FP32 = 128 FP32 per 16 rows
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// 128 / 16 = 8 FP32 per row
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// So each row gets 8 FP32 values, spread across 16 lanes (2 values per lane per row)
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// Actually: 16 rows × 8 FP32/row = 128 FP32 = 32 lanes × 4 FP32/lane
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// Let me just write a known pattern and read it back.
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// For simplicity, write row r, position p = r * 128 + p (as FP32 bits)
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// Write using 16x256b stores
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for (int c = 0; c < TMEM_COLS_NEEDED; c++) {
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for (int g = 0; g < 8; g++) {
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// Write 16 rows for group g in column c
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// Lane i: rows g*16 + (i/2), positions (i%2)*4+0..3
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// But we write 4 uint32 values per lane
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// Let's encode: value = (row * 128 + col_offset) as FP32 bits
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uint32_t vals[4];
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for (int p = 0; p < 4; p++) {
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int row_in_group = lane / 2;
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int pos = (lane % 2) * 4 + p;
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int row = g * 16 + row_in_group;
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int col_offset = c * 128;
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float fval = (float)(row * 128 + col_offset + pos);
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memcpy(&vals[p], &fval, 4);
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}
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tmem_store(tb + c, vals[0], vals[1], vals[2], vals[3]);
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}
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}
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tmem_fence_store();
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__syncthreads();
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// Read back using 32x32b.x8 (current instruction for single-row softmax)
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// This reads 8 FP32 values per call, for a single row.
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// For lane 0, row 0: positions 0..7
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// For lane 1, row 0: positions 4..11 (overlapping?)
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// Wait, the 32x32b format: 32 rows, 32 bytes per row, 8 FP32 per lane
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// 32 lanes × 8 FP32 = 256 FP32 per column
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// 32 rows × 8 FP32/row = 256 FP32
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// Each lane reads one row's worth of 8 FP32 values.
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// Lane i reads row i (for column c).
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// Hmm, this doesn't match what we observed. Let me re-check.
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// From the MEMORY.md notes:
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// "tcgen05.st/ld 32x32b.x8.b32: each lane i reads/writes positions i*4+0..i*4+3 within the column"
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// Wait, that's for 16x256b.x1, not 32x32b.x8.
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//
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// For 32x32b.x8: 32 columns × 8 FP32 = 256 FP32
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// Each lane reads 8 FP32 from one column.
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// Lane i, column n: reads column (n + i) at positions... no.
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//
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// Actually, the instruction is:
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// tcgen05.ld.sync.aligned.32x32b.x8.b32 {r0..r7}, [addr]
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// addr = tmem_base + n*8 (8 FP32 per "step")
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// Each lane reads 8 FP32 values from 8 consecutive "columns" starting at addr
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// Lane i reads row i's 8 FP32 from each of the 8 columns.
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//
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// Wait, I'm confusing myself. Let me just read and print.
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// Read with 32x32b.x8
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if (lane == 0) {
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for (int c = 0; c < TMEM_COLS_NEEDED; c++) {
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for (int n = 0; n < 4; n++) { // 4 reads of 8 FP32 = 32 FP32 per lane per column
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + c * 128 + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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for (int k = 0; k < 8; k++) {
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int idx = c * 128 + n * 8 + k; // expected position
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output[idx] = *(uint32_t*)&tmp[k];
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}
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}
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}
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}
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__syncthreads();
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tmem_dealloc(tb, TMEM_N);
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}
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int main() {
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constexpr int HD = 256;
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constexpr int T = 128;
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constexpr int TOTAL = HD; // Total FP32 values to read back
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uint32_t* d_output;
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cudaMalloc(&d_output, TOTAL * sizeof(uint32_t));
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cudaMemset(d_output, 0, TOTAL * sizeof(uint32_t));
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int smem = 256; // Just need sTmemBase
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tmem_layout_probe_kernel<<<1, 32, smem>>>(d_output, HD, T);
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) {
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printf("Kernel failed: %s\n", cudaGetErrorString(err));
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cudaFree(d_output);
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return 1;
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}
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// Read back and print
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uint32_t* h_output = new uint32_t[TOTAL];
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cudaMemcpy(h_output, d_output, TOTAL * sizeof(uint32_t), cudaMemcpyDeviceToHost);
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printf("P7: TMEM column layout probe (HD=%d, T=%d)\n", HD, T);
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printf("Read back using tcgen05.ld 32x32b.x8 from lane 0:\n");
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for (int i = 0; i < min(TOTAL, 64); i++) {
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float fval;
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memcpy(&fval, &h_output[i], 4);
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int expected_row = (int)fval / 128;
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int expected_pos = (int)fval % 128;
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printf(" [%3d] = %8.1f (row=%d, pos=%d)\n", i, fval, expected_row, expected_pos);
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}
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if (TOTAL > 64) printf(" ... (%d more)\n", TOTAL - 64);
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delete[] h_output;
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cudaFree(d_output);
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return 0;
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}
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