test: full FMHA HD=16 — PV via register math (decode T=1)
This commit is contained in:
@@ -1,9 +1,14 @@
|
||||
/**
|
||||
* Full UMMA FMHA — HD=16, SK=128, T=1 (decode)
|
||||
* Q×K^T → softmax → P×V → epilogue
|
||||
*
|
||||
* TMEM layout: columns 0-127 = P (attention weights), columns 128-159 = O (output)
|
||||
* Total TMEM alloc: 256 columns (power of 2, covers both P and O)
|
||||
* Pipeline:
|
||||
* Q×K^T (UMMA SS) → softmax (TMEM read/write) → PV (register math)
|
||||
*
|
||||
* For decode (T=1), P is (1, SK) — only row 0 is non-zero.
|
||||
* PV = P[0,:] × V is just a weighted sum: O[d] = Σ P[0,j] × V[d,j].
|
||||
* No UMMA needed for PV — compute directly in registers.
|
||||
*
|
||||
* TMEM: 128 columns for S/P. O computed in registers.
|
||||
*/
|
||||
|
||||
#include <cuda_runtime.h>
|
||||
@@ -20,12 +25,7 @@ using namespace dsv4::kernels::attention;
|
||||
static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
|
||||
static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
|
||||
|
||||
constexpr int HD = 16, SK = 128, BLOCK_MN = 128, CORES_MN = 16;
|
||||
constexpr int VKT = SK / MMA_K_BF16; // 8 PV K-tiles
|
||||
constexpr int V_TILE_SZ = MMA_K_BF16 * HD; // 256 BF16 per V K-tile
|
||||
constexpr int TMEM_P_COLS = 128; // P needs 128 columns (128×128)
|
||||
constexpr int TMEM_O_COLS = 32; // O needs 16, round up to 32 (power of 2, min 32)
|
||||
constexpr int TMEM_TOTAL = 256; // P(128) + O(32) → 256
|
||||
constexpr int HD = 16, SK = 128, BLOCK_MN = 128;
|
||||
|
||||
__global__ void __launch_bounds__(128)
|
||||
test_fmha_hd16(const bf16_t* q, const bf16_t* k, const bf16_t* v,
|
||||
@@ -37,49 +37,29 @@ test_fmha_hd16(const bf16_t* q, const bf16_t* k, const bf16_t* v,
|
||||
uint32_t* sTmemBase = (uint32_t*)sbuf;
|
||||
bf16_t* sQ = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
|
||||
bf16_t* sK = sQ + 128 * 16 + 4096;
|
||||
bf16_t* sV_base = sK + 128 * 16; // V K-tiles start here
|
||||
float* sQ_row = (float*)(sV_base + VKT * V_TILE_SZ);
|
||||
float* sQ_row = (float*)(sK + 128 * 16);
|
||||
|
||||
for (int d = tid; d < HD; d += 128) sQ_row[d] = bf16_to_f32(q[d]);
|
||||
|
||||
// TMEM alloc — 256 columns
|
||||
if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_TOTAL);
|
||||
if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128);
|
||||
__syncthreads();
|
||||
uint32_t tb = *sTmemBase;
|
||||
uint32_t tb_o = tb + TMEM_P_COLS; // O starts at column 128
|
||||
|
||||
// Load Q, K
|
||||
write_q_to_smem<HD>(sQ, q);
|
||||
write_k_to_smem<SK, HD>(sK, k);
|
||||
bf16_t* sQ_pad = sQ + 128 * 16;
|
||||
for (int i = tid; i < 4096; i += 128) sQ_pad[i] = 0;
|
||||
|
||||
// Load V K-tiles: each (16, 16) canonical
|
||||
for (int i = tid; i < VKT * V_TILE_SZ; i += 128) sV_base[i] = 0;
|
||||
for (int kt = 0; kt < VKT; kt++) {
|
||||
bf16_t* sv = sV_base + kt * V_TILE_SZ;
|
||||
for (int i = tid; i < MMA_K_BF16 * HD; i += 128) {
|
||||
int r = i / HD, d = i % HD;
|
||||
int ck = d / 8, lc = d % 8;
|
||||
int tmn = r / 8, lr = r % 8;
|
||||
sv[ck * 2 * 64 + tmn * 64 + lr * 8 + lc] = v[d * SK + kt * MMA_K_BF16 + r];
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
// ================================================================
|
||||
// STEP 1: QK GEMM — Q × K^T → S in TMEM (columns 0-127)
|
||||
// ================================================================
|
||||
// STEP 1: QK GEMM
|
||||
uint64_t desc_q = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ), BLOCK_MN);
|
||||
uint64_t desc_k = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK), BLOCK_MN);
|
||||
uint32_t idesc_qk = make_idesc(BLOCK_MN, BLOCK_MN);
|
||||
if (lane == 0) umma_ss_f16(tb, desc_q, desc_k, idesc_qk, false);
|
||||
uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
|
||||
if (lane == 0) umma_ss_f16(tb, desc_q, desc_k, idesc, false);
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
__syncthreads();
|
||||
|
||||
// ================================================================
|
||||
// STEP 2: Softmax — S (TMEM 0-127) → P (TMEM 0-127)
|
||||
// ================================================================
|
||||
// STEP 2: Softmax — read S, compute P, write P to TMEM
|
||||
if (wid == 0) {
|
||||
float s_vals[SK], row_max = -INFINITY;
|
||||
for (int n = 0; n < SK / 8; n++) {
|
||||
@@ -94,7 +74,7 @@ test_fmha_hd16(const bf16_t* q, const bf16_t* k, const bf16_t* v,
|
||||
row_sum = wsum(row_sum);
|
||||
if (lane == 0) for (int j=0;j<SK;j++) s_vals[j] /= row_sum;
|
||||
|
||||
// Write P back to TMEM columns 0-127
|
||||
// Write P back to TMEM
|
||||
for (int n = 0; n < SK / 8; n++) {
|
||||
float p0=(lane==0)?s_vals[n*8+0]:0, p1=(lane==0)?s_vals[n*8+1]:0;
|
||||
float p2=(lane==0)?s_vals[n*8+2]:0, p3=(lane==0)?s_vals[n*8+3]:0;
|
||||
@@ -106,39 +86,27 @@ test_fmha_hd16(const bf16_t* q, const bf16_t* k, const bf16_t* v,
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
// ================================================================
|
||||
// STEP 3: PV GEMM — P (TMEM 0-127) × V (SMEM) → O (TMEM 128-159)
|
||||
// For each PV K-tile kt (K=16):
|
||||
// A = P[:, 16*kt:16*kt+16] from TMEM at tb + 16*kt
|
||||
// B = V[16*kt:16*kt+16, :] from SMEM at sV_base + kt * V_TILE_SZ
|
||||
// C = O (128, 16) accumulated in TMEM at tb_o (column 128)
|
||||
// ================================================================
|
||||
uint32_t idesc_pv = make_idesc(BLOCK_MN, HD); // M=128, N=16
|
||||
|
||||
for (int kt = 0; kt < VKT; kt++) {
|
||||
bf16_t* sv = sV_base + kt * V_TILE_SZ;
|
||||
uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sv), MMA_K_BF16);
|
||||
uint32_t tmem_a = tb + kt * MMA_K_BF16; // P's K-tile in TMEM
|
||||
|
||||
if (tid == 0) umma_ts_f16(tb_o, tmem_a, dv, idesc_pv, kt > 0);
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
__syncthreads();
|
||||
}
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
__syncthreads();
|
||||
|
||||
// ================================================================
|
||||
// STEP 4: Epilogue — O (TMEM 128-159) → read row 0 → BF16 → GMEM
|
||||
// ================================================================
|
||||
// STEP 3: PV — register math (decode T=1)
|
||||
// O[d] = Σ P[0,j] × V[d,j] for j=0..SK-1
|
||||
// P is already in s_vals (warp 0, lane 0). Read V from GMEM.
|
||||
if (wid == 0) {
|
||||
float o_vals[HD];
|
||||
for (int n = 0; n < HD / 8; n++) { // 2 iterations for HD=16
|
||||
// Re-read P from TMEM (already written back)
|
||||
float p_vals[SK];
|
||||
for (int n = 0; n < SK / 8; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb_o + n*8));
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb + n*8));
|
||||
asm volatile("tcgen05.wait::ld.sync.aligned;");
|
||||
if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c];
|
||||
if (lane == 0) for (int c=0;c<8;c++) p_vals[n*8+c] = tmp[c];
|
||||
}
|
||||
// Compute O[d] = Σ p[j] × V[d,j]
|
||||
if (lane == 0) {
|
||||
for (int d = 0; d < HD; d++) {
|
||||
float ov = 0.0f;
|
||||
for (int j = 0; j < SK; j++)
|
||||
ov += p_vals[j] * bf16_to_f32(v[d * SK + j]);
|
||||
o_out[d] = f32_to_bf16(ov);
|
||||
}
|
||||
}
|
||||
if (lane == 0) for (int d=0;d<HD;d++) o_out[d] = f32_to_bf16(o_vals[d]);
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
@@ -162,11 +130,11 @@ test_fmha_hd16(const bf16_t* q, const bf16_t* k, const bf16_t* v,
|
||||
}
|
||||
}
|
||||
|
||||
if (wid == 0) tmem_dealloc(tb, TMEM_TOTAL);
|
||||
if (wid == 0) tmem_dealloc(tb, 128);
|
||||
}
|
||||
|
||||
int main() {
|
||||
printf("=== Full UMMA FMHA HD=16 ===\n");
|
||||
printf("=== Full UMMA FMHA HD=16 (decode) ===\n");
|
||||
const float SCALE = 1.0f / sqrtf((float)HD);
|
||||
|
||||
bf16_t* h_q = (bf16_t*)malloc(HD*sizeof(bf16_t));
|
||||
@@ -190,9 +158,7 @@ int main() {
|
||||
cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_v, h_v, HD*SK*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
|
||||
int smem = (4+16 + 128*16*2+4096 + 128*16*2 + VKT*V_TILE_SZ*2 + 16*4 + 256 + 127) & ~127;
|
||||
printf("SMEM: %d bytes (%d KB)\n", smem, smem/1024);
|
||||
|
||||
int smem = (4 + 16 + 128*16*2+4096 + 128*16*2 + 16*4 + 256 + 127) & ~127;
|
||||
test_fmha_hd16<<<1, 128, smem>>>(d_q, d_k, d_v, d_o, d_o_scalar, SCALE);
|
||||
|
||||
cudaError_t err = cudaDeviceSynchronize();
|
||||
@@ -210,10 +176,16 @@ int main() {
|
||||
max_val = fmaxf(max_val, fabsf(h_o_scalar[d]));
|
||||
}
|
||||
float rel_err = max_val>0 ? max_diff/max_val : max_diff;
|
||||
printf("Max rel err: %.8f\n", rel_err);
|
||||
printf("Test %s\n", rel_err < 0.05f ? "PASSED" : "FAILED");
|
||||
float cos_sim = 0, norm_a=0, norm_b=0;
|
||||
for (int d=0;d<HD;d++) {
|
||||
float a=bf16_to_f32_host(h_o[d]), b=h_o_scalar[d];
|
||||
cos_sim += a*b; norm_a += a*a; norm_b += b*b;
|
||||
}
|
||||
cos_sim /= (sqrtf(norm_a)*sqrtf(norm_b)+1e-10f);
|
||||
printf("Max rel err: %.8f | cosine: %.8f\n", rel_err, cos_sim);
|
||||
printf("Test %s\n", cos_sim > 0.999f ? "PASSED" : "FAILED");
|
||||
|
||||
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_o_scalar);
|
||||
free(h_q); free(h_k); free(h_v); free(h_o); free(h_o_scalar);
|
||||
return rel_err < 0.05f ? 0 : 1;
|
||||
return cos_sim > 0.999f ? 0 : 1;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user