fmha_multirow: non-interleaved design — softmax first, then PV
KEY FIX: TMEM is shared between QK output (S) and PV output (O). Cannot interleave softmax reads with PV writes because PV overwrites S. New flow: 1. QK GEMM → S in TMEM 2. Softmax: read ALL S from TMEM, compute P in registers - Pass 1: row_max (4 warps, 32x32b.x8) - Pass 2: exp, sum, store P in p_vals[SK_TILE] registers 3. PV GEMM: write P to sPk per K-tile, accumulate O in TMEM 4. Epilogue: read O from TMEM, normalize, write GMEM P in registers: each lane holds float p_vals[128] = 512 bytes. Register budget: 128 lanes × 512B = 64KB (within B200 256KB register file).
This commit is contained in:
@@ -8,37 +8,25 @@
|
||||
* 6-warp CTA: warps 0-3 = softmax, warp 4 = MMA, warp 5 = TMA load.
|
||||
* Grid: (1, n_h, batch) — each CTA processes one head of one batch item.
|
||||
*
|
||||
* TMEM operations ALL use 32x32b.x8 format exclusively.
|
||||
* 16x256b.x1 stores crash on 2nd call (verified on B200).
|
||||
* KEY: TMEM is shared between QK output (S) and PV output (O).
|
||||
* We CANNOT interleave softmax reads with PV writes.
|
||||
* Instead: softmax reads ALL of S first (into registers), THEN PV writes O.
|
||||
*
|
||||
* KEY DISCOVERY (verified on B200):
|
||||
* After UMMA (QK GEMM), 4 warps reading TMEM with 32x32b.x8 each
|
||||
* see a DIFFERENT 32-row partition of the S matrix:
|
||||
* Warp 0 → rows 0-31, Warp 1 → rows 32-63,
|
||||
* Warp 2 → rows 64-95, Warp 3 → rows 96-127.
|
||||
* After UMMA, 4 warps reading TMEM with 32x32b.x8 each see a different
|
||||
* 32-row partition (verified on B200):
|
||||
* Warp 0 → rows 0-31, Warp 1 → rows 32-63, etc.
|
||||
* Lane l in warp w reads row w*32 + l across 8 columns.
|
||||
* This is because the MMA writes Layout D to TMEM, and each warp's
|
||||
* 32x32b.x8 read naturally accesses its partition.
|
||||
*
|
||||
* SOFTMAX (two regimes):
|
||||
* - T <= 32: only warp 0 active. Lane l handles row l.
|
||||
* - T > 32: 4 softmax warps. Warp w handles rows [w*32, min((w+1)*32, T)).
|
||||
* Lane l in warp w handles row w*32 + l.
|
||||
* Two-pass: (1) row_max over all S columns, (2) exp/sum, stream P to sPk.
|
||||
* FLOW:
|
||||
* 1. QK GEMM → S in TMEM
|
||||
* 2. Softmax: read all S from TMEM, compute P in registers
|
||||
* - Pass 1: row_max
|
||||
* - Pass 2: exp(S*scale - row_max), accumulate row_sum, store P in regs
|
||||
* 3. PV GEMM: write P to sPk per K-tile, PV accumulate into TMEM
|
||||
* 4. Epilogue: read O from TMEM, normalize, write to GMEM
|
||||
*
|
||||
* P STAGING FOR PV (no s_p_vals buffer):
|
||||
* P written one K-tile at a time to sPk (128, 16) SMEM in canonical layout.
|
||||
* Softmax warps compute P in registers, write to sPk. Then MMA does PV.
|
||||
* Softmax and PV interleaved per K-tile (can't hold full 128×128 P in SMEM).
|
||||
*
|
||||
* PV GEMM:
|
||||
* N=16 sub-tiles (avoids Layout D N=64 bug). SS MMA: sPk(128,16) × sV(16,16).
|
||||
* Accumulate into TMEM across K-tiles and N-sub-tiles.
|
||||
*
|
||||
* EPILOGUE:
|
||||
* 32x32b.x8 TMEM read → normalize (1/row_sum) → BF16 → GMEM.
|
||||
* Each softmax warp reads its own 32-row partition of O from TMEM.
|
||||
* LSE = ln(row_sum) + row_max for D5 KV merge.
|
||||
* P in registers: each lane holds float p_vals[SK_TILE] = 512 bytes.
|
||||
* For T=128, 128 lanes × 512 = 64KB register space (within B200 budget).
|
||||
* ==================================================================
|
||||
*/
|
||||
|
||||
@@ -76,6 +64,7 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
static constexpr int TMEM_N = (HD <= 128) ? 128 : 256;
|
||||
static constexpr int MAX_ROWS = 128;
|
||||
static constexpr int CORES_MN = 128 / 8;
|
||||
static constexpr int NUM_READS = SK_TILE / 8; // 16 groups of 8 columns
|
||||
|
||||
const int head_idx = blockIdx.y;
|
||||
const int batch_idx = blockIdx.z;
|
||||
@@ -95,9 +84,7 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
bf16_t* __restrict__ o_head = params.o + head_idx * params.o_head_stride + batch_idx * params.o_batch_stride;
|
||||
float* __restrict__ lse_head = params.lse ? params.lse + head_idx * params.lse_head_stride + batch_idx * params.lse_batch_stride : nullptr;
|
||||
|
||||
// ================================================================
|
||||
// SMEM allocation — NO s_p_vals buffer
|
||||
// ================================================================
|
||||
// SMEM allocation
|
||||
extern __shared__ char sbuf[];
|
||||
uint32_t* sTmemBase = (uint32_t*)sbuf;
|
||||
float* sRowMax = (float*)(sbuf + 8);
|
||||
@@ -107,7 +94,7 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
bf16_t* sPk = (bf16_t*)(((uintptr_t)(sK0 + TILE_SZ) + 127) & ~(uintptr_t)127);
|
||||
bf16_t* sV = (bf16_t*)(((uintptr_t)(sPk + TILE_SZ) + 127) & ~(uintptr_t)127);
|
||||
|
||||
// TMEM allocation (warp 4)
|
||||
// TMEM alloc
|
||||
if (is_mma_warp) {
|
||||
uint32_t smem_ptr = __cvta_generic_to_shared(sTmemBase);
|
||||
tmem_alloc(smem_ptr, TMEM_N);
|
||||
@@ -115,17 +102,13 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
__syncthreads();
|
||||
uint32_t tb = *sTmemBase;
|
||||
|
||||
// ================================================================
|
||||
// Row assignment for softmax
|
||||
// ================================================================
|
||||
// After UMMA, warp w's 32x32b.x8 read gives rows [w*32, w*32+31].
|
||||
// Lane l in warp w reads row w*32 + l.
|
||||
// Row assignment
|
||||
const bool my_warp_active = (T <= 32) ? (wid == 0) : is_softmax_warp;
|
||||
const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
|
||||
const bool my_row_active = my_warp_active && (my_row < T);
|
||||
|
||||
// ================================================================
|
||||
// QK GEMM: accumulate all K-tiles into TMEM
|
||||
// QK GEMM → S in TMEM
|
||||
// ================================================================
|
||||
for (int kt = 0; kt < NKT_QK; kt++) {
|
||||
if (is_load_warp) {
|
||||
@@ -134,9 +117,8 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
for (int d = lane; d < MMA_K_BF16; d += 32) {
|
||||
int full_d = kt * MMA_K_BF16 + d;
|
||||
if (full_d < HD) {
|
||||
int ck = d / 8, lc = d % 8;
|
||||
int core_mn = r / 8, local_r = r % 8;
|
||||
sQ0[ck * CORES_MN * 64 + core_mn * 64 + local_r * 8 + lc] = q_head[r * HD + full_d];
|
||||
int ck = d/8, lc = d%8, cm = r/8, lr = r%8;
|
||||
sQ0[ck*CORES_MN*64 + cm*64 + lr*8 + lc] = q_head[r * HD + full_d];
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -145,15 +127,13 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
for (int d = lane; d < MMA_K_BF16; d += 32) {
|
||||
int full_d = kt * MMA_K_BF16 + d;
|
||||
if (full_d < HD) {
|
||||
int ck = d / 8, lc = d % 8;
|
||||
int tmn = r / 8, lr = r % 8;
|
||||
sK0[ck * CORES_MN * 64 + tmn * 64 + lr * 8 + lc] = k_head[r * HD + full_d];
|
||||
int ck = d/8, lc = d%8, tmn = r/8, lr = r%8;
|
||||
sK0[ck*CORES_MN*64 + tmn*64 + lr*8 + lc] = k_head[r * HD + full_d];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
if (is_mma_warp) {
|
||||
uint32_t idesc = make_idesc(128, 128);
|
||||
uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
|
||||
@@ -164,16 +144,16 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
__syncthreads();
|
||||
}
|
||||
|
||||
// Ensure TMEM visibility across all warps after QK GEMM
|
||||
// TMEM visibility fence
|
||||
asm volatile("fence.sc.gpu;" ::: "memory");
|
||||
__syncthreads();
|
||||
|
||||
// ================================================================
|
||||
// SOFTMAX PASS 1: compute row_max for each row
|
||||
// SOFTMAX — compute P in registers (TWO passes over TMEM)
|
||||
// ================================================================
|
||||
float my_row_max = -INFINITY;
|
||||
const int NUM_READS = SK_TILE / 8;
|
||||
|
||||
// Pass 1: row_max
|
||||
float my_row_max = -INFINITY;
|
||||
if (my_warp_active) {
|
||||
for (int n = 0; n < NUM_READS; n++) {
|
||||
float tmp[8];
|
||||
@@ -182,121 +162,113 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
|
||||
: "r"(tb + n * 8));
|
||||
asm volatile("tcgen05.wait::ld.sync.aligned;");
|
||||
if (my_row_active) {
|
||||
for (int c = 0; c < 8; c++) {
|
||||
int col = n * 8 + c;
|
||||
if (col < s_k) my_row_max = fmaxf(my_row_max, tmp[c] * scale);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Store row_max to SMEM for cross-warp visibility
|
||||
if (my_row_active) sRowMax[my_row] = my_row_max;
|
||||
__syncthreads();
|
||||
|
||||
// Pass 2: compute P values (exp, sum, normalize)
|
||||
float my_p_vals[SK_TILE]; // P for my row, all columns
|
||||
float my_row_sum = 0.0f;
|
||||
|
||||
if (my_warp_active) {
|
||||
float rm = my_row_active ? sRowMax[my_row] : 0.0f;
|
||||
for (int n = 0; n < NUM_READS; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
|
||||
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
|
||||
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
|
||||
: "r"(tb + n * 8));
|
||||
asm volatile("tcgen05.wait::ld.aligned;"); // NOTE: ld not ld.sync — some B200 builds need the dot
|
||||
if (my_row_active) {
|
||||
for (int c = 0; c < 8; c++) {
|
||||
int col = n * 8 + c;
|
||||
if (col < s_k) {
|
||||
float val = tmp[c] * scale;
|
||||
my_row_max = fmaxf(my_row_max, val);
|
||||
float p = expf(tmp[c] * scale - rm);
|
||||
my_p_vals[col] = p;
|
||||
my_row_sum += p;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (my_row_active) sRowMax[my_row] = my_row_max;
|
||||
// Store row_sum
|
||||
if (my_row_active) sRowSum[my_row] = my_row_sum;
|
||||
__syncthreads();
|
||||
|
||||
// ================================================================
|
||||
// SOFTMAX PASS 2 + PV GEMM (interleaved per PV K-tile)
|
||||
// PV GEMM — write P to sPk per K-tile, accumulate O in TMEM
|
||||
// ================================================================
|
||||
float my_row_sum = 0.0f;
|
||||
for (int n_sub = 0; n_sub < N_NSUB; n_sub++) {
|
||||
int d_base = n_sub * 16;
|
||||
for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
|
||||
const int col_start = pv_kt * MMA_K_BF16;
|
||||
|
||||
for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
|
||||
const int col_start = pv_kt * MMA_K_BF16;
|
||||
const int col_end = col_start + MMA_K_BF16;
|
||||
const int rg_start = col_start / 8;
|
||||
const int rg_end = col_end / 8;
|
||||
// Load warp: zero sPk
|
||||
if (is_load_warp) {
|
||||
for (int i = lane; i < TILE_SZ; i += 32) sPk[i] = 0;
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
float p_vals[16];
|
||||
for (int c = 0; c < MMA_K_BF16; c++) p_vals[c] = 0.0f;
|
||||
|
||||
if (my_warp_active) {
|
||||
float rm = my_row_active ? sRowMax[my_row] : 0.0f;
|
||||
|
||||
for (int n = rg_start; n < rg_end; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
|
||||
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
|
||||
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
|
||||
: "r"(tb + n * 8));
|
||||
asm volatile("tcgen05.wait::ld.sync.aligned;");
|
||||
|
||||
if (my_row_active) {
|
||||
for (int c = 0; c < 8; c++) {
|
||||
int col = n * 8 + c;
|
||||
if (col < s_k && col >= col_start && col < col_end) {
|
||||
float val = expf(tmp[c] * scale - rm);
|
||||
p_vals[col - col_start] = val;
|
||||
my_row_sum += val;
|
||||
}
|
||||
}
|
||||
// Softmax warps: write P to sPk
|
||||
if (my_row_active) {
|
||||
for (int c = 0; c < MMA_K_BF16; c++) {
|
||||
int gc = col_start + c;
|
||||
int ck = c/8, lc = c%8;
|
||||
int core_mn = my_row/8, local_r = my_row%8;
|
||||
sPk[ck*CORES_MN*64 + core_mn*64 + local_r*8 + lc] = f32_to_bf16(my_p_vals[gc]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Zero sPk
|
||||
if (is_load_warp) {
|
||||
for (int i = lane; i < TILE_SZ; i += 32) sPk[i] = 0;
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
// Write P to sPk in canonical layout
|
||||
if (my_row_active) {
|
||||
for (int c = 0; c < MMA_K_BF16; c++) {
|
||||
int ck = c / 8, lc = c % 8;
|
||||
int core_mn = my_row / 8, local_r = my_row % 8;
|
||||
sPk[ck * CORES_MN * 64 + core_mn * 64 + local_r * 8 + lc] = f32_to_bf16(p_vals[c]);
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
// PV GEMM: N=16 sub-tiles
|
||||
for (int n_sub = 0; n_sub < N_NSUB; n_sub++) {
|
||||
int d_base = n_sub * 16;
|
||||
__syncthreads();
|
||||
|
||||
// Load warp: fill sV
|
||||
if (is_load_warp) {
|
||||
for (int i = lane; i < V_SUB_SZ; i += 32) sV[i] = 0;
|
||||
for (int dd = lane; dd < 16; dd += 32) {
|
||||
for (int lr = 0; lr < MMA_K_BF16; lr++) {
|
||||
int r = col_start + lr;
|
||||
if (r < s_k && (d_base + dd) < HD) {
|
||||
int g_mn = dd / 8, g_k = lr / 8;
|
||||
int llr = dd % 8, lc = lr % 8;
|
||||
sV[g_k * 2 * 64 + g_mn * 64 + llr * 8 + lc] = v_head[(d_base + dd) * s_k + r];
|
||||
int g_mn = dd/8, g_k = lr/8, llr = dd%8, lc = lr%8;
|
||||
sV[g_k*2*64 + g_mn*64 + llr*8 + lc] = v_head[(d_base+dd)*s_k + r];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
// MMA: sPk × sV → TMEM
|
||||
if (is_mma_warp) {
|
||||
uint32_t idesc_pv = make_idesc(128, 16);
|
||||
uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), 128);
|
||||
uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
|
||||
if (tid == 128) umma_ss_f16(tb + n_sub * 16, dp, dv, idesc_pv, pv_kt > 0);
|
||||
// accumulate: first K-tile for this n_sub should NOT accumulate
|
||||
// pv_kt > 0 means we're accumulating across K-tiles for the same n_sub
|
||||
if (tid == 128) umma_ss_f16(tb + n_sub*16, dp, dv, idesc_pv, pv_kt > 0);
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
}
|
||||
__syncthreads();
|
||||
}
|
||||
}
|
||||
|
||||
if (my_row_active) sRowSum[my_row] = my_row_sum;
|
||||
__syncthreads();
|
||||
|
||||
// ================================================================
|
||||
// EPILOGUE: TMEM → regs → normalize → BF16 → GMEM
|
||||
// ================================================================
|
||||
// After PV GEMM, O[128, HD] is in TMEM. Each softmax warp reads
|
||||
// its own 32-row partition (same as after QK GEMM).
|
||||
// HD/8 = N_NSUB*2 read groups.
|
||||
if (my_warp_active) {
|
||||
if (my_row_active) {
|
||||
float rm = sRowMax[my_row];
|
||||
float rs = sRowSum[my_row];
|
||||
float inv_rs = 1.0f / rs;
|
||||
|
||||
// Read O from TMEM: N_NSUB*2 groups of 8 columns
|
||||
for (int n = 0; n < N_NSUB * 2; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
|
||||
@@ -307,15 +279,11 @@ fmha_6warp_multirow_kernel(FmhaMultiRowParams params) {
|
||||
|
||||
for (int c = 0; c < 8; c++) {
|
||||
int d = n * 8 + c;
|
||||
if (d < HD) {
|
||||
o_head[my_row * HD + d] = f32_to_bf16(tmp[c] * inv_rs);
|
||||
}
|
||||
if (d < HD) o_head[my_row * HD + d] = f32_to_bf16(tmp[c] * inv_rs);
|
||||
}
|
||||
}
|
||||
|
||||
if (lse_head) {
|
||||
lse_head[my_row] = logf(rs) + rm;
|
||||
}
|
||||
if (lse_head) lse_head[my_row] = logf(rs) + rm;
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
@@ -1,15 +1,13 @@
|
||||
/**
|
||||
* Minimal test: multirow kernel QK + softmax only (no PV, no epilogue).
|
||||
* Writes row_max per row to GMEM. If this works, the hang is in PV/epilogue.
|
||||
* If it hangs, the hang is in QK or softmax.
|
||||
* Compile: -DHD_VAL=64
|
||||
* Test multi-row FMHA kernel (6-warp, T>1 prefill).
|
||||
* Compile with -DHD_VAL=64 etc.
|
||||
*/
|
||||
|
||||
#include <cuda_runtime.h>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
#include <cmath>
|
||||
#include <cstdlib>
|
||||
#include <cstring>
|
||||
|
||||
#ifndef HD_VAL
|
||||
#define HD_VAL 64
|
||||
@@ -25,155 +23,146 @@ static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; m
|
||||
|
||||
constexpr int HD = HD_VAL;
|
||||
constexpr int SK = 128;
|
||||
constexpr int MAX_T = 128;
|
||||
|
||||
template<int HD_T, int SK_TILE=128>
|
||||
__global__ void __launch_bounds__(192)
|
||||
test_softmax_only_kernel(const bf16_t* q, const bf16_t* k, float* row_max_out, int T, int s_k, float scale) {
|
||||
static constexpr int NKT_QK = HD_T / MMA_K_BF16;
|
||||
static constexpr int TILE_SZ = 128 * MMA_K_BF16;
|
||||
static constexpr int TMEM_N = (HD_T <= 128) ? 128 : 256;
|
||||
static constexpr int CORES_MN = 128 / 8;
|
||||
static constexpr int NUM_READS = SK_TILE / 8;
|
||||
#include "dsv4/kernels/attention/fmha_6warp_multirow.cuh"
|
||||
|
||||
const int tid = threadIdx.x;
|
||||
const int wid = tid / 32;
|
||||
const int lane = tid % 32;
|
||||
const bool is_mma_warp = (wid == 4);
|
||||
const bool is_load_warp = (wid == 5);
|
||||
const bool my_warp_active = (T <= 32) ? (wid == 0) : (wid < 4);
|
||||
const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
|
||||
const bool my_row_active = my_warp_active && (my_row < T);
|
||||
static int compute_smem() {
|
||||
size_t off = 0;
|
||||
off += 8;
|
||||
off += 128 * sizeof(float); // sRowMax
|
||||
off += 128 * sizeof(float); // sRowSum
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sQ0
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sK0
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sPk
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 16 * MMA_K_BF16 * sizeof(bf16_t); // sV
|
||||
off += 256;
|
||||
return (int)off;
|
||||
}
|
||||
|
||||
extern __shared__ char sbuf[];
|
||||
uint32_t* sTmemBase = (uint32_t*)sbuf;
|
||||
bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 256) + 127) & ~(uintptr_t)127);
|
||||
bf16_t* sK0 = sQ0 + TILE_SZ;
|
||||
|
||||
if (is_mma_warp) {
|
||||
uint32_t sp = __cvta_generic_to_shared(sTmemBase);
|
||||
tmem_alloc(sp, TMEM_N);
|
||||
static void reference_attention_multirow(
|
||||
const bf16_t* q, const bf16_t* k, const bf16_t* v,
|
||||
float* o_ref, float* lse_ref,
|
||||
int hd, int T, int s_k, float scale
|
||||
) {
|
||||
for (int t = 0; t < T; t++) {
|
||||
float s[512];
|
||||
for (int j = 0; j < s_k; j++) {
|
||||
float dot = 0.0f;
|
||||
for (int d = 0; d < hd; d++)
|
||||
dot += bf16_to_f32_host(q[t * hd + d]) * bf16_to_f32_host(k[j * hd + d]);
|
||||
s[j] = dot * scale;
|
||||
}
|
||||
float mx = -INFINITY;
|
||||
for (int j = 0; j < s_k; j++) mx = fmaxf(mx, s[j]);
|
||||
float sm = 0.0f;
|
||||
for (int j = 0; j < s_k; j++) { s[j] = expf(s[j] - mx); sm += s[j]; }
|
||||
for (int j = 0; j < s_k; j++) s[j] /= sm;
|
||||
for (int d = 0; d < hd; d++) {
|
||||
float ov = 0.0f;
|
||||
for (int j = 0; j < s_k; j++) ov += s[j] * bf16_to_f32_host(v[d * s_k + j]);
|
||||
o_ref[t * hd + d] = ov;
|
||||
}
|
||||
if (lse_ref) lse_ref[t] = logf(sm) + mx;
|
||||
}
|
||||
__syncthreads();
|
||||
uint32_t tb = *sTmemBase;
|
||||
}
|
||||
|
||||
// QK GEMM
|
||||
for (int kt = 0; kt < NKT_QK; kt++) {
|
||||
if (is_load_warp) {
|
||||
for (int i = lane; i < TILE_SZ; i += 32) sQ0[i] = 0;
|
||||
for (int r = 0; r < T; r++) {
|
||||
for (int d = lane; d < MMA_K_BF16; d += 32) {
|
||||
int full_d = kt * MMA_K_BF16 + d;
|
||||
if (full_d < HD_T) {
|
||||
int ck = d/8, lc = d%8;
|
||||
int cm = r/8, lr = r%8;
|
||||
sQ0[ck*CORES_MN*64 + cm*64 + lr*8 + lc] = q[r * HD_T + full_d];
|
||||
}
|
||||
}
|
||||
}
|
||||
for (int i = lane; i < TILE_SZ; i += 32) sK0[i] = 0;
|
||||
for (int r = 0; r < s_k; r++) {
|
||||
for (int d = lane; d < MMA_K_BF16; d += 32) {
|
||||
int full_d = kt * MMA_K_BF16 + d;
|
||||
if (full_d < HD_T) {
|
||||
int ck = d/8, lc = d%8;
|
||||
int tmn = r/8, lr = r%8;
|
||||
sK0[ck*CORES_MN*64 + tmn*64 + lr*8 + lc] = k[r * HD_T + full_d];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
static int test_single_T(int T, int n_h = 1, int batch = 1) {
|
||||
printf("\n=== T=%d, n_h=%d, batch=%d, HD=%d ===\n", T, n_h, batch, HD);
|
||||
const float SCALE = 1.0f / sqrtf((float)HD);
|
||||
int total_heads = batch * n_h;
|
||||
|
||||
if (is_mma_warp) {
|
||||
uint32_t idesc = make_idesc(128, 128);
|
||||
uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
|
||||
uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
|
||||
if (tid == 128) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
}
|
||||
__syncthreads();
|
||||
bf16_t* h_q = (bf16_t*)malloc(total_heads * T * HD * sizeof(bf16_t));
|
||||
bf16_t* h_k = (bf16_t*)malloc(total_heads * SK * HD * sizeof(bf16_t));
|
||||
bf16_t* h_v = (bf16_t*)malloc(total_heads * HD * SK * sizeof(bf16_t));
|
||||
bf16_t* h_o = (bf16_t*)calloc(total_heads * T * HD, sizeof(bf16_t));
|
||||
float* h_lse = (float*)calloc(total_heads * T, sizeof(float));
|
||||
|
||||
srand(42 + T);
|
||||
for (int i = 0; i < total_heads * T * HD; i++) h_q[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
|
||||
for (int i = 0; i < total_heads * SK * HD; i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
|
||||
for (int i = 0; i < total_heads * HD * SK; i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
|
||||
|
||||
bf16_t *d_q, *d_k, *d_v, *d_o; float *d_lse;
|
||||
cudaMalloc(&d_q, total_heads * T * HD * sizeof(bf16_t));
|
||||
cudaMalloc(&d_k, total_heads * SK * HD * sizeof(bf16_t));
|
||||
cudaMalloc(&d_v, total_heads * HD * SK * sizeof(bf16_t));
|
||||
cudaMalloc(&d_o, total_heads * T * HD * sizeof(bf16_t));
|
||||
cudaMalloc(&d_lse, total_heads * T * sizeof(float));
|
||||
cudaMemcpy(d_q, h_q, total_heads * T * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_k, h_k, total_heads * SK * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_v, h_v, total_heads * HD * SK * sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
|
||||
FmhaMultiRowParams params;
|
||||
params.q = d_q; params.k = d_k; params.v = d_v; params.o = d_o; params.lse = d_lse;
|
||||
params.s_k = SK; params.T = T; params.scale = SCALE; params.head_dim = HD;
|
||||
params.q_head_stride = T * HD; params.q_batch_stride = n_h * T * HD;
|
||||
params.k_head_stride = SK * HD; params.k_batch_stride = n_h * SK * HD;
|
||||
params.v_head_stride = HD * SK; params.v_batch_stride = n_h * HD * SK;
|
||||
params.o_head_stride = T * HD; params.o_batch_stride = n_h * T * HD;
|
||||
params.lse_head_stride = T; params.lse_batch_stride = n_h * T;
|
||||
|
||||
int smem = compute_smem();
|
||||
if (smem > 48 * 1024)
|
||||
cudaFuncSetAttribute(fmha_6warp_multirow_kernel<HD>, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
|
||||
|
||||
dim3 grid(1, n_h, batch);
|
||||
fmha_6warp_multirow_kernel<HD><<<grid, 192, smem>>>(params);
|
||||
|
||||
cudaError_t err = cudaDeviceSynchronize();
|
||||
if (err != cudaErrorCudaSuccess) {
|
||||
printf(" CUDA ERROR: %s\n", cudaGetErrorString(err));
|
||||
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_lse);
|
||||
free(h_q); free(h_k); free(h_v); free(h_o); free(h_lse);
|
||||
return 0;
|
||||
}
|
||||
|
||||
asm volatile("fence.sc.gpu;" ::: "memory");
|
||||
__syncthreads();
|
||||
cudaMemcpy(h_o, d_o, total_heads * T * HD * sizeof(bf16_t), cudaMemcpyDeviceToHost);
|
||||
cudaMemcpy(h_lse, d_lse, total_heads * T * sizeof(float), cudaMemcpyDeviceToHost);
|
||||
|
||||
// Softmax pass 1: row_max
|
||||
float my_row_max = -INFINITY;
|
||||
if (my_warp_active) {
|
||||
for (int n = 0; n < NUM_READS; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
|
||||
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
|
||||
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
|
||||
: "r"(tb + n * 8));
|
||||
asm volatile("tcgen05.wait::ld.sync.aligned;");
|
||||
if (my_row_active) {
|
||||
for (int c = 0; c < 8; c++) {
|
||||
int col = n * 8 + c;
|
||||
if (col < s_k) my_row_max = fmaxf(my_row_max, tmp[c] * scale);
|
||||
int failed = 0; float min_cos = 1.0f;
|
||||
for (int b = 0; b < batch; b++) {
|
||||
for (int h = 0; h < n_h; h++) {
|
||||
int idx = b * n_h + h;
|
||||
float o_ref[MAX_T * 512]; float lse_ref[MAX_T];
|
||||
reference_attention_multirow(
|
||||
h_q + idx*T*HD, h_k + idx*SK*HD, h_v + idx*HD*SK,
|
||||
o_ref, lse_ref, HD, T, SK, SCALE);
|
||||
for (int t = 0; t < T; t++) {
|
||||
float cs=0,na=0,nb=0;
|
||||
for (int d=0;d<HD;d++) {
|
||||
float a=bf16_to_f32_host(h_o[(idx*T+t)*HD+d]), b2=o_ref[t*HD+d];
|
||||
if(fabsf(b2)>1e-4f){cs+=a*b2;na+=a*a;nb+=b2*b2;}
|
||||
}
|
||||
cs /= (sqrtf(na)*sqrtf(nb)+1e-10f);
|
||||
if(cs<min_cos) min_cos=cs;
|
||||
if(cs<0.999f) { printf(" FAIL b=%d h=%d t=%d cos=%.6f\n",b,h,t,cs); failed++; }
|
||||
}
|
||||
}
|
||||
}
|
||||
printf(" min_cos=%.8f %s\n", min_cos, failed==0?"PASSED":"FAILED");
|
||||
|
||||
// Write row_max to GMEM
|
||||
if (my_row_active) row_max_out[my_row] = my_row_max;
|
||||
|
||||
__syncthreads();
|
||||
if (is_mma_warp) tmem_dealloc(tb, TMEM_N);
|
||||
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_lse);
|
||||
free(h_q); free(h_k); free(h_v); free(h_o); free(h_lse);
|
||||
return failed == 0;
|
||||
}
|
||||
|
||||
int main() {
|
||||
printf("Softmax-only test (HD=%d)\n", HD);
|
||||
const float SCALE = 1.0f / sqrtf((float)HD);
|
||||
printf("Multi-row FMHA test (HD=%d)\n", HD);
|
||||
|
||||
for (int T : {1, 4, 32, 128}) {
|
||||
printf("T=%d: ", T);
|
||||
int ok = 1;
|
||||
ok &= test_single_T(1);
|
||||
ok &= test_single_T(2);
|
||||
ok &= test_single_T(4);
|
||||
ok &= test_single_T(8);
|
||||
ok &= test_single_T(16);
|
||||
ok &= test_single_T(32);
|
||||
ok &= test_single_T(64);
|
||||
ok &= test_single_T(128);
|
||||
|
||||
bf16_t *h_q = (bf16_t*)malloc(T * HD * sizeof(bf16_t));
|
||||
bf16_t *h_k = (bf16_t*)malloc(SK * HD * sizeof(bf16_t));
|
||||
float *h_rm = (float*)calloc(T, sizeof(float));
|
||||
|
||||
srand(42 + T);
|
||||
for (int i=0;i<T*HD;i++) h_q[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
|
||||
for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
|
||||
|
||||
bf16_t *d_q, *d_k; float *d_rm;
|
||||
cudaMalloc(&d_q, T*HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_rm, T*sizeof(float));
|
||||
cudaMemcpy(d_q, h_q, T*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemset(d_rm, 0, T*sizeof(float));
|
||||
|
||||
int smem = 256 + 128 + 128*MMA_K_BF16*2*2 + 256;
|
||||
test_softmax_only_kernel<HD><<<1, 192, smem>>>(d_q, d_k, d_rm, T, SK, SCALE);
|
||||
|
||||
cudaError_t err = cudaDeviceSynchronize();
|
||||
if (err != cudaSuccess) {
|
||||
printf("CUDA ERROR: %s\n", cudaGetErrorString(err));
|
||||
} else {
|
||||
cudaMemcpy(h_rm, d_rm, T*sizeof(float), cudaMemcpyDeviceToHost);
|
||||
|
||||
// Compute reference row_max
|
||||
int ok = 1;
|
||||
for (int t = 0; t < T; t++) {
|
||||
float ref_max = -INFINITY;
|
||||
for (int j = 0; j < SK; j++) {
|
||||
float dot = 0;
|
||||
for (int d = 0; d < HD; d++)
|
||||
dot += bf16_to_f32_host(h_q[t*HD+d]) * bf16_to_f32_host(h_k[j*HD+d]);
|
||||
ref_max = fmaxf(ref_max, dot * SCALE);
|
||||
}
|
||||
float err2 = fabsf(h_rm[t] - ref_max) / (fabsf(ref_max) + 1e-6f);
|
||||
if (err2 > 0.01f) { ok = 0; printf("t=%d: got %.4f ref %.4f err %.4f ", t, h_rm[t], ref_max, err2); }
|
||||
}
|
||||
printf("%s (T=%d)\n", ok ? "OK" : "FAIL", T);
|
||||
}
|
||||
|
||||
cudaFree(d_q); cudaFree(d_k); cudaFree(d_rm);
|
||||
free(h_q); free(h_k); free(h_rm);
|
||||
}
|
||||
|
||||
return 0;
|
||||
printf("\n%s\n", ok ? "ALL PASSED" : "SOME FAILED");
|
||||
return ok ? 0 : 1;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user