biondizzle/nvfp4-megamoe-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

test: softmax-only kernel (QK + row_max, no PV)

Browse Source
This commit is contained in:
biondizzle
2026-05-28 23:15:36 +00:00
parent 43ba672e15
commit c768abed95
1 changed files with 140 additions and 139 deletions
Download Patch File Download Diff File Expand all files Collapse all files

279
tests/unit/test_fmha_6warp_multirow.cu
View File

@@ -1,13 +1,15 @@
/**
* Test multi-row FMHA kernel (6-warp, T>1 prefill).
* Compile with -DHD_VAL=64 etc.
* Minimal test: multirow kernel QK + softmax only (no PV, no epilogue).
* Writes row_max per row to GMEM. If this works, the hang is in PV/epilogue.
* If it hangs, the hang is in QK or softmax.
* Compile: -DHD_VAL=64
*/
#include <cuda_runtime.h>
#include <cstdio>
#include <cstring>
#include <cmath>
#include <cstdlib>
#include <cstring>
#ifndef HD_VAL
#define HD_VAL 64
@@ -23,156 +25,155 @@ static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; m
constexpr int HD = HD_VAL;
constexpr int SK = 128;
constexpr int MAX_T = 128;
#include "dsv4/kernels/attention/fmha_6warp_multirow.cuh"
template<int HD_T, int SK_TILE=128>
__global__ void __launch_bounds__(192)
test_softmax_only_kernel(const bf16_t* q, const bf16_t* k, float* row_max_out, int T, int s_k, float scale) {
static constexpr int NKT_QK = HD_T / MMA_K_BF16;
static constexpr int TILE_SZ = 128 * MMA_K_BF16;
static constexpr int TMEM_N = (HD_T <= 128) ? 128 : 256;
static constexpr int CORES_MN = 128 / 8;
static constexpr int NUM_READS = SK_TILE / 8;
// Compute SMEM size matching the kernel layout exactly
static int compute_smem() {
// Mirror the kernel's SMEM layout:
// sTmemBase(8B) + sRowMax(128*4) + sRowSum(128*4) + align128
// + sQ0(128*16*2) + sK0(128*16*2) + align128
// + sPk(128*16*2) + align128 + sV(16*16*2) + slack
size_t off = 0;
off += 8; // sTmemBase + alignment
off += 128 * sizeof(float); // sRowMax
off += 128 * sizeof(float); // sRowSum
off = (off + 127) & ~(size_t)127; // align for sQ0
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sQ0
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sK0
off = (off + 127) & ~(size_t)127; // align for sPk
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sPk
off = (off + 127) & ~(size_t)127; // align for sV
off += 16 * MMA_K_BF16 * sizeof(bf16_t); // sV
off += 256; // slack
return (int)off;
}
const int tid = threadIdx.x;
const int wid = tid / 32;
const int lane = tid % 32;
const bool is_mma_warp = (wid == 4);
const bool is_load_warp = (wid == 5);
const bool my_warp_active = (T <= 32) ? (wid == 0) : (wid < 4);
const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
const bool my_row_active = my_warp_active && (my_row < T);
static void reference_attention_multirow(
const bf16_t* q, const bf16_t* k, const bf16_t* v,
float* o_ref, float* lse_ref,
int hd, int T, int s_k, float scale
) {
for (int t = 0; t < T; t++) {
float s[512];
for (int j = 0; j < s_k; j++) {
float dot = 0.0f;
for (int d = 0; d < hd; d++)
dot += bf16_to_f32_host(q[t * hd + d]) * bf16_to_f32_host(k[j * hd + d]);
s[j] = dot * scale;
}
float mx = -INFINITY;
for (int j = 0; j < s_k; j++) mx = fmaxf(mx, s[j]);
float sm = 0.0f;
for (int j = 0; j < s_k; j++) { s[j] = expf(s[j] - mx); sm += s[j]; }
for (int j = 0; j < s_k; j++) s[j] /= sm;
for (int d = 0; d < hd; d++) {
float ov = 0.0f;
for (int j = 0; j < s_k; j++) ov += s[j] * bf16_to_f32_host(v[d * s_k + j]);
o_ref[t * hd + d] = ov;
}
if (lse_ref) lse_ref[t] = logf(sm) + mx;
extern __shared__ char sbuf[];
uint32_t* sTmemBase = (uint32_t*)sbuf;
bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 256) + 127) & ~(uintptr_t)127);
bf16_t* sK0 = sQ0 + TILE_SZ;
if (is_mma_warp) {
uint32_t sp = __cvta_generic_to_shared(sTmemBase);
tmem_alloc(sp, TMEM_N);
}
}
__syncthreads();
uint32_t tb = *sTmemBase;
static int test_single_T(int T, int n_h = 1, int batch = 1) {
printf("\n=== T=%d, n_h=%d, batch=%d, HD=%d, SK=%d ===\n", T, n_h, batch, HD, SK);
const float SCALE = 1.0f / sqrtf((float)HD);
int total_heads = batch * n_h;
bf16_t* h_q = (bf16_t*)malloc(total_heads * T * HD * sizeof(bf16_t));
bf16_t* h_k = (bf16_t*)malloc(total_heads * SK * HD * sizeof(bf16_t));
bf16_t* h_v = (bf16_t*)malloc(total_heads * HD * SK * sizeof(bf16_t));
bf16_t* h_o = (bf16_t*)calloc(total_heads * T * HD, sizeof(bf16_t));
float* h_lse = (float*)calloc(total_heads * T, sizeof(float));
srand(42 + T);
for (int i = 0; i < total_heads * T * HD; i++) h_q[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
for (int i = 0; i < total_heads * SK * HD; i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
for (int i = 0; i < total_heads * HD * SK; i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
bf16_t *d_q, *d_k, *d_v, *d_o; float *d_lse;
cudaMalloc(&d_q, total_heads * T * HD * sizeof(bf16_t));
cudaMalloc(&d_k, total_heads * SK * HD * sizeof(bf16_t));
cudaMalloc(&d_v, total_heads * HD * SK * sizeof(bf16_t));
cudaMalloc(&d_o, total_heads * T * HD * sizeof(bf16_t));
cudaMalloc(&d_lse, total_heads * T * sizeof(float));
cudaMemcpy(d_q, h_q, total_heads * T * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemcpy(d_k, h_k, total_heads * SK * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemcpy(d_v, h_v, total_heads * HD * SK * sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemset(d_o, 0, total_heads * T * HD * sizeof(bf16_t));
cudaMemset(d_lse, 0, total_heads * T * sizeof(float));
FmhaMultiRowParams params;
params.q = d_q; params.k = d_k; params.v = d_v; params.o = d_o; params.lse = d_lse;
params.s_k = SK; params.T = T; params.scale = SCALE; params.head_dim = HD;
params.q_head_stride = T * HD; params.q_batch_stride = n_h * T * HD;
params.k_head_stride = SK * HD; params.k_batch_stride = n_h * SK * HD;
params.v_head_stride = HD * SK; params.v_batch_stride = n_h * HD * SK;
params.o_head_stride = T * HD; params.o_batch_stride = n_h * T * HD;
params.lse_head_stride = T; params.lse_batch_stride = n_h * T;
int smem = compute_smem();
if (smem > 48 * 1024)
cudaFuncSetAttribute(fmha_6warp_multirow_kernel<HD>, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
dim3 grid(1, n_h, batch);
fmha_6warp_multirow_kernel<HD><<<grid, 192, smem>>>(params);
cudaError_t err = cudaDeviceSynchronize();
if (err != cudaSuccess) {
printf(" CUDA ERROR: %s\n", cudaGetErrorString(err));
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_lse);
free(h_q); free(h_k); free(h_v); free(h_o); free(h_lse);
return 0;
}
cudaMemcpy(h_o, d_o, total_heads * T * HD * sizeof(bf16_t), cudaMemcpyDeviceToHost);
cudaMemcpy(h_lse, d_lse, total_heads * T * sizeof(float), cudaMemcpyDeviceToHost);
int failed = 0; float min_cos = 1.0f;
for (int b = 0; b < batch; b++) {
for (int h = 0; h < n_h; h++) {
int idx = b * n_h + h;
float o_ref[MAX_T * 512]; float lse_ref[MAX_T];
reference_attention_multirow(
h_q + idx * T * HD, h_k + idx * SK * HD, h_v + idx * HD * SK,
o_ref, lse_ref, HD, T, SK, SCALE);
for (int t = 0; t < T; t++) {
float cs=0,na=0,nb=0;
for (int d=0;d<HD;d++) {
float a=bf16_to_f32_host(h_o[(idx*T+t)*HD+d]), b2=o_ref[t*HD+d];
if(fabsf(b2)>1e-4f){cs+=a*b2;na+=a*a;nb+=b2*b2;}
// QK GEMM
for (int kt = 0; kt < NKT_QK; kt++) {
if (is_load_warp) {
for (int i = lane; i < TILE_SZ; i += 32) sQ0[i] = 0;
for (int r = 0; r < T; r++) {
for (int d = lane; d < MMA_K_BF16; d += 32) {
int full_d = kt * MMA_K_BF16 + d;
if (full_d < HD_T) {
int ck = d/8, lc = d%8;
int cm = r/8, lr = r%8;
sQ0[ck*CORES_MN*64 + cm*64 + lr*8 + lc] = q[r * HD_T + full_d];
}
}
cs /= (sqrtf(na)*sqrtf(nb)+1e-10f);
if(cs<min_cos) min_cos=cs;
if(cs<0.999f) {
printf(" FAIL b=%d h=%d t=%d: cos=%.6f\n",b,h,t,cs);
failed++;
}
for (int i = lane; i < TILE_SZ; i += 32) sK0[i] = 0;
for (int r = 0; r < s_k; r++) {
for (int d = lane; d < MMA_K_BF16; d += 32) {
int full_d = kt * MMA_K_BF16 + d;
if (full_d < HD_T) {
int ck = d/8, lc = d%8;
int tmn = r/8, lr = r%8;
sK0[ck*CORES_MN*64 + tmn*64 + lr*8 + lc] = k[r * HD_T + full_d];
}
}
}
}
__syncthreads();
if (is_mma_warp) {
uint32_t idesc = make_idesc(128, 128);
uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
if (tid == 128) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
}
__syncthreads();
}
asm volatile("fence.sc.gpu;" ::: "memory");
__syncthreads();
// Softmax pass 1: row_max
float my_row_max = -INFINITY;
if (my_warp_active) {
for (int n = 0; n < NUM_READS; n++) {
float tmp[8];
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
: "r"(tb + n * 8));
asm volatile("tcgen05.wait::ld.sync.aligned;");
if (my_row_active) {
for (int c = 0; c < 8; c++) {
int col = n * 8 + c;
if (col < s_k) my_row_max = fmaxf(my_row_max, tmp[c] * scale);
}
}
}
}
printf(" min_cos=%.8f failed=%d %s\n", min_cos, failed, failed==0?"PASSED":"FAILED");
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_lse);
free(h_q); free(h_k); free(h_v); free(h_o); free(h_lse);
return failed == 0;
// Write row_max to GMEM
if (my_row_active) row_max_out[my_row] = my_row_max;
__syncthreads();
if (is_mma_warp) tmem_dealloc(tb, TMEM_N);
}
int main() {
printf("Multi-row FMHA test (HD=%d)\n", HD);
printf("Softmax-only test (HD=%d)\n", HD);
const float SCALE = 1.0f / sqrtf((float)HD);
int ok = 1;
ok &= test_single_T(1); // decode regression
ok &= test_single_T(2);
ok &= test_single_T(4);
ok &= test_single_T(8);
ok &= test_single_T(16);
ok &= test_single_T(32);
ok &= test_single_T(64);
ok &= test_single_T(128);
for (int T : {1, 4, 32, 128}) {
printf("T=%d: ", T);
printf("\n%s\n", ok ? "ALL PASSED" : "SOME FAILED");
return ok ? 0 : 1;
bf16_t *h_q = (bf16_t*)malloc(T * HD * sizeof(bf16_t));
bf16_t *h_k = (bf16_t*)malloc(SK * HD * sizeof(bf16_t));
float *h_rm = (float*)calloc(T, sizeof(float));
srand(42 + T);
for (int i=0;i<T*HD;i++) h_q[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
bf16_t *d_q, *d_k; float *d_rm;
cudaMalloc(&d_q, T*HD*sizeof(bf16_t));
cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
cudaMalloc(&d_rm, T*sizeof(float));
cudaMemcpy(d_q, h_q, T*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemset(d_rm, 0, T*sizeof(float));
int smem = 256 + 128 + 128*MMA_K_BF16*2*2 + 256;
test_softmax_only_kernel<HD><<<1, 192, smem>>>(d_q, d_k, d_rm, T, SK, SCALE);
cudaError_t err = cudaDeviceSynchronize();
if (err != cudaSuccess) {
printf("CUDA ERROR: %s\n", cudaGetErrorString(err));
} else {
cudaMemcpy(h_rm, d_rm, T*sizeof(float), cudaMemcpyDeviceToHost);
// Compute reference row_max
int ok = 1;
for (int t = 0; t < T; t++) {
float ref_max = -INFINITY;
for (int j = 0; j < SK; j++) {
float dot = 0;
for (int d = 0; d < HD; d++)
dot += bf16_to_f32_host(h_q[t*HD+d]) * bf16_to_f32_host(h_k[j*HD+d]);
ref_max = fmaxf(ref_max, dot * SCALE);
}
float err2 = fabsf(h_rm[t] - ref_max) / (fabsf(ref_max) + 1e-6f);
if (err2 > 0.01f) { ok = 0; printf("t=%d: got %.4f ref %.4f err %.4f ", t, h_rm[t], ref_max, err2); }
}
printf("%s (T=%d)\n", ok ? "OK" : "FAIL", T);
}
cudaFree(d_q); cudaFree(d_k); cudaFree(d_rm);
free(h_q); free(h_k); free(h_rm);
}
return 0;
}