biondizzle
6421f7c3f3
Evidence: TMA loads succeed with 128B-aligned GMEM on all descriptor configs. The bit-21 workaround was NOT needed. The 'misaligned address' crashes were caused by passing non-128B-aligned GMEM pointers to cp.async.bulk.tensor. Added docs/p4_tma_hang_resolution.md with root cause and fix. Cleaned up stale P4 test files.
32 lines
1.4 KiB
Markdown
32 lines
1.4 KiB
Markdown
# P4 Resolution: TMA Hang Root Cause
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## Date: 2026-05-30
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## Status: RESOLVED
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## Root Cause
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The TMA `cp.async.bulk.tensor.2d` hang was caused by **GMEM pointer misalignment**, NOT by descriptor format, swizzle mode, driver version, or bit-21 issues.
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## Evidence
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1. With 128-byte aligned GMEM and SMEM, TMA loads succeed with ALL descriptor configs (NO swizzle, SWIZZLE_128B, OOB_FILL_ZERO).
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2. With `cudaMalloc` (which guarantees only 256-byte alignment for the allocation base, but the actual tensor data pointer may not be 128B-aligned if offset), TMA loads crash with "misaligned address" or hang (mbarrier never signals).
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3. The bit-21 workaround was NOT needed — both original and bit-21-cleared descriptors work identically.
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## Fix
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For TMA loads in raw CUDA kernels:
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1. Ensure GMEM tensor base address is 128-byte aligned (`posix_memalign` or `cudaMalloc` + offset alignment check)
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2. Ensure SMEM buffer is 128-byte aligned (`__attribute__((aligned(128)))`)
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3. Use `cuTensorMapEncodeTiled` with outermost-first dims, byte strides
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## Descriptor bytes (128, 16) BF16, NO swizzle:
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```
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[0-7]: 00 00 00 f7 c3 71 00 00 (GMEM address)
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[8-15]: 10 05 00 00 02 00 00 00 (dims, strides, flags)
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```
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Bit 21 of word[1] is 0 in this case (address already has bit 21 clear).
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The bit-21 issue from CUTLASS only affects very small tensors where the
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address itself has bit 21 set.
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