biondizzle
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All HD=16/64/128/256 pass across MHA (4+8 heads), MQA, batched modes. cos 0.999997+, LSE matches reference. Updated CURRENT_ISSUE.md.
73 lines
3.7 KiB
Markdown
73 lines
3.7 KiB
Markdown
# CURRENT_ISSUE.md — FMHA 6-Warp Specialization
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## Status: Milestone 5 COMPLETE ✅ (multi-head grid launch with MHA/MQA/batch)
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### What works:
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- **6-warp kernel**: Warps 0-3 softmax/epilogue, Warp 4 MMA, Warp 5 data staging
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- **All HD values**: HD=16/64/128/256 pass with cos 0.999997+
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- **Warp role separation**: MMA and data loading on separate warps
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- **CTA-wide sync**: __syncthreads() between phases
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- **Multi-head grid launch**: grid=(1, n_h, batch), each CTA handles one head
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- **MQA**: k_head_stride=0 / v_head_stride=0 for shared KV heads
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- **Batched**: blockIdx.z for batch dimension
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- **LSE output**: per-row LSE for multi-segment KV merge
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- **FmhaParams struct**: stride-based tensor addressing, future-proof for GQA
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### Architecture:
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```
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Warp 0-3 (tid 0-127): Softmax + correction + epilogue
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- Read S from TMEM → softmax → write P to SMEM
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- After PV: read O from TMEM → BF16 → GMEM
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- T=1 decode: only warp 0 processes row 0
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Warp 4 (tid 128-159): MMA
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- tcgen05.mma SS for QK (N=128) and PV (N=16 sub-tiles)
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- TMEM alloc/dealloc
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Warp 5 (tid 160-191): Data staging
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- Load Q/K/V from GMEM to SMEM (canonical layout)
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- Fill sPk from s_p_vals
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```
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### Next milestones:
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1. **TMA loads** (Milestone 2): Replace direct GMEM reads with cp.async.bulk.tensor
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- Requires CUtensorMap creation on host
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- mbarrier synchronization
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- BLOCKED: cuTensorMapEncodeTiled 2D/3D/5D returns INVALID_VALUE on B200 driver v580.126.20
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- Alternative: Study CuTeDSL's TMA descriptor creation source code
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2. **Pipeline overlap** (Milestone 3): Double-buffer K/V loads
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- Load next K/V while computing current QK
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- mbarrier producer-consumer sync between warp 5 and warp 4
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- Depends on TMA loads (Milestone 2)
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3. **Multi-row softmax** (Milestone 4): Process all 128 rows (prefill T>1)
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- All 4 softmax warps process rows in parallel
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- Warp w handles rows [w*32, (w+1)*32) ∩ [0, T)
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4. ~~**Multi-head launch** (Milestone 5): grid=(1, n_h, batch)~~ ✅ DONE
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5. **Production integration** (Milestone 6): Hook into production.py
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### Files:
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- `dsv4/kernels/attention/fmha_6warp.cuh` — 6-warp kernel (single-head)
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- `dsv4/kernels/attention/fmha_6warp_multihead.cuh` — Multi-head grid launch kernel
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- `tests/unit/test_fmha_6warp_multihead.cu` — Multi-head test harness
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- `tests/unit/test_fmha_6warp_multihead_hd{16,64,128,256}.cu` — HD-specific wrappers
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### Layout D N=64 Bug (documented for NVIDIA):
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- tcgen05.mma with make_idesc(128, 64) skips TMEM cols 32-35, 48-51
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- Workaround: N=16 sub-tiles with TMEM offset n*16
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Mike, I've hit a wall with TMA. Here's the situation:
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1. **Raw `cuTensorMapEncodeTiled` doesn't work for ANY multi-dimensional descriptor on the B200.** 1D works, 2D/3D/5D all return INVALID_VALUE. This might be a driver issue (v580.126.20) or a parameter format I haven't figured out.
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2. **CuTeDSL's TMA works perfectly** (the existing FMHA kernel uses it), but I can't mix it with raw CUDA inline PTX easily.
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3. **The CuTeDSL FMHA with pv_n_tile=16 crashes** (illegal memory access) — needs CuTeDSL debugging.
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What I recommend: **focus on what works.** The raw CUDA 6-warp kernel is fully working at all HD values with direct GMEM reads. The TMA optimization can wait for:
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- A driver update that fixes `cuTensorMapEncodeTiled` for multi-dimensional descriptors, OR
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- Debugging the CuTeDSL pv_n_tile=16 crash (CuTeDSL-specific, different skill set), OR
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- Using CuTeDSL's TMA in a separate staging kernel
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Should I:
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- **A)** Continue debugging the CuTeDSL pv_n_tile=16 crash (might take a while, but gives us TMA + correct PV)
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- **B)** Move on to multi-head launch (more immediate production impact, no TMA needed)
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- **C)** Try to find the correct `cuTensorMapEncodeTiled` parameters by studying the CuTeDSL source code that creates the descriptors |