143 lines
9.7 KiB
Markdown
143 lines
9.7 KiB
Markdown
# DSV4 → vLLM: CUDA-Graph Safety / GPU-Native Requirements (PART 2 companion)
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**Goal:** the per-step decode forward must be fully GPU-native so vLLM can capture and replay it. No implicit device→host sync, no host control flow that reads a device value, no data-dependent shapes, no per-step host allocation. This doc gives you (A) a detector so you find every violation *once, upfront*, (B) the exhaustive hidden-CPU checklist, and (C) the DSV4-specific kernels that must be device-native.
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## The one rule that decides everything
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Branching on a **host-known integer** (step number, position, batch size, dtype, static shape) is graph-compatible — you capture one graph per bucket and the scheduler picks by that integer. Branching on a **device value** (sampled token, per-expert token count, top-k result, a mask, a norm/residual magnitude) is **not** — it must become device-side, fixed-shape work with masking. Every violation below is a place something reads a device value on the host.
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You do **not** need one monolithic graph. The standard pattern (what vLLM's DSV4 does) is *bucket by shape + break at attention + keep the dense parts captured.* Your job is to make each dynamic decision either device-side or isolated to that eager break.
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---
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## SECTION A — The detector (build this FIRST, before porting anything) ✅ DONE
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**Status:** Built and verified on B200 (2026-06-03). See `tests/unit/test_cuda_graph_readiness.py`.
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Results from detector runs on B200:
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- **Method 1** (sync debug mode): 0 violations in forward compute path
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- `dec_tid_buf.copy_(dec_tid_pinned)` is flagged but this is a valid graph-capturable pinned memcpy
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- All `.item()` syncs eliminated from hot path
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- **Method 2** (graph capture L0): **PASS** ✅
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- `torch.cuda.CUDAGraph()` capture of layer 0 decode step succeeds
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- All per-call allocations eliminated
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- All host reads of GPU values eliminated
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The detector:
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1. Grep for Section B sync patterns in hot path files
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2. Run one decode step with `torch.cuda.set_sync_debug_mode("error")`
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3. Attempt `torch.cuda.graph` capture of L0 decode step
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4. Report results to `/tmp/cuda_graph_readiness_results.json`
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Run via test harness:
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```bash
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fire_b200_test tests/unit/test_cuda_graph_readiness.py kernel-test /tmp/kernel-test.log 1800
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```
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---
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## SECTION B — The hidden-CPU checklist (grep the hot path for these) ✅ ADDRESSED
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**Explicit device→host transfers** — All `.item()` calls on hot path eliminated:
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- mhc.py `post_block`: removed `X_next.abs().max().item()` (122 syncs/step across 61 layers × 2 mHC)
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- All other `.item()` calls are guarded by `VERBOSE >= 2` and don't execute at VERBOSE=0
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- Warmup-gsa `.item()` calls run once at step 0, outside graph region
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**Data-dependent shapes** — Eliminated `torch.bincount` from MoE:
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- Replaced with `scatter_add_` into pre-allocated `_tokens_per_expert_buf` (fixed shape, GPU-only)
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- Pre-allocated `_ones_buf` to avoid per-call `torch.ones()`
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**Per-step host allocation** — All eliminated:
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- `torch.zeros()` in `_assemble_scales_single_group` → pre-allocated `_scale_a_buf` (linear.py, grouped_linear.py, shared_expert.py)
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- `torch.full()` for MoE l1_gsa → `self._l1_gsa_buf.fill_(l1_gs)`
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- `torch.empty()` for grouped_linear output → pre-allocated `_output_buf`
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- `mHCLayer.init_state` `.clone()` → `out_buf` parameter for in-place write
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- `torch.zeros_like` in quantize.py → scalar `0.0` in `torch.where`
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**Host control flow on device values** — Eliminated:
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- `dec_tid_buf[0] = python_int` → pinned CPU buffer + `copy_` (async, graph-capturable)
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- `expert_offsets[g] = python_int` → element-wise GPU multiply with pre-allocated range tensor
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- `if group_offsets[0] != 0` → unconditional GPU-only update (no host read of GPU tensor)
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**What is FINE (no sync, don't waste time on these)**
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- `.shape` / `.size()` / `.numel()` / `.dtype` (host metadata, no sync)
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- Branching on host-known ints (step/batch/static shape)
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- The **stop-token check, detokenize, and your BF16 precision-floor dequant** (all load-time or *outside* the captured graph — leave them on host, that's correct).
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- `dec_tid_buf.copy_(dec_tid_pinned)` — pinned CPU→GPU async memcpy, graph-capturable
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---
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## SECTION C — DSV4-specific kernels that must be GPU-native
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| # | Hazard | Status | Fix Applied |
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|---|--------|--------|-------------|
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| 1 | Compressor returns `None` for 3/4 (CSA) or 127/128 (HCA) decode steps | ⏳ Phase 2 (eager-break) | Compressor runs in eager section. Phase 2: device-side boundary detection + fixed-shape output |
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| 2 | KV grows each step → attention shape changes | ⏳ Phase 2 (eager-break) | Attention is the eager break. Phase 2: paged KV with fixed blocks + block table |
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| 3 | Indexer top-k → host reads selected count to size gather | ✅ DONE | Already fixed-shape gather (`topk_indices` is always `top_k` elements). No host read of count. |
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| 4 | MoE top-6 → per-expert token counts drive per-expert launches | ✅ DONE | `torch.bincount` → `scatter_add_` into pre-allocated buffer. Expert offsets are GPU tensors. |
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| 5 | Next token / positions managed on host, fresh tensors per step | ✅ DONE | Pre-allocated pinned CPU buffers + `copy_` to GPU. No per-step allocation. |
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Also confirmed:
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- **Sinkhorn** runs a **fixed 20 iterations with no host convergence check** ✅
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- **Sampler** is device-side; the EOS/stop decision is a host step **outside** the graph ✅
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- **Router** is graph-safe: pre-allocated output buffers, GPU-only operations ✅
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- **mHC** is graph-safe: fixed-iteration Sinkhorn, no `.item()` on hot path ✅
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### Architectural Decision: Eager-Break-at-Attention (Phase 1) — UPDATED 2026-06-04
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The per-layer compute is split into **two graph-captured regions** with eager attention in between:
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- **Graph A** (captured): mHC pre_block(attn) + fused RMSNorm + quantize + q_a + q_a_norm + q_b + kv projections
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- Outputs written to pre-allocated buffers: x_normed, q_heads, kv_3d, ctx_a_B, ctx_a_C, X_mid
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- **Eager** (NOT captured): Compressor → Indexer → KV gather → FMHA → inverse RoPE → o_a + o_b → F_attn
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- Dynamic shapes (FMHA seq_len, compressor returns None) → cannot be captured
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- `forward_attention()` accepts optional `q_heads`/`kv_3d` to skip projections when called from graph replay
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- **Graph B** (captured): mHC post_block(attn) + FFN mHC + RMSNorm + quantize + Router + MoE + SE + mHC post_block(ffn)
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- Reads F_attn from pre-allocated buffer (written by eager attention)
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- Writes X_next to pre-allocated output buffer
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**Rationale**: FMHA has dynamic sequence length; compressor/KV are data-dependent. Capturing the compute-heavy parts (projections, MoE, SE) eliminates ~94ms of Python dispatch overhead per step. The attention path (which is NOT compute-heavy for T=1 decode) runs eagerly with negligible overhead.
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**Phase 2**: Paged KV + device-side compressor → full graph capture for vLLM integration.
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---
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## SECTION D — Integration order
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1. ✅ **Build Section A's detector and run it on the current forward** — DONE. `tests/unit/test_cuda_graph_readiness.py` on B200.
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2. ✅ **Fix Section C's five device-native kernels** — 3/5 done, 2 deferred to Phase 2 with architectural decision.
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3. ✅ **Re-run capture-under-test until it captures clean** — WORKING on all 8 GPUs! Root cause: multi-GPU requires explicit `torch.cuda.Stream(device=device)`.
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4. ⬜ **Gate every commit on the capture test** — Not yet implemented.
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### Next Steps (for next session)
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1. ~~**Continue fixing per-step allocations in graph capture path**~~ ✅ DONE
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2. ~~**Verify swizzled scale buffers are allocated before graph capture**~~ ✅ DONE (SE bug fixed)
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3. ~~**Test graph capture on B200**~~ ✅ DONE — working with 0.28s/token
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4. ~~**Extend capture to all 61 layers**~~ ✅ DONE — all 61 layers captured and replayed
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5. ~~**Replay verification**~~ ✅ DONE — graph replay matches eager forward
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6. ~~**Benchmark**~~ ✅ DONE — 0.28s/token (2x faster than eager 0.55s/token)
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7. **Gate commits on capture test** — implement CI check
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8. **Optimize stream sync** — replace `torch.cuda.synchronize()` with event-based waits
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9. **Phase 2**: Paged KV + device-side compressor for full vLLM graph capture
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## Guardrails
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- Keep the stop-check, detokenize, and load-time BF16 dequant on the host — they're outside the captured region by design; don't contort them to be "graph-safe."
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- **Phase 1 uses eager-break-at-attention.** Phase 2 adds paged KV. Don't retrofit paged KV into Phase 1 — it's a separate integration.
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- Host-known-int branching is allowed; only device-value branching must be eliminated. Don't over-correct and try to make legitimate shape/dtype dispatch device-side.
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## Violation Fix Log
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| Commit | Description |
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|--------|-------------|
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| `a9ea303` | mhc.py `.item()` removal, linear/shared_expert pre-alloc, quantize gsa fix |
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| `46a3a51` | mHCLayer.init_state out_buf, dec_X_buf pre-allocation |
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| `0ca7bed` | Pinned CPU buffers for token transfer, grouped_linear expert_offsets GPU-only |
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| `e07d798` | _assemble_scales_single_group correctly-sized view for swizzle |
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| `df05289` | Remove conditional host read of GPU tensor in grouped_linear |
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| `84655d0` | MoE bincount → scatter_add_, MoE torch.full → fill_() |
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| `f13a81d` | grouped_linear scale_a_buf pre-alloc, quantize zeros_like → scalar 0.0 |
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| `518a1d3` | MoE scatter_add_ int64 indices, fix second bincount call |
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| `80bb27f` | gsa broadcast: reshape for M=1 decode (no stride-0), contiguous for M>1 prefill |
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| `6dc2f22` | **CRITICAL: _l1_out_buf 2x too narrow → GPU memory corruption (root cause of ALL cudaErrorInvalidValue errors)**. Also: all GEMM output buffers pre-allocated, gsa copy_ → scalar assignment |
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| `69e15f1` | Blackwell swizzle CUDA kernel for graph capture, swizzled output buffers |
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| `ffa7842` | Dense router: BF16 GEMM instead of FP32 conversion during graph capture |
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