biondizzle 44c4bade5f Rewrite fmha_sm100_tc.cuh with working N=16 PV sub-tile approach ...

Production FMHA kernel template for Blackwell SM100:
- FmhaSm100Kernel<HD>::launch(q, k, v, o, s_k, scale, stream)
- QK: SS MMA N=128, one K-tile at a time
- PV: SS MMA N=16 sub-tiles (HD/16 calls per K-tile)
- Epilogue: TMEM → regs → BF16 → GMEM
- ~25KB SMEM for all HD values
- All HD=16/64/128/256 pass with cos 0.999997+

2026-05-28 16:04:11 +00:00

..

attention

Rewrite fmha_sm100_tc.cuh with working N=16 PV sub-tile approach

2026-05-28 16:04:11 +00:00

cache

KV Cache: schema, allocator, pools, manager, append_swa kernel

2026-05-22 00:08:38 +00:00

compressor

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

cuda

fix quantize_nvfp4 kernel: use proven single-thread-per-CTA pattern from deinterleave_quantize.cu

2026-05-25 16:21:44 +00:00

decode

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

gemm

NVFP4-1.1: Mark fp4_quant.py as toolchain-blocked, clean up test files

2026-05-28 04:59:01 +00:00

indexer

Indexer: score+topk kernel, gather KV, compute_valid_lens

2026-05-22 01:20:39 +00:00

router

Router: Blackwell-native fused decode kernel — real CuTeDSL implementation

2026-05-21 22:04:20 +00:00

__init__.py

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00