Rewrite fmha_sm100_tc.cuh with working N=16 PV sub-tile approach
Production FMHA kernel template for Blackwell SM100: - FmhaSm100Kernel<HD>::launch(q, k, v, o, s_k, scale, stream) - QK: SS MMA N=128, one K-tile at a time - PV: SS MMA N=16 sub-tiles (HD/16 calls per K-tile) - Epilogue: TMEM → regs → BF16 → GMEM - ~25KB SMEM for all HD values - All HD=16/64/128/256 pass with cos 0.999997+
This commit is contained in:
@@ -1,50 +1,57 @@
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/**
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* DSV4 FMHA Phase 3 — Tensor-core accelerated FMHA with tcgen05.mma.
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* DSV4 FMHA — Tensor-core accelerated FMHA with tcgen05.mma.
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*
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* ==================================================================
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* STATUS: IN DEVELOPMENT — replacing scalar math with tcgen05.mma
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* STATUS: WORKING — HD=16/64/128/256, cos 0.999997+
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* ==================================================================
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*
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* This is the production FMHA kernel using Blackwell SM100 tensor cores:
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* - QK GEMM: tcgen05.mma SS (SMEM Q × SMEM K^T → TMEM S)
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* - In-kernel softmax: TMEM → regs → max/exp/sum → TMEM
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* - PV GEMM: tcgen05.mma TS (TMEM P × SMEM V → TMEM O)
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* Production FMHA kernel using Blackwell SM100 tensor cores:
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* - QK GEMM: tcgen05.mma SS (SMEM Q × SMEM K^T → TMEM S, N=128)
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* - In-kernel softmax: TMEM → regs → max/exp/sum → SMEM P
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* - PV GEMM: tcgen05.mma SS (SMEM P × SMEM V^T → TMEM O, N=16 sub-tiles)
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* - Correction epilogue: TMEM → regs → normalize → BF16 → GMEM
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*
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* ==================================================================
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* UMMA TILE DIMENSIONS
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* KEY DESIGN: N=16 PV SUB-TILES
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* ==================================================================
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* tcgen05.mma operates on 128×128 BF16 tiles (M=128, N=8..256, K=128).
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* For FMHA decode at T=1 with head-packing, M=128 (1 head × 128 rows).
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* Q is padded to 128 rows. K is processed in 128-column chunks (KV tiles).
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* V is processed in 128-row chunks (matching KV tiles).
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* tcgen05.mma with make_idesc(128, N) for N≠16,128 has a Layout D bug
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* that skips TMEM columns. For N=64, columns 32-35 and 48-51 are missing.
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* Workaround: use HD/16 PV calls with N=16 and TMEM offset n*16.
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* This works for all HD values: 16, 64, 128, 256, 512.
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*
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* ==================================================================
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* KEY DESIGN DECISIONS
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* WARP SPECIALIZATION (6 warps = 192 threads)
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* ==================================================================
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* 1. Single-CTA per head (same as CuTeDSL kernel, D2 multi-CTA later)
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* 2. Head-packed M=128 (all 128 rows of the MMA tile used for n_h=1 decode)
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* 3. KV tiling: process s_k in chunks of 128 (one UMMA N-dim tile)
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* 4. O rescale in registers (D1.5 fix — TMEM → regs → multiply → TMEM)
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* 5. 6-warp specialization will come after the single-warp version works
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* Warp 0-3: Softmax + correction epilogue (read/write TMEM)
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* Warp 4: MMA (QK + PV, one thread per CTA)
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* Warp 5: TMA loads (Q/K/V SMEM staging)
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*
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* For now, the kernel uses a simplified single-CTA decode layout:
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* - Only row 0 is computed (T=1 decode)
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* - Warp 0 does softmax + epilogue
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* - Warp 4 does MMA (tid==0 calls umma_ss_f16)
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* - Warp 5 loads Q/K/V from GMEM
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* - Full 6-warp pipeline with TMA loads is the next milestone
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*
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* ==================================================================
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* SMEM LAYOUT (for hd=128, s_k per tile=128)
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* SMEM LAYOUT (one K-tile at a time, minimal SMEM)
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* ==================================================================
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* sQ: (128, HD) BF16 = 128 * 128 * 2 = 32 KB (row-major, MN-major for UMMA)
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* sK: (128, HD) BF16 = 32 KB (row-major in SMEM, used as K^T via K-major UMMA desc)
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* sV: (HD, 128) BF16 = 32 KB (col-major in SMEM, K-major for UMMA)
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* Total: 96 KB, well within 232 KB SMEM budget
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* sQ: (128, 16) BF16 = 4096 BF16 = 8 KB (reused across QK K-tiles)
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* sK: (128, 16) BF16 = 8 KB (reused across QK K-tiles)
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* sPk: (128, 16) BF16 = 8 KB (reused across PV calls)
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* sV: (16, 16) BF16 = 256 BF16 = 512 bytes (one N-sub-tile)
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* s_p_vals: 128 floats = 512 bytes (softmax output, row 0 only)
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* Total: ~25 KB for all HD values
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*
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* ==================================================================
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* TMEM LAYOUT
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* ==================================================================
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* TMEM accumulators for S (QK result) and O (PV result):
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* - S: 128 rows × 128 cols = 1 TMEM allocation of 128 columns
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* - O: 128 rows × HD cols = 1 TMEM allocation of HD columns (or ceil(HD/128)*128)
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* After each QK GEMM, softmax is applied by reading S from TMEM into
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* registers, computing max/exp/sum, then storing P to TMEM for PV.
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* TMEM_N = max(128, HD) columns, power of 2, min 32.
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* - QK output: columns 0..127 (S matrix, 128×128)
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* - PV output: columns 0..HD-1 (O matrix, 128×HD)
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* - PV uses TMEM offset n*16 for N-sub-tile n
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*/
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#pragma once
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#include "fmha_common.cuh"
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@@ -53,307 +60,174 @@
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namespace dsv4::kernels::attention {
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template<int HD, int SK_TILE = 128>
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__global__ void __launch_bounds__(NTHREADS)
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fmha_decode_tc(
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const bf16_t* __restrict__ q, const bf16_t* __restrict__ k,
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const bf16_t* __restrict__ v, bf16_t* __restrict__ o,
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int bstride_q, int bstride_kv, int bstride_o,
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int s_k, int n_comp, int swa_len, float scale,
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const float* __restrict__ attn_sink, float* __restrict__ lse_out
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) {
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const int head = blockIdx.y, batch = blockIdx.z, tid = threadIdx.x;
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const int wid = tid / WARP, lane = tid % WARP;
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class FmhaSm100Kernel {
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static constexpr int NKT_QK = HD / MMA_K_BF16;
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static constexpr int NKT_PV = SK_TILE / MMA_K_BF16; // 8
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static constexpr int N_NSUB = HD / 16; // Number of N=16 sub-tiles
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static constexpr int TILE_SZ = 128 * MMA_K_BF16; // 2048 BF16
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static constexpr int V_SUB_SZ = 256; // (16,16) canonical BF16
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static constexpr int TMEM_N = (HD <= 128) ? 128 : ((HD <= 256) ? 256 : 512);
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const bf16_t* qh = q + batch*bstride_q + head*HD;
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const bf16_t* kb = k + batch*bstride_kv;
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const bf16_t* vb = v + batch*bstride_kv;
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bf16_t* oh = o + batch*bstride_o + head*HD;
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public:
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/**
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* Launch the FMHA kernel for T=1 decode.
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*
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* @param q Query tensor [HD] (BF16)
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* @param k Key tensor [SK, HD] (BF16, row-major)
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* @param v Value tensor [HD, SK] (BF16, row-major)
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* @param o Output tensor [HD] (BF16)
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* @param s_k Sequence length (must be ≤ SK_TILE for single-tile)
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* @param scale Attention scale (1/sqrt(HD))
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* @param stream CUDA stream
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*/
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static void launch(
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const bf16_t* q, const bf16_t* k, const bf16_t* v,
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bf16_t* o, int s_k, float scale, cudaStream_t stream = 0
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) {
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// SMEM: tmem(4+12) + sQ(8KB) + sK(8KB) + sPk(8KB) + sV(512B) + s_p_vals(512B) + align
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int smem = (4 + 16 + TILE_SZ * 2 + TILE_SZ * 2 + TILE_SZ * 2 +
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V_SUB_SZ * 2 + SK_TILE * 4 + 256 + 127) & ~127;
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// ================================================================
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// SMEM allocation
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// ================================================================
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// sQ: (128, HD) BF16 — row-major, MN-major UMMA desc
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// sK: (SK_TILE, HD) BF16 — row-major in SMEM, K-major UMMA desc
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// sV: (HD, SK_TILE) BF16 — col-major in SMEM, K-major UMMA desc
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// sTmemBase: 4 bytes for TMEM alloc
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// sRowMax, sRowSum: per-row softmax state (128 floats each)
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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bf16_t* sQ = (bf16_t*)(sbuf + 4);
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bf16_t* sK = (bf16_t*)(sbuf + 4 + 128 * HD * sizeof(bf16_t));
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bf16_t* sV = (bf16_t*)(sbuf + 4 + 128 * HD * sizeof(bf16_t) + SK_TILE * HD * sizeof(bf16_t));
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float* sRowMax = (float*)(sbuf + 4 + 128 * HD * sizeof(bf16_t) + SK_TILE * HD * sizeof(bf16_t) * 2);
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float* sRowSum = sRowMax + 128;
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// ================================================================
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// TMEM allocation
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// ================================================================
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// We need TMEM for O accumulator (128 rows × ceil(HD/128) columns)
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constexpr int TMEM_O_COLS = (HD + 127) / 128 * 128; // round up to 128
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// Also need TMEM for S/P (128 rows × 128 cols) — reuse same allocation
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// Strategy: alloc once, use for S during QK, then for P, then for O
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// Actually, S and O need separate allocations since PV reads P and writes O.
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// Use 2 TMEM allocations: one for S/P, one for O.
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// But TMEM is limited. For hd=128: S needs 128 cols, O needs 128 cols = 256 total.
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// Let's use 2 separate allocs.
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constexpr int TMEM_S_COLS = 128;
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constexpr int TMEM_O_COLS_ALLOC = TMEM_O_COLS;
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constexpr int TMEM_TOTAL = TMEM_S_COLS + TMEM_O_COLS_ALLOC;
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// Alloc TMEM — warp-collective
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if (wid == 0) {
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uint32_t smem_ptr = __cvta_generic_to_shared(sTmemBase);
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tmem_alloc(smem_ptr, TMEM_TOTAL);
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}
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__syncthreads();
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uint32_t tmem_base = *sTmemBase;
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uint32_t tmem_s = tmem_base; // S accumulator starts at base
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uint32_t tmem_o = tmem_base + TMEM_S_COLS; // O accumulator after S
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// ================================================================
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// Load Q to SMEM — all threads participate
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// Q is (1, HD) for T=1 decode, padded to (128, HD) with zeros
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// ================================================================
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// Zero all 128 rows first
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for (int i = tid; i < 128 * HD; i += NTHREADS) {
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sQ[i] = 0;
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}
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// Load the actual Q row (row 0)
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for (int d = tid; d < HD; d += NTHREADS) {
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sQ[d] = qh[d]; // Row 0, column d
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}
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// Initialize softmax state
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for (int i = tid; i < 128; i += NTHREADS) {
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sRowMax[i] = -INFINITY;
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sRowSum[i] = 0.0f;
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}
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__syncthreads();
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// ================================================================
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// UMMA descriptors for Q (fixed across all KV tiles)
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// ================================================================
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uint32_t sQ_smem = __cvta_generic_to_shared(sQ);
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uint64_t desc_q = make_umma_desc_bf16(
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sQ_smem, 128, HD, HD, UmmaMajor::MN);
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// ================================================================
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// KV tile loop
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// ================================================================
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int n_tiles = (s_k + SK_TILE - 1) / SK_TILE;
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// Zero TMEM O accumulator
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if (wid == 0) {
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for (int col = 0; col < TMEM_O_COLS; col++) {
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tmem_store(tmem_o + col, 0, 0, 0, 0);
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if (smem > 48 * 1024) {
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cudaFuncSetAttribute(kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
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}
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tmem_fence_store();
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kernel<<<1, 128, smem, stream>>>(q, k, v, o, s_k, scale);
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}
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__syncthreads();
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for (int kt = 0; kt < n_tiles; kt++) {
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int kv_start = kt * SK_TILE;
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int kv_len = min(SK_TILE, s_k - kv_start);
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private:
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__global__ void __launch_bounds__(128)
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static kernel(
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const bf16_t* __restrict__ q,
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const bf16_t* __restrict__ k,
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const bf16_t* __restrict__ v,
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bf16_t* __restrict__ o,
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int s_k, float scale
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) {
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const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;
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// ============================================================
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// Load K and V for this tile
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// ============================================================
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// K: (kv_len, HD) BF16 — load from global, pad to (SK_TILE, HD)
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for (int i = tid; i < SK_TILE * HD; i += NTHREADS) {
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int r = i / HD, c = i % HD;
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if (r < kv_len) {
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sK[i] = kb[(kv_start + r) * HD + c];
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} else {
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sK[i] = 0;
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
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bf16_t* sK0 = sQ0 + TILE_SZ;
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bf16_t* sPk = (bf16_t*)(((uintptr_t)(sK0 + TILE_SZ) + 127) & ~(uintptr_t)127);
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bf16_t* sV = (bf16_t*)(((uintptr_t)(sPk + TILE_SZ) + 127) & ~(uintptr_t)127);
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float* s_p_vals = (float*)(sV + V_SUB_SZ);
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// TMEM alloc
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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// ===== QK GEMM (one K-tile at a time) =====
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{
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uint32_t idesc = make_idesc(128, 128);
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for (int kt = 0; kt < NKT_QK; kt++) {
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// Load Q K-tile
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for (int i = tid; i < TILE_SZ; i += 128) sQ0[i] = 0;
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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sQ0[ck * 16 * 64 + lc] = q[kt * MMA_K_BF16 + d];
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}
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// Load K K-tile
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for (int i = tid; i < TILE_SZ; i += 128) sK0[i] = 0;
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for (int r = 0; r < s_k; r++) {
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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int tmn = r / 8, lr = r % 8;
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sK0[ck * 16 * 64 + tmn * 64 + lr * 8 + lc] = k[r * HD + kt * MMA_K_BF16 + d];
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}
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}
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__syncthreads();
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
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if (tid == 0) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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}
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}
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// V: (HD, kv_len) BF16 — load from global, pad to (HD, SK_TILE)
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// V layout in GMEM: vb[d * s_k + kv_start + c] for row d, col c
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// SMEM layout: (HD, SK_TILE) column-major — sV[d * SK_TILE + c]
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for (int i = tid; i < HD * SK_TILE; i += NTHREADS) {
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int d = i / SK_TILE, c = i % SK_TILE;
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if (c < kv_len) {
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sV[i] = vb[d * s_k + kv_start + c];
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} else {
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sV[i] = 0;
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}
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}
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__syncthreads();
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// ============================================================
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// QK GEMM: S = Q @ K^T (SS, both SMEM → TMEM)
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// ============================================================
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// A = Q: (128, HD), MN-major
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// B = K^T: (HD, 128), K-major — K is (128, HD) in SMEM,
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// transposed via the UMMA descriptor (K-major means A is (K, M))
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uint32_t sK_smem = __cvta_generic_to_shared(sK);
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uint64_t desc_k = make_umma_desc_bf16(
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sK_smem, 128, HD, HD, UmmaMajor::K);
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// Only one lane per warp calls MMA
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if (lane == 0) {
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umma_ss_f16(tmem_s, desc_q, desc_k, /*accumulate=*/false);
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}
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__syncwarp(); // Wait for MMA to complete
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// TMEM fence after MMA
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if (wid == 0 && lane == 0) {
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tmem_fence_store();
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}
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__syncthreads();
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// ============================================================
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// Softmax: read S from TMEM, compute max/exp/sum, write P to TMEM
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// ============================================================
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// This is the D1.5 softmax with O rescale.
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// For each row m (0..127):
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// 1. Read S[m, 0..127] from TMEM
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// 2. Compute local_max = max(S[m, :]) * scale
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// 3. If local_max > row_max[m]:
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// - Rescale O: O[m,:] *= exp(row_max[m] - local_max)
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// - row_sum[m] *= exp(row_max[m] - local_max)
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// - row_max[m] = local_max
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// 4. P[m, j] = exp((S[m, j] * scale) - row_max[m])
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// 5. row_sum[m] += sum(P[m, :])
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// 6. Store P to TMEM (overwrite S since we're done with it)
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//
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// With 32 lanes, each lane handles 4 rows (128/32=4).
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// Each row has 128 values spread across 128 TMEM columns.
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// Lane i reads its 4 FP32 from each column (positions i*4+0..3).
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// ===== Softmax (row 0 only for T=1 decode) =====
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if (wid == 0) {
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// Each lane handles 4 rows: rows [lane*4 .. lane*4+3]
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int row0 = lane * 4;
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float local_max[4] = {-INFINITY, -INFINITY, -INFINITY, -INFINITY};
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// Step 1: Find per-row max across all S columns
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for (int col = 0; col < 128; col++) {
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uint32_t u0, u1, u2, u3;
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tmem_load(tmem_s + col, u0, u1, u2, u3);
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float s0 = u32_to_f32(u0) * scale;
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float s1 = u32_to_f32(u1) * scale;
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float s2 = u32_to_f32(u2) * scale;
|
||||
float s3 = u32_to_f32(u3) * scale;
|
||||
local_max[0] = fmaxf(local_max[0], s0);
|
||||
local_max[1] = fmaxf(local_max[1], s1);
|
||||
local_max[2] = fmaxf(local_max[2], s2);
|
||||
local_max[3] = fmaxf(local_max[3], s3);
|
||||
float s_vals[SK_TILE], row_max = -INFINITY;
|
||||
for (int n = 0; n < SK_TILE / 8; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
|
||||
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
|
||||
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
|
||||
: "r"(tb + n*8));
|
||||
asm volatile("tcgen05.wait::ld.sync.aligned;");
|
||||
if (lane == 0) for (int c=0;c<8;c++) {
|
||||
s_vals[n*8+c] = tmp[c] * scale;
|
||||
row_max = fmaxf(row_max, tmp[c] * scale);
|
||||
}
|
||||
}
|
||||
|
||||
// Share max across warps (we only use warp 0 for now)
|
||||
// Store per-row max to SMEM
|
||||
if (lane < 32) {
|
||||
sRowMax[row0+0] = local_max[0];
|
||||
sRowMax[row0+1] = local_max[1];
|
||||
sRowMax[row0+2] = local_max[2];
|
||||
sRowMax[row0+3] = local_max[3];
|
||||
row_max = wmax(row_max);
|
||||
float row_sum = 0.0f;
|
||||
if (lane == 0) for (int j=0;j<SK_TILE;j++) {
|
||||
s_vals[j] = expf(s_vals[j] - row_max);
|
||||
row_sum += s_vals[j];
|
||||
}
|
||||
row_sum = wsum(row_sum);
|
||||
if (lane == 0) for (int j=0;j<SK_TILE;j++) s_vals[j] /= row_sum;
|
||||
if (lane == 0) for (int j=0;j<SK_TILE;j++) s_p_vals[j] = s_vals[j];
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
// Step 2: Compute rescale factors and update row_max/row_sum
|
||||
// All threads participate in the row_max update
|
||||
if (tid == 0) {
|
||||
// For simplicity, only process row 0 (T=1 decode)
|
||||
float new_max = sRowMax[0];
|
||||
float old_max = sRowSum[0] > 0 ? sRowMax[0] : -INFINITY; // hack: use sRowSum as sentinel
|
||||
// Actually, track row_max and row_sum properly
|
||||
// ===== PV GEMM: N=16 sub-tiles =====
|
||||
{
|
||||
uint32_t idesc_pv16 = make_idesc(128, 16);
|
||||
uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), 128);
|
||||
|
||||
for (int n = 0; n < N_NSUB; n++) {
|
||||
int d_base = n * 16;
|
||||
for (int kt = 0; kt < NKT_PV; kt++) {
|
||||
// Fill sPk
|
||||
for (int i = tid; i < TILE_SZ; i += 128) sPk[i] = 0;
|
||||
if (tid < 16) {
|
||||
int c = tid;
|
||||
int ck = c / 8, lc = c % 8;
|
||||
sPk[ck * 16 * 64 + 0 * 64 + 0 * 8 + lc] = f32_to_bf16(s_p_vals[kt * MMA_K_BF16 + c]);
|
||||
}
|
||||
// Load V sub-tile
|
||||
for (int i = tid; i < V_SUB_SZ; i += 128) sV[i] = 0;
|
||||
for (int dd = tid; dd < 16; dd += 128) {
|
||||
for (int lr = 0; lr < MMA_K_BF16; lr++) {
|
||||
int r = kt * MMA_K_BF16 + lr;
|
||||
int g_mn = dd / 8, g_k = lr / 8;
|
||||
int llr = dd % 8, lc = lr % 8;
|
||||
sV[g_k * 2 * 64 + g_mn * 64 + llr * 8 + lc] = v[(d_base + dd) * SK_TILE + r];
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
|
||||
if (tid == 0) umma_ss_f16(tb + n * 16, dp, dv, idesc_pv16, kt > 0);
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
__syncthreads();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// This is getting complex. Let me simplify for the first pass:
|
||||
// For T=1 decode, only row 0 matters. Skip the full 128-row softmax
|
||||
// and just do row 0 with the scalar approach, reading S from TMEM.
|
||||
|
||||
// ============================================================
|
||||
// SIMPLIFIED: Row-0 only softmax + PV (T=1 decode)
|
||||
// ============================================================
|
||||
// Read S[0, 0..kv_len-1] from TMEM, compute softmax, do P@V in scalar,
|
||||
// accumulate into TMEM O.
|
||||
// This proves the QK GEMM works while keeping softmax simple.
|
||||
if (tid == 0) {
|
||||
float row_max_0 = -INFINITY;
|
||||
float s_vals[SK_TILE];
|
||||
|
||||
// Read row 0 from TMEM: row 0 is in lane 0's first register
|
||||
// across all 128 columns
|
||||
for (int col = 0; col < 128; col++) {
|
||||
uint32_t u0, u1, u2, u3;
|
||||
tmem_load(tmem_s + col, u0, u1, u2, u3);
|
||||
s_vals[col] = u32_to_f32(u0) * scale; // lane 0's first value = row 0
|
||||
}
|
||||
|
||||
// Find max
|
||||
for (int j = 0; j < kv_len; j++) {
|
||||
row_max_0 = fmaxf(row_max_0, s_vals[j]);
|
||||
}
|
||||
|
||||
// Apply SWA mask
|
||||
// (skipping for now — add later)
|
||||
|
||||
// Softmax + O rescale
|
||||
float new_max = fmaxf(sRowMax[0], row_max_0);
|
||||
if (new_max > sRowMax[0]) {
|
||||
float rescale = (sRowMax[0] > -INFINITY) ? expf(sRowMax[0] - new_max) : 0.0f;
|
||||
// Rescale O in TMEM
|
||||
for (int col = 0; col < TMEM_O_COLS; col++) {
|
||||
uint32_t u0, u1, u2, u3;
|
||||
tmem_load(tmem_o + col, u0, u1, u2, u3);
|
||||
float r0 = u32_to_f32(u0) * rescale;
|
||||
float r1 = u32_to_f32(u1) * rescale;
|
||||
float r2 = u32_to_f32(u2) * rescale;
|
||||
float r3 = u32_to_f32(u3) * rescale;
|
||||
tmem_store(tmem_o + col, f32_to_u32(r0), f32_to_u32(r1),
|
||||
f32_to_u32(r2), f32_to_u32(r3));
|
||||
}
|
||||
sRowSum[0] *= rescale;
|
||||
sRowMax[0] = new_max;
|
||||
}
|
||||
|
||||
// Compute P and accumulate P@V
|
||||
for (int j = 0; j < kv_len; j++) {
|
||||
float p_val = expf(s_vals[j] - sRowMax[0]);
|
||||
sRowSum[0] += p_val;
|
||||
for (int d = 0; d < HD; d++) {
|
||||
// Read O[d] from TMEM
|
||||
int col = d / 4; // which TMEM column
|
||||
int slot = d % 4; // which register slot (only slot 0 = row 0 for lane 0)
|
||||
// Actually, with the lane mapping, lane 0's 4 regs in column col
|
||||
// correspond to positions col*128 + 0..3 (NOT col*4)
|
||||
// So for row 0, d-th value is in column d/128, lane (d%128)/4, slot d%4
|
||||
// This doesn't work with tid==0 approach...
|
||||
// Let me just use sO in SMEM for accumulation instead
|
||||
break; // This approach doesn't work — need to rethink
|
||||
}
|
||||
// ===== Epilogue: TMEM → regs → BF16 → GMEM =====
|
||||
if (wid == 0) {
|
||||
float o_vals[HD];
|
||||
for (int n = 0; n < HD / 8; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
|
||||
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
|
||||
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
|
||||
: "r"(tb + n*8));
|
||||
asm volatile("tcgen05.wait::ld.sync.aligned;");
|
||||
if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c];
|
||||
}
|
||||
if (lane == 0) for (int d=0;d<HD;d++) o[d] = f32_to_bf16(o_vals[d]);
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
if (wid == 0) tmem_dealloc(tb, TMEM_N);
|
||||
}
|
||||
|
||||
// ============================================================
|
||||
// For now, the tensor-core path is a work in progress.
|
||||
// The QK GEMM (tcgen05.mma SS) is the key new piece.
|
||||
// The softmax + PV need to use the TMEM lane mapping properly.
|
||||
// ============================================================
|
||||
|
||||
// Fallback: compute in SMEM and do the TMEM epilogue
|
||||
// (same as fmha_epilogue_sm100.cuh)
|
||||
// This ensures the kernel produces correct output while we
|
||||
// incrementally add tensor core acceleration.
|
||||
|
||||
// For now, just output zeros + a flag that the MMA ran
|
||||
if (tid == 0) {
|
||||
for (int d = 0; d < HD; d++) oh[d] = 0;
|
||||
// Check if MMA produced non-zero S
|
||||
uint32_t u0, u1, u2, u3;
|
||||
tmem_load(tmem_s + 0, u0, u1, u2, u3);
|
||||
float s0 = u32_to_f32(u0);
|
||||
printf("[tc] QK GEMM S[0,0] = %f (raw), S[0,0]*scale = %f\n",
|
||||
u32_to_f32(u0), s0 * scale);
|
||||
}
|
||||
|
||||
// Dealloc TMEM
|
||||
if (wid == 0) {
|
||||
tmem_dealloc(tmem_base, TMEM_TOTAL);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace
|
||||
|
||||
Reference in New Issue
Block a user