268 lines
15 KiB
Markdown
268 lines
15 KiB
Markdown
# NVFP4 MegaMoE Kernel
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Full NVFP4 inference pipeline for DeepSeek-V4 on NVIDIA Blackwell (SM100). The entire model — MoE experts, shared experts, and attention projections — runs in native NVFP4 with zero dequantization overhead.
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## What This Is
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A native NVFP4 inference stack for DeepSeek-V4:
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**MoE Experts** — CuTeDSL ScaledGroupedGemmKernel (our work):
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```
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BF16 input → quantize to NVFP4
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L1 GEMM: NVFP4 × NVFP4 → BF16 (gate + up)
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SiLU(gate) * up → BF16 (only nonlinear — can't avoid BF16 here)
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Re-quantize → NVFP4
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L2 GEMM: NVFP4 × NVFP4 → BF16 (down_proj)
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Scatter with routing weights → BF16 output
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```
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**Attention Projections** — FlashInferCutlassNvFp4LinearKernel (vLLM built-in):
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- `wq_b`, `wo_b`, `fused_wqa_wkv` — native NVFP4, no conversion
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- `wo_a` — NVFP4→FP8 for `fp8_einsum` (only attention weight that needs conversion)
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- Compressor — BF16 (weight_loader stacking issue, small matmul)
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**Shared Experts** — FlashInferCutlassNvFp4LinearKernel (vLLM built-in):
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- `gate_up_proj`, `down_proj` — native NVFP4
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Both GEMM types use `float4_e2m1fn_x2` for weights, `float8_e4m3fn` for block scales, `float32` for global scales. BF16 is used only for SiLU activation, the final MoE scatter, and the compressor — the minimum possible.
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## Current Status: vLLM Inference Running 🎉
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**vLLM serves DeepSeek-V4-Pro NVFP4 with cudagraph enabled.** The model loads, cudagraph captures successfully, and inference runs. Output quality is still being tuned (garbage tokens currently), but this is the first time the entire pipeline — model loading, kernel compilation, cudagraph capture, and inference — works end-to-end.
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**Test Results:**
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- `tests/layertest.py`: cosine 0.988 vs BF16 reference ✅
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- `tests/cudagraph_test.py`: capture + replay PASS ✅
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- vLLM inference: running with cudagraph, output quality in progress
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## How We Got Here
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### The C++ CUTLASS Kernel Was Broken
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The original kernel was a C++ `.cu` file using CUTLASS's C++ API directly. It passed all the simple tests (uniform data → exact output, SF remap verifier → 0 errors) but produced **cosine 0.05** with real random data. After weeks of debugging the SF remap (8+ iterations, all producing the same 0.2 cosine against a wrong reference), we discovered:
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1. **The BF16 reference comparison was wrong** — our Python dequantization didn't match CUTLASS's internal FP4 handling. A wrong reference is worse than no reference. We chased ghosts through 8+ SF remap rewrites because the 0.2 cosine was never about the remap.
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2. **The C++ CUTLASS kernel misinterpreted FP4 data** — even with SF remap verified correct (0 byte errors), the GEMM produced garbage with non-uniform data. The issue was in how CUTLASS's C++ API handles FP4 packing/tiling internally — something we couldn't easily debug or fix.
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3. **The checkpoint `input_scale` was a red herring** — we tried using the checkpoint's calibration scale as the activation normalization scale. It saturated all block scales to 448.0 (max float8). The `input_scale` is a calibration constant for alpha computation, not a normalization scale.
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### The CuTeDSL Kernel Works
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NVIDIA's CuTeDSL approach (Python-based CUTLASS kernels compiled via MLML → PTX) is what the CUTLASS team recommends for Blackwell. Their official MoE scaled grouped GEMM example (`torch_scaled_grouped_mm.py`) supports NVFP4 out of the box. We adapted it.
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**Results with real DeepSeek-V4 layer 0 weights:**
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- L1 GEMM alone: cosine 0.995
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- Full MoE pipeline (L1→SiLU→L2→scatter): cosine 0.989
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- Weight loading: **0% loss** — direct uint8→float4_e2m1fn_x2 view-cast, bit-identical to checkpoint
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- Activation quantization: ~1.1% cosine loss (dynamic BF16→NVFP4 — inherent to the format, unavoidable)
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- GEMM kernel: 0% loss (CuTeDSL is correct)
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The 0.989 cosine is entirely from activation quantization. The weights are bit-identical to the checkpoint — no BF16 round-trip, no precision loss.
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### The Dequant→Requant Anti-Pattern
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Early versions dequantized all NVFP4 weights to BF16, then let vLLM's `FlashInferCutlassNvFp4LinearKernel` requantize them back to NVFP4 at inference time. This:
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- Wasted 5 minutes on load doing NVFP4→BF16 conversion
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- Lost precision on the double round-trip
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- Caused vLLM to hang — the NVFP4 attention kernel expects native NVFP4 weights, not BF16 weights with an NVFP4 quant_method attached
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The fix: **keep everything in NVFP4**. The checkpoint stores NVFP4. The kernels consume NVFP4. No conversion needed.
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### CUDAGraph Compatibility
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vLLM uses CUDA graphs to eliminate kernel launch overhead in the decode path. CUDA graphs record the entire forward pass once, then replay it — but they require **fixed tensor shapes, fixed memory addresses, and zero CPU-GPU syncs**.
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Our original runner was not cudagraph-safe. We had to fix several classes of issues:
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#### 1. CPU↔CUDA Tensor Copies
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`torch.tensor([0,1,...], device=x.device)` creates the tensor on **CPU first**, then copies to CUDA. This copy is forbidden during graph capture. The fix: **cache tensors per device** on first use, outside the graph.
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```python
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# BAD — CPU→CUDA copy inside graph
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step_to_idx = torch.tensor([0,1,2,3,4,4,5,5,6,6,6,7,7], device=x.device)
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# GOOD — cached on first use, reused in graph
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step_to_idx = _get_step_to_idx_lut(x.device) # returns cached CUDA tensor
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```
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Similarly, `torch.zeros` and `torch.rand` don't support `float4_e2m1fn_x2` or `float8_e4m3fn` dtypes. The fix: create as `uint8` or `float16`, then `.view()` or `.to()` the target dtype.
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#### 2. GPU Scalar Slicing
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`buf[:gpu_scalar, :]` requires the runtime to query the GPU scalar's value to determine the output shape. This triggers an implicit CPU-GPU sync, which invalidates the graph. The fix: **always use full pre-allocated buffers**. Extra rows are zeros that contribute nothing to the computation.
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```python
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# BAD — GPU scalar as slice index (implicit sync)
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total_padded_rows = padded_expert_offsets[-1] # GPU scalar
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padded_scales = buf[:total_padded_rows, :padded_cols] # sync!
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# GOOD — full pre-allocated buffer, zero out before use
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padded_scales = self._padded_scales_buf # always max size
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padded_scales.zero_()
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```
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**Design decision:** Padding to max size wastes a few rows of compute on zero data, but:
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- The extra rows are zeros → zero GEMM output → no accuracy impact
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- GEMMs are memory-bandwidth bound → multiplying zeros is nearly free
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- VRAM cost is negligible (~350KB for activation intermediates across all MoE layers)
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- vLLM already does this everywhere (attention, FFN, etc.)
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#### 3. Kernel Compilation in the Forward Path
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`cute.compile()` is a host-side JIT operation that generates PTX and compiles a CUDA kernel. It cannot be called inside cudagraph capture. The fix: **compile once during warmup, cache the compiled kernel, then only invoke `compiled()` on subsequent calls**.
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The compiled kernel uses `separate_tensormap_init=True`, which handles TMA descriptor re-initialization for new tensor data. We create new `mark_layout_dynamic` CuTe tensor views for each forward call, and the compiled kernel accepts them.
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**Critical lesson:** Caching the compiled kernel across different tensor allocations initially produced wrong results (cosine 0.5 instead of 0.99). The issue was NOT that caching is fundamentally broken — it was that our bridge had other bugs (wrong `make_b_k_major` stride check, `quantize_weight_to_nvfp4` packing N instead of K). Once those were fixed, cached compilation works correctly.
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#### 4. Weight Quantization: K is the Packed Dimension
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`quantize_weight_to_nvfp4` packs K (dim 0) differently from `quantize_to_nvfp4` which packs the last dimension. For a weight matrix `(K, N)`:
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- K=7168 is the packed dimension (7168 → 3584 in float4)
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- N=6144 stays as-is
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- Block scales are computed along K blocks: `(K//16, N)` not `(K//2, N//16)`
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- The nibble packing uses `[:, ::2, :]` and `[:, 1::2, :]` (along the K block dim)
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Confusing the two quantization functions produces wrong tensor shapes that crash or produce garbage.
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#### 5. B Tensor K-Major Layout
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The CuTeDSL kernel expects B tensors in K-major memory layout (K elements contiguous in memory). `torch.stack` produces N-major layout. The fix: **double-permute trick** — transpose, make contiguous, transpose back. Same shape, different strides.
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```python
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# Double-permute: (E,K,N) → (E,N,K) → contiguous → (E,K,N)
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# Same shape, but K-contiguous memory layout
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return b_tensor.permute(0, 2, 1).contiguous().permute(0, 2, 1)
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```
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A single permute changes the tensor SHAPE (swapping K and N), which breaks everything downstream.
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### Key Lessons
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1. **A wrong reference is worse than no reference** — the 0.2 cosine against a broken BF16 dequant sent us chasing SF remap bugs for weeks
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2. **The C++ CUTLASS API is a footgun for FP4** — CuTeDSL handles tensor layouts, tiling, and SF construction correctly by construction
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3. **Test with real data early** — uniform tests pass even with broken kernels; random data reveals real bugs
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4. **Separate the GEMM from the pipeline** — our `layertest.py` runs without vLLM, Docker, or tensor parallelism. It caught the kernel bug that vLLM's integration layers masked.
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5. **Don't dequant what's already quantized** — if the kernel expects NVFP4 and the checkpoint is NVFP4, leave it alone. No BF16 round-trips.
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6. **GPU scalar slicing is a silent cudagraph killer** — no error, no warning, just `cudaErrorStreamCaptureInvalidated` with no pointer to the cause. The test harness catches it.
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7. **Weight vs activation quantization are different** — K-packed (weights) vs last-dim-packed (activations). Mixing them up produces wrong shapes and garbage output.
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8. **Double-permute for memory layout changes** — single permute changes shape, double-permute changes layout. The kernel cares about both.
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## Project Structure
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```
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nvfp4-megamoe-kernel/
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├── cutedsl/ # CuTeDSL kernel + bridge layer
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│ ├── bridge.py # Tensor layout conversion, quantization, kernel launch
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│ ├── moe_pipeline.py # Full MoE pipeline (L1→SiLU→L2→scatter)
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│ └── kernel/moe/ # NVIDIA's ScaledGroupedGemmKernel (untouched)
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│ ├── torch_scaled_grouped_mm.py # The working kernel (3900 lines)
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│ ├── moe_utils.py
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│ moe_persistent_scheduler.py
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│ └── moe_sched_extension.py
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├── vllm/ # vLLM integration
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│ ├── nvfp4_cutedsl.py # CuTeDSLMoERunner — cudagraph-safe MoE kernel interface
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│ └── patches/
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│ ├── deepseek_v4.py # DeepSeek-V4 model patch (NVFP4 native)
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│ └── deepseek_v4_attention.py # Attention patch (NVFP4 native)
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├── tests/
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│ ├── cudagraph_test.py # CUDAGraph compatibility test (✅ PASS)
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│ ├── layertest.py # Layer 0 comparison: CuTeDSL vs BF16 (✅ cosine 0.988)
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│ ├── test_cutedsl.py # Small standalone CuTeDSL test (✅ cosine 0.991)
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│ ├── test_uniform_fp4.py # Uniform data GEMM test
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│ ├── test_b_layout.py # B matrix column layout test
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│ └── test_quick_rand.py # Quick random GEMM sanity check
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└── reference/ # Reference files for study
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```
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## The Bridge Layer (`cutedsl/bridge.py`)
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Handles all tensor layout conversion from our pipeline to what the CuTeDSL kernel expects:
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| Function | What it does |
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|----------|--------------|
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| `quantize_to_nvfp4()` | BF16 → float4_e2m1fn_x2 + float8_e4m3fn block scales (NOT cudagraph-safe — uses .max()) |
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| `quantize_activation_nvfp4()` | Same, but cudagraph-safe (fixed global_scale, no .max()) |
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| `quantize_weight_to_nvfp4()` | Same, but K is the packed dimension (different block scale shape) |
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| `assemble_scales_2d_side()` | Pad and swizzle activation scale factors (2Dx3D A side) |
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| `assemble_scales_3d_side()` | Pad and swizzle weight scale factors (2Dx3D B side) |
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| `make_b_k_major()` | Convert B tensor from N-major to K-major strides (double-permute trick) |
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| `run_nvfp4_grouped_gemm()` | Kernel launch with cached compilation (cudagraph-safe) |
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## Running Tests
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On the B200 (host venv, no container):
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```bash
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cd /root/nvfp4-megamoe-kernel
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source tests/.venv/bin/activate
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export CUDA_TOOLKIT_PATH=/usr/local/cuda
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# CUDAGraph compatibility test
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python3 tests/cudagraph_test.py
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# Small standalone test
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python3 tests/test_cutedsl.py
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# Full layer 0 comparison with real weights
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python3 tests/layertest.py
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```
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## NVFP4 Coverage
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| Component | Format | Kernel | Conversion? |
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|-----------|--------|--------|-------------|
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| MoE experts (L1+L2) | NVFP4 native | CuTeDSL ScaledGroupedGemm | No — direct uint8→float4 view-cast |
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| Shared experts | NVFP4 native | FlashInferCutlassNvFp4 | No — stays native |
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| wq_b, wo_b, fused_wqa_wkv | NVFP4 native | FlashInferCutlassNvFp4 | No — stays native |
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| wo_a | NVFP4 → FP8 | fp8_einsum | Yes — fp8_einsum requires FP8 |
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| Compressor | NVFP4 → BF16 | torch.mm | Yes — weight_loader stacking issue |
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| KV cache | FP8 | FlashInfer MLA | N/A — FP8 is optimal for KV cache |
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## Plan
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### Phase 1: Kernel ✅ DONE
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- CuTeDSL ScaledGroupedGemmKernel works with NVFP4
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- Bridge layer handles all tensor layout conversion
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- Full MoE pipeline (L1→SiLU→L2→scatter) produces cosine 0.988 vs BF16
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### Phase 2: vLLM Integration ✅ DONE
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- CuTeDSLMoERunner wires CuTeDSL kernel into vLLM
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- Weight loading: checkpoint uint8 → float4_e2m1fn_x2 view-cast (bit-preserving)
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- Block scales (float8_e4m3fn) and global scales (float32) pass through directly
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- L1 dual global scale handling: normalize to max(gate_gs, up_gs), fold ratio into block scales
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- Attention projections stay native NVFP4 (FlashInferCutlassNvFp4LinearKernel)
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- CuTeDSL kernel warmup during model load (prevents RPC timeout)
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- Removed all debug prints and env var gates from vLLM serving path
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### Phase 2.5: CUDAGraph Compatibility ✅ DONE
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- CuTeDSLMoERunner is fully cudagraph-safe
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- Zero CPU-GPU syncs, zero dynamic shapes, zero GPU scalar slicing
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- All intermediate buffers pre-allocated at max_num_tokens * top_k
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- `quantize_activation_nvfp4` uses cached LUT (no CPU→CUDA copy)
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- `torch.zeros/rand` for float4/float8 → uint8→view or float16→cast
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- Test harness validates capture + replay
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- VRAM overhead: ~350KB (negligible)
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- Compute overhead: zero rows through GEMM on padding (memory-bound, free)
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- Kernel compilation cached: `cute.compile()` once during warmup, `compiled()` on forward calls
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### Phase 3: Output Quality 🔧 IN PROGRESS
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- vLLM serves the model with cudagraph, but output is garbage tokens
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- Layer 0 cosine is 0.988 in isolation, so the GEMM math is correct
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- Investigating: weight loading path in vLLM, tensor parallelism handling, scale normalization
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- Need to compare vLLM's weight pipeline vs layertest's direct path
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### Phase 4: Optimization
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- Replace wo_a FP8 conversion with native NVFP4 GEMM (eliminate last dequant)
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- Fix compressor weight_loader so it stays NVFP4 native
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- Explore larger tile sizes for better occupancy
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- Profile end-to-end inference on full model
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- Proper TMA descriptor management for kernel caching across different tensor pools
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### Phase 5: Production
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- Clean up old C++ kernel code (tagged `the-last-of-cutlass`)
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- Add proper error handling and logging
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- Benchmark vs BF16 baseline
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