ffafd47d07
Remove debug print lines referencing deleted sP_2d
2026-05-23 09:34:09 +00:00
6a078b88d9
Remove duplicate sP_2d line causing indentation error
2026-05-23 09:33:40 +00:00
1fd3670ca4
SMEM-P: Implement rank mismatch fix by reshaping source tensor
2026-05-23 09:33:24 +00:00
fe3b1abf22
Update STAGE_D.md checklist with current progress and lessons learned
2026-05-23 09:27:48 +00:00
77b0f5824b
Add more debug prints for sP shapes
2026-05-23 09:26:30 +00:00
303df9b8c4
Add debug prints to SMEM-P path to understand rank mismatch
2026-05-23 09:25:48 +00:00
1f4fe3e404
Fix SMEM-P copy rank mismatch (use rP_bf16 directly instead of group_modes)
2026-05-23 09:21:13 +00:00
162bf51d64
D1.3: Implement SMEM-P path (write P to SMEM via tiled_smem_copy instead of zeroing sP)
2026-05-23 09:20:37 +00:00
1d1de22775
Stage D1: Multi-PV-tile support for hd>256 (tcgen05 MMA max N=256)
2026-05-23 09:04:01 +00:00
eedcfd7d21
Fix v_fmha layout to use pv_n_tile instead of head_dim for multi-PV-tile support
2026-05-23 09:02:01 +00:00
fcdfc4239c
D1.4: Add pv_n_tile and n_pv_tiles for multi-PV-tile support (tcgen05 MMA max N=256)
2026-05-23 09:00:18 +00:00
b13da6b7a0
diag: add 2-CTA check + fix LayoutEnum in MMA test
2026-05-23 08:45:26 +00:00
c34291843b
fix: remove bad import in NVFP4 diag
2026-05-23 08:44:37 +00:00
8a8e0c5ed6
fix: import ceil_div in quantize.py (was NameError at runtime)
2026-05-23 08:40:24 +00:00
538dbb0643
fix: use quantize_activation_nvfp4 in diag
2026-05-23 08:39:12 +00:00
e2f599e4af
fix: use correct API for NVFP4-0 diag (sf_vec_size + mma_tiler_mn)
2026-05-23 08:38:19 +00:00
5572b74591
fix: use Sm100BlockScaledPersistentDenseGemmKernel in diag
2026-05-23 08:30:43 +00:00
6b1330ba47
fix: use randint+view for FP4/FP8 tensors in diag
2026-05-23 08:29:16 +00:00
3733927f28
fix: NVFP4-0 diag script — import SF_VEC_SIZE from quantize.py
2026-05-23 08:28:13 +00:00
6d8f7db2dd
diag: NVFP4-0 primitive verification script
2026-05-23 08:26:56 +00:00
d9780c0a0c
docs: add NVFP4 precision roadmap to STAGE_D.md (3 honest buckets + speculative bucket)
2026-05-23 07:39:09 +00:00
74d0822214
shit carmine left dangling
2026-05-23 06:55:22 +00:00
3b167a4362
D1.2: TMEM budget verified on B200. Split-PV mandatory at hd=512 (MMA max N=256)
2026-05-23 06:43:01 +00:00
99000cba8d
D1.2: fix probe for hd=512 (MMA max N=256, use pv_n_tile)
2026-05-23 06:41:42 +00:00
60824b62db
D1.2: simplify TMEM budget probe, fix printf args
2026-05-23 06:40:55 +00:00
de439bcd75
fix: cuda.CUstream import
2026-05-23 06:40:05 +00:00
1c20b826d9
D1.2: TMEM budget probe using @cute.jit for MLIR context
2026-05-23 06:39:27 +00:00
6575e83f6d
fix: remove unused v_fmha_layout from probe
2026-05-23 06:38:08 +00:00
07bf2adf51
D1.2: TMEM budget probe with real tensor major modes
2026-05-23 06:37:34 +00:00
6e351c276d
fix: OperandMajorMode.MN not .M
2026-05-23 06:36:39 +00:00
cabe8489aa
fix: typo + OperandMajorMode for TMEM budget probe
2026-05-23 06:35:55 +00:00
61b9dbb2d6
fix: LayoutEnum import from cutlass.utils
2026-05-23 06:35:03 +00:00
4c35fa49a9
fix import path for tcgen05
2026-05-23 06:34:30 +00:00
a2d0dec7bb
D1.2: TMEM budget probe script for hd=64,128,256,512
2026-05-23 06:33:26 +00:00
578d186c20
fix: add SwiGLU clamping to fused kernel (paper §4.2.3, CG-1)
...
The fused SwiGLU kernel stored swiglu_limit but never applied it.
Paper §4.2.3: gate capped at swiglu_limit, linear clamped to [-limit, +limit].
Non-fused reference path already applies clamping correctly.
Fix: add fmin/fmax clamping in FP32 before BF16 conversion.
2026-05-23 06:32:54 +00:00
11c7e2c663
STAGE_D.md: restructure with correctness gaps, TMEM budget, execution order
2026-05-23 06:31:37 +00:00
3d69215c4e
D1.1: Fix make_fragment_A — use sP for SMEM source pv_mma
2026-05-23 06:04:44 +00:00
d0567524e1
D1.1: Fix PV A-operand construction — compile-time branch for TMEM vs SMEM
2026-05-23 06:03:27 +00:00
a3344ddd50
D1.1: Add SMEM-P path behind use_smem_p flag (stub: zero sP)
2026-05-23 06:01:02 +00:00
27041964e3
D1.0: Replace HEAD_DIM=64 with self.head_dim constructor parameter
2026-05-23 05:55:03 +00:00
e98f5e4f9e
Add STAGE_D.md: step-by-step runbook and todo list for D1-D5
2026-05-23 05:52:03 +00:00
0520d55ca6
Rename FmhaV3StageC → FmhaKernel — no dev stage artifacts in production API
2026-05-23 05:45:58 +00:00
af925abe3b
Update README: reflect Stage C migration, built indexer/router/compressor, SMEM-P path, CuTeDSL scoping lesson
2026-05-23 05:42:44 +00:00
c92976b3cd
Migrate Stage C kernel (proven cos 0.97) into module - exact copy, no modifications
2026-05-23 05:36:22 +00:00
e397386ba2
Fix TMEM-P offset calc: match Stage C with p_cols_fp32 from pv_mma_tiler[2]
2026-05-23 05:18:37 +00:00
a284580422
Add missing TMEM fence after P store in TMEM-P path
2026-05-23 05:17:45 +00:00
0cd0e8b35f
Fix p_cols_fp32: use pv_mma_tiler[2] (K-dim) not [1] (N-dim)
2026-05-23 05:16:19 +00:00
721bac4958
Fix PV A-operand major mode: K for TMEM-P, a_major for SMEM-P
2026-05-23 05:14:08 +00:00
a0363e8911
Fix CuTeDSL scoping: hoist P store vars out of if block
2026-05-23 05:12:30 +00:00
86bf5771c1
Fix O rescale: use Stage C proven correction_rescale pattern
2026-05-23 05:10:46 +00:00
