0286d57631
D1.3: Re-enable coordinate-indexed SMEM-P write with identity tensor coords
2026-05-23 23:26:46 +00:00
3118bec420
D1.3: Revert to zero-fill for sP - need to verify sP→PV pipeline first
2026-05-23 23:26:07 +00:00
0963d949c4
D1.3: Compute (m,k) directly from thread mapping instead of identity tensor
2026-05-23 23:24:54 +00:00
fca9652719
D1.3: Add debug prints for SMEM-P coordinate mapping
2026-05-23 23:24:02 +00:00
de869c01c8
D1.3: Add SMEM-P coordinate diagnostic test
2026-05-23 23:23:05 +00:00
89393b8352
D1.3: Fix coord extraction - identity tensor stores (m,k) pairs as values
2026-05-23 23:21:15 +00:00
f74fd75054
D1.3: Fix coordinate indexing - tTMEM_LOADcS first mode is (32,1) nested tuple
2026-05-23 23:20:12 +00:00
4b8970d83c
D1.3: Direct coordinate-indexed SMEM-P write using tTMEM_LOADcS coords
...
Each softmax thread writes its P values to sP using the (m,k) coordinates
from tTMEM_LOADcS. The k coordinate is decomposed into (k0,k1,k2) to
match sP's ((128,16),1,(4,2)) layout. CuTeDSL tensor indexing handles
the swizzle automatically. No make_tiled_copy needed.
2026-05-23 23:19:21 +00:00
58b4537741
D1.3: Use make_cotiled_copy for SMEM-P — custom TV layout from TMEM-load coords to sP
...
Per CUTLASS guidance:
- make_tiled_copy_C/D encode wrong invariants for this transfer
- Build custom R→S copy where TV map comes from tTMEM_LOADcS (softmax thread
ownership) and destination addresses come from sP layout (PV A-operand swizzled SMEM)
- Use composition(sP_2d_layout, p_coord_layout) for atom_layout_tv
- Start with scalar BF16 (16-bit) stores — vectorize later
- Zero-fill source for compile test, will fill with actual P values next
2026-05-23 23:17:30 +00:00
48c1e6d7e9
D1.3: Use const_expr for lse None check
2026-05-23 22:30:55 +00:00
82179f1f61
D1.3: Fix LSE with const_expr, always create valid mLSE tensor
2026-05-23 22:30:14 +00:00
f1341ad76e
D1.3: Try make_tiled_copy_C(qk_mma) for SMEM-P copy - zero-fill source for compile test
2026-05-23 22:29:10 +00:00
bafcfa658f
D1.3: Define SMEM-P copy atoms unconditionally (CuTeDSL scoping)
2026-05-23 22:28:12 +00:00
8d226a6243
D1.3: Use full sP (4D) for make_tiled_copy_D partition
2026-05-23 22:27:11 +00:00
fa2e513168
D1.3: SMEM-P via get_smem_store_op + make_tiled_copy_D
...
Uses the CUTLASS blackwell_helpers pattern:
- get_smem_store_op creates a SMEM store atom paired with the TMEM load
- make_tiled_copy_D uses the same thread partition as the TMEM load
- Softmax warps write P to sP using the same thread mapping they use for reading S
- MMA warp reads P from sP via pv_mma.make_fragment_A(sP)
- Replaces the zero-fill stub with a proper register→SMEM copy
2026-05-23 22:26:09 +00:00
b77ad244a2
D5b: Use normalized O + LSE for merge (correct formula), always output LSE
2026-05-23 21:35:40 +00:00
aff208fb4c
D5a: Fix LSE formula - lse = ln(row_sum) + row_max * ln(2)
...
row_max is in scale_log2 domain, need to convert to natural log domain.
attn_max = row_max * ln(2), so lse = ln(row_sum) + row_max * ln(2).
2026-05-23 21:15:14 +00:00
a5061a24b9
D5a: Use tensor indexing for LSE write
2026-05-23 21:13:52 +00:00
7a87c634fb
D5a: Use cute.store for LSE write
2026-05-23 21:13:07 +00:00
7c38bd5522
D5a: Fix LSE - compute row_max_safe from final row_max, remove mLSE None check
2026-05-23 21:12:29 +00:00
aecf6671d9
D5a: Fix - add normalize param to __init__
2026-05-23 21:11:37 +00:00
b273d4a7e8
D5a: Add normalize flag + LSE output
...
- normalize=True (default): O = softmax(P) @ V (existing behavior)
- normalize=False: O = P @ V (un-normalized) + lse = log(row_sum) + row_max
- LSE tensor passed as optional parameter
- Test includes D5a normalize=False verification with LSE comparison
- Cleaned up SMEM-P debug prints and broken make_tiled_copy_C code
- hd=64 TMEM-P regression: cos 0.973 PASS
2026-05-23 21:10:40 +00:00
aa72779a7a
D1.3: Use const_expr if for tOrP0 compile-time selection
2026-05-23 21:07:58 +00:00
61cb8f002d
D1.3: Pre-compute tOrP0_offset in _setup, use const_expr for compile-time selection
2026-05-23 21:07:10 +00:00
77035f8a54
D1.3: Use const_expr for tOrP0 offset (compile-time conditional)
2026-05-23 21:06:16 +00:00
2e0db67c80
D1.3: Use MLIR-compatible expression for tOrP0 offset (same as Stage C)
2026-05-23 21:05:12 +00:00
399a241e84
D1.3: Initialize tOrP0 before conditional for CuTeDSL scoping
2026-05-23 21:03:53 +00:00
17109a8f04
D1.3: Fix tOrP0 for SMEM-P - skip make_tensor when offset is 0
...
CuTeDSL doesn't support OpResult + int. When offset is 0 (SMEM-P),
just use tOrP directly.
2026-05-23 21:03:00 +00:00
0727725634
D1.3: Fix tOrP0 offset - scale FP32 columns to BF16 elements
...
tmem_p0_offset is in FP32 columns, but tOrP uses BF16 elements.
Offset = p0_offset * (32/16) = p0_offset * 2.
2026-05-23 21:02:04 +00:00
c83b7de258
D1.3: Fix CuTeDSL scoping - define tOrP0 unconditionally with p0 offset
2026-05-23 21:01:18 +00:00
cba41d500c
D1.3: Fix critical bug - add TMEM column offset for P0 in PV GEMM
...
The softmax warps store P at tmem_p0_offset=32. PV MMA must read from
the same offset. tOrP0 was missing the offset, causing PV to read from
TMEM column 0 (where S is) instead of column 32 (where P is).
This was the root cause of NaN/zeros in D1 tests.
2026-05-23 21:00:29 +00:00
ed71f25903
D1.3: Revert to d1.3-pre-sm100-helpers baseline for testing
2026-05-23 20:58:06 +00:00
79a17303c4
D1.3: DIAGNOSTIC - test epilogue_tma_store raw PV without any round-trips
2026-05-23 20:57:13 +00:00
b926a0e806
D1.3: Remove NO-OP round-trip, keep normalize + epilogue_tma_store
2026-05-23 20:56:13 +00:00
820d6921d9
D1.3: Full correction_epilog with TMA store, normalize in reg before SMEM write
...
One-way trip: TMEM->reg (normalize) ->SMEM->GMEM
Replicates epilogue_tma_store logic with normalize step added
Uses CUTLASS helpers for correct layout handling
2026-05-23 20:54:23 +00:00
1c74d02adb
D1.3: Apply transform_partitioned_tensor_layout before epilogue helpers
2026-05-23 20:52:42 +00:00
1cf7140ea3
D1.3: Replace NO-op TMEM round-trip with correction_epilog using epilogue_tmem_copy_and_partition + epilogue_smem_copy_and_partition
...
- Remove hand-constructed TMEM round-trips (3% layout mismatch error)
- Use CUTLASS get_tmem_load_op + get_smem_store_op paired atoms
- One-way trip: TMEM -> reg (normalize) -> SMEM -> GMEM
- SMEM-P path: zero-fill stub (proper copy TBD)
- Keep per-tile O rescale atoms for n>128 support
2026-05-23 20:50:23 +00:00
1e55e36919
SMEM-P: test permutation 4 (swap m↔n2)
2026-05-23 20:20:07 +00:00
c0e2fe43f1
SMEM-P: add iterator offset debug print
2026-05-23 20:19:22 +00:00
42880fa397
SMEM-P: add tCrP debug print, reset permute to 0
2026-05-23 20:14:32 +00:00
1f46a62f65
SMEM-P: test permutation 1 (swap m↔n0)
2026-05-23 20:14:21 +00:00
474363ce59
SMEM-P: add debug_permute flag for coordinate permutation testing
2026-05-23 20:13:44 +00:00
cf9050c333
SMEM-P: disable debug flags, revert to original mapping
2026-05-23 20:12:26 +00:00
c7f613644f
SMEM-P: fix scoping error, disable debug_p_one, enable debug_swap_mn
2026-05-23 20:11:50 +00:00
14524295c7
SMEM-P: add debug_swap_mn flag to test swapped coordinate mapping
2026-05-23 20:10:39 +00:00
aafbe16a81
SMEM-P: add debug_p_one flag to write constant P=1.0
2026-05-23 20:09:47 +00:00
75b3d0f4b4
auto: pre-test commit
2026-05-23 20:08:31 +00:00
b551287123
SMEM-P: implement two-phase softmax with normalization before SMEM write
2026-05-23 20:08:29 +00:00
c88ec626e0
Revert TMEM layout change (caused error)
2026-05-23 20:07:02 +00:00
bb7f53702f
SMEM-P: try using PV A-operand layout directly for TMEM-P
2026-05-23 20:06:23 +00:00
