biondizzle cba41d500c D1.3: Fix critical bug - add TMEM column offset for P0 in PV GEMM ...

The softmax warps store P at tmem_p0_offset=32. PV MMA must read from
the same offset. tOrP0 was missing the offset, causing PV to read from
TMEM column 0 (where S is) instead of column 32 (where P is).
This was the root cause of NaN/zeros in D1 tests.

2026-05-23 21:00:29 +00:00

..

attention

D1.3: Fix critical bug - add TMEM column offset for P0 in PV GEMM

2026-05-23 21:00:29 +00:00

cache

KV Cache: schema, allocator, pools, manager, append_swa kernel

2026-05-22 00:08:38 +00:00

compressor

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

cuda

Fix indexer score kernel: use static shared memory, correct FP4 head offsets

2026-05-22 01:45:05 +00:00

decode

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00

gemm

fix: add SwiGLU clamping to fused kernel (paper §4.2.3, CG-1)

2026-05-23 06:32:54 +00:00

indexer

Indexer: score+topk kernel, gather KV, compute_valid_lens

2026-05-22 01:20:39 +00:00

router

Router: Blackwell-native fused decode kernel — real CuTeDSL implementation

2026-05-21 22:04:20 +00:00

__init__.py

Restructure: cutedsl/ -> dsv4/ with proper layering

2026-05-21 17:30:44 +00:00