8010e3dda2
test: add try/except for SMEM-P coord test
2026-05-24 02:15:07 +00:00
16bade9e10
test: use FmhaKernel for SMEM-P coord test
2026-05-24 01:59:25 +00:00
f2d95da4aa
test: SMEM-P coordinate verification test
2026-05-24 01:58:32 +00:00
394f08601a
fix: proper v_major from tensor
2026-05-24 01:55:37 +00:00
384de55dfd
fix: COL_MAJOR
2026-05-24 01:54:30 +00:00
313f2c77cd
fix: hardcode v_major for diag test
2026-05-24 01:54:20 +00:00
268265ba0b
diag: use FmhaKernel setup for cotiled test
2026-05-24 01:54:08 +00:00
32d8483443
fix: v_major derivation in cotiled diag
2026-05-24 01:53:40 +00:00
ce1e2177ec
diag: simplified cotiled layout test
2026-05-24 01:53:24 +00:00
f6e3bddb10
fix: LayoutEnum import in cotiled diag test
2026-05-24 01:52:58 +00:00
67a2c3ee72
diag: layout composition test for make_cotiled_copy SMEM-P
2026-05-24 01:48:50 +00:00
699c646497
D1.5: Fix bSG_gC slicing - group trailing modes (CUTLASS pattern)
2026-05-24 01:41:52 +00:00
f2ab5790e8
D1.5: Dynamic slicing for tTR_gC (variable rest dims)
2026-05-24 01:40:44 +00:00
d28257185f
D1.5: Fix flat_divide slice coordinates (4 modes, no STAGE dim)
2026-05-24 01:39:21 +00:00
86971dda81
D1.5: Rewrite correction epilogue using CUTLASS pattern (transform_partitioned, flat_divide, paired atoms)
2026-05-24 01:37:53 +00:00
ec250eccd6
D1.5: Fix TMA store - group_modes on bSG_gC, use flat indexing
2026-05-24 01:36:01 +00:00
61c4e107da
D1.5: Fix TMA store - use flat_divide on tCgC instead of local_tile on mC
2026-05-24 01:35:10 +00:00
6de0d316ef
D1.5: Fix TMA store - use 3D tile for local_tile on 3D mC
2026-05-24 01:20:33 +00:00
f59fd07ba7
D1.5: Use group_modes on sC for 2D TMA view (preserves swizzle)
2026-05-24 00:52:57 +00:00
577066bb7f
D1.5: Use 2D sC_epi layout from c_smem_s for TMA partition
2026-05-24 00:51:18 +00:00
534327f31b
D1.5: Fix TMA store - use group_modes on sC and tCgC
2026-05-24 00:48:18 +00:00
8048aa4be6
D1.5: Simplify TMA store - use 2D sC_epi and gC_epi views
2026-05-24 00:46:52 +00:00
88a5f55120
D1.5: Fix TMA store - use existing gC partition
2026-05-24 00:43:35 +00:00
b9e91853fb
D1.5: Implement correction epilog with paired atoms (get_tmem_load_op + get_smem_store_op)
...
One-way: TMEM → registers (normalize) → SMEM → GMEM
Based on CUTLASS FMHA reference's correction_epilog pattern.
Eliminates TMEM round-trip error for O normalization.
O rescale (kt>0) still uses old atoms (separate fix).
2026-05-24 00:41:27 +00:00
e632490682
D1.5: Add TODO for correction epilog - keeping working TMEM round-trip for now
2026-05-24 00:37:36 +00:00
9f88db897f
D1.5: Revert to pre-epilog backup - correction epilog refactor is complex, will do incrementally
...
The correction epilog (TMEM→reg→SMEM→GMEM one-way trip) is the right approach
but the TMA store from SMEM requires proper partitioning that needs more work.
Reverting to the known-working state (with 3% TMEM round-trip error) to focus
on the SMEM-P write first.
2026-05-24 00:35:00 +00:00
501ba7b2a5
D1.5: Fix TMA store - use local_tile with pv_mma_tiler
2026-05-24 00:32:35 +00:00
d028088dd0
D1.5: Fix TMA store rank mismatch - use 2D sC_epi view
2026-05-24 00:31:45 +00:00
ea5662ab2b
D1.5: Implement correction epilog with get_tmem_load_op + get_smem_store_op paired atoms
...
- One-way: TMEM → registers (normalize) → SMEM → GMEM
- Eliminates TMEM round-trip error for O normalization
- O rescale (kt>0) still uses old atoms (fix later)
- Based on CUTLASS FMHA reference's correction_epilog pattern
2026-05-24 00:30:38 +00:00
90131da010
D1.5: Replace TMEM round-trip normalize with correction epilog (one-way: TMEM→reg→SMEM→GMEM)
...
- Remove noop + normalize TMEM round-trips (3% error per trip)
- Use epilogue_tmem_copy_and_partition for TMEM→reg (paired atoms)
- Use epilogue_smem_copy_and_partition for reg→SMEM (paired atoms)
- Apply 1/row_sum normalization in register space (exact)
- TMA store from SMEM→GMEM (no TMEM write-back)
- Add iter_acc_early_release_in_epilogue attribute
- Update SMEM-P comments to reflect coordinate-indexed fallback
2026-05-24 00:24:24 +00:00
e23119ce7e
D1.3: Fix LSE tensor layout for weakly congruent store
2026-05-24 00:16:22 +00:00
d4aeb4e41c
D1.3: Add unnormalized debug test to isolate SMEM-P vs O round-trip error
2026-05-24 00:15:41 +00:00
b2a583a2a8
D1.3: Add SMEM-P write/read diagnostic
2026-05-24 00:13:28 +00:00
0fc6530f3f
D1.3: Add SMEM-P vs TMEM-P comparison test
2026-05-24 00:10:18 +00:00
d56e5601bb
D1.3: Fix while loop in cotiled diag - precompute num_tmem_alloc_cols
2026-05-24 00:07:22 +00:00
7bd857e5d3
D1.3: Fix cotiled diagnostic - use proper MMA construction
2026-05-24 00:06:50 +00:00
3fe17495ee
D1.3: Add make_cotiled_copy diagnostic test
2026-05-24 00:05:48 +00:00
ed539653d0
shit left dangling
2026-05-23 23:58:57 +00:00
0286d57631
D1.3: Re-enable coordinate-indexed SMEM-P write with identity tensor coords
2026-05-23 23:26:46 +00:00
3118bec420
D1.3: Revert to zero-fill for sP - need to verify sP→PV pipeline first
2026-05-23 23:26:07 +00:00
0963d949c4
D1.3: Compute (m,k) directly from thread mapping instead of identity tensor
2026-05-23 23:24:54 +00:00
fca9652719
D1.3: Add debug prints for SMEM-P coordinate mapping
2026-05-23 23:24:02 +00:00
de869c01c8
D1.3: Add SMEM-P coordinate diagnostic test
2026-05-23 23:23:05 +00:00
89393b8352
D1.3: Fix coord extraction - identity tensor stores (m,k) pairs as values
2026-05-23 23:21:15 +00:00
f74fd75054
D1.3: Fix coordinate indexing - tTMEM_LOADcS first mode is (32,1) nested tuple
2026-05-23 23:20:12 +00:00
4b8970d83c
D1.3: Direct coordinate-indexed SMEM-P write using tTMEM_LOADcS coords
...
Each softmax thread writes its P values to sP using the (m,k) coordinates
from tTMEM_LOADcS. The k coordinate is decomposed into (k0,k1,k2) to
match sP's ((128,16),1,(4,2)) layout. CuTeDSL tensor indexing handles
the swizzle automatically. No make_tiled_copy needed.
2026-05-23 23:19:21 +00:00
58b4537741
D1.3: Use make_cotiled_copy for SMEM-P — custom TV layout from TMEM-load coords to sP
...
Per CUTLASS guidance:
- make_tiled_copy_C/D encode wrong invariants for this transfer
- Build custom R→S copy where TV map comes from tTMEM_LOADcS (softmax thread
ownership) and destination addresses come from sP layout (PV A-operand swizzled SMEM)
- Use composition(sP_2d_layout, p_coord_layout) for atom_layout_tv
- Start with scalar BF16 (16-bit) stores — vectorize later
- Zero-fill source for compile test, will fill with actual P values next
2026-05-23 23:17:30 +00:00
63f662edb3
Add SMEM-P guidance request document for CUTLASS LLM consultation
2026-05-23 23:03:35 +00:00
48c1e6d7e9
D1.3: Use const_expr for lse None check
2026-05-23 22:30:55 +00:00
82179f1f61
D1.3: Fix LSE with const_expr, always create valid mLSE tensor
2026-05-23 22:30:14 +00:00
