6d8f7db2dd
diag: NVFP4-0 primitive verification script
2026-05-23 08:26:56 +00:00
d9780c0a0c
docs: add NVFP4 precision roadmap to STAGE_D.md (3 honest buckets + speculative bucket)
2026-05-23 07:39:09 +00:00
74d0822214
shit carmine left dangling
2026-05-23 06:55:22 +00:00
3b167a4362
D1.2: TMEM budget verified on B200. Split-PV mandatory at hd=512 (MMA max N=256)
2026-05-23 06:43:01 +00:00
99000cba8d
D1.2: fix probe for hd=512 (MMA max N=256, use pv_n_tile)
2026-05-23 06:41:42 +00:00
60824b62db
D1.2: simplify TMEM budget probe, fix printf args
2026-05-23 06:40:55 +00:00
de439bcd75
fix: cuda.CUstream import
2026-05-23 06:40:05 +00:00
1c20b826d9
D1.2: TMEM budget probe using @cute.jit for MLIR context
2026-05-23 06:39:27 +00:00
6575e83f6d
fix: remove unused v_fmha_layout from probe
2026-05-23 06:38:08 +00:00
07bf2adf51
D1.2: TMEM budget probe with real tensor major modes
2026-05-23 06:37:34 +00:00
6e351c276d
fix: OperandMajorMode.MN not .M
2026-05-23 06:36:39 +00:00
cabe8489aa
fix: typo + OperandMajorMode for TMEM budget probe
2026-05-23 06:35:55 +00:00
61b9dbb2d6
fix: LayoutEnum import from cutlass.utils
2026-05-23 06:35:03 +00:00
4c35fa49a9
fix import path for tcgen05
2026-05-23 06:34:30 +00:00
a2d0dec7bb
D1.2: TMEM budget probe script for hd=64,128,256,512
2026-05-23 06:33:26 +00:00
578d186c20
fix: add SwiGLU clamping to fused kernel (paper §4.2.3, CG-1)
...
The fused SwiGLU kernel stored swiglu_limit but never applied it.
Paper §4.2.3: gate capped at swiglu_limit, linear clamped to [-limit, +limit].
Non-fused reference path already applies clamping correctly.
Fix: add fmin/fmax clamping in FP32 before BF16 conversion.
2026-05-23 06:32:54 +00:00
11c7e2c663
STAGE_D.md: restructure with correctness gaps, TMEM budget, execution order
2026-05-23 06:31:37 +00:00
3d69215c4e
D1.1: Fix make_fragment_A — use sP for SMEM source pv_mma
2026-05-23 06:04:44 +00:00
d0567524e1
D1.1: Fix PV A-operand construction — compile-time branch for TMEM vs SMEM
2026-05-23 06:03:27 +00:00
a3344ddd50
D1.1: Add SMEM-P path behind use_smem_p flag (stub: zero sP)
2026-05-23 06:01:02 +00:00
27041964e3
D1.0: Replace HEAD_DIM=64 with self.head_dim constructor parameter
2026-05-23 05:55:03 +00:00
e98f5e4f9e
Add STAGE_D.md: step-by-step runbook and todo list for D1-D5
2026-05-23 05:52:03 +00:00
0520d55ca6
Rename FmhaV3StageC → FmhaKernel — no dev stage artifacts in production API
2026-05-23 05:45:58 +00:00
af925abe3b
Update README: reflect Stage C migration, built indexer/router/compressor, SMEM-P path, CuTeDSL scoping lesson
2026-05-23 05:42:44 +00:00
c92976b3cd
Migrate Stage C kernel (proven cos 0.97) into module - exact copy, no modifications
2026-05-23 05:36:22 +00:00
e397386ba2
Fix TMEM-P offset calc: match Stage C with p_cols_fp32 from pv_mma_tiler[2]
2026-05-23 05:18:37 +00:00
a284580422
Add missing TMEM fence after P store in TMEM-P path
2026-05-23 05:17:45 +00:00
0cd0e8b35f
Fix p_cols_fp32: use pv_mma_tiler[2] (K-dim) not [1] (N-dim)
2026-05-23 05:16:19 +00:00
721bac4958
Fix PV A-operand major mode: K for TMEM-P, a_major for SMEM-P
2026-05-23 05:14:08 +00:00
a0363e8911
Fix CuTeDSL scoping: hoist P store vars out of if block
2026-05-23 05:12:30 +00:00
86bf5771c1
Fix O rescale: use Stage C proven correction_rescale pattern
2026-05-23 05:10:46 +00:00
e204aa7a4c
Fix tOrP0 indexing: 3-dim slice (None,None,kb) not 4-dim
2026-05-23 05:09:19 +00:00
dda5afee87
Fix CuTeDSL scoping: unconditionally define tOrP0 and tCrP
2026-05-23 05:08:10 +00:00
0f715bfaff
Fix CuTeDSL variable scoping: define tOrP0 and tCrP in both branches
2026-05-23 05:07:30 +00:00
70db626550
Fix p_tmem_s: use ComposedLayout from make_smem_layout_a, pass as kernel arg
2026-05-23 05:06:45 +00:00
09cac38a67
Consolidate FMHA stages A/B/C into unified kernel module with SMEM-P stub
2026-05-23 05:04:43 +00:00
6f834ae8b5
WIP: make_tiled_copy_C for P→SMEM
2026-05-23 03:56:56 +00:00
8114a225d1
fix: cpasync.CopyOp for reg→SMEM
2026-05-23 03:54:49 +00:00
0dbdc4f865
fix: CopyAtomUniversalOp
2026-05-23 03:52:47 +00:00
05173c1992
WIP: tiled copy for P→SMEM (zero fill)
2026-05-23 03:51:58 +00:00
5a9c299f64
fix: cute.copy(dst, src) order
2026-05-23 03:51:00 +00:00
398f5cf631
fix: BFloat16 not Float32 for bf16 reg
2026-05-23 03:50:09 +00:00
9bc7fc9361
WIP: P→SMEM write stub (zero fill, proper mapping TODO)
2026-05-23 03:49:05 +00:00
ed35a8a4ba
fix: partition_A not partition_S
2026-05-23 03:47:53 +00:00
48432522b8
fix: make_smem_layout_epi not make_epilogue_smem_layout
2026-05-23 03:47:09 +00:00
07f319d1f3
WIP: SMEM P path for PV (compiles but P write not implemented)
2026-05-23 03:46:01 +00:00
1be005296c
debug: hd=64 with CUDA_LAUNCH_BLOCKING
2026-05-23 03:42:53 +00:00
482928f142
D1: P store as BF16 using PV A-fragment layout (tOrP0)
...
Reverted tP to p_tmem_s.outer (needed for make_fragment_A profile).
P store now writes BF16 to TMEM using tOrP0's layout, matching PV A-fragment reads.
This fixes the layout mismatch at hd>64 where QK C-fragment composition
writes to different TMEM columns than PV A-fragment reads.
2026-05-23 03:42:07 +00:00
f266c3dae2
D1: align P store and PV A-fragment layouts via tP
...
Key insight: tP (PV A-fragment base) used p_tmem_s.outer layout,
but P store used QK C-fragment composition layout. These diverge at hd>64.
Fix: tP now uses the same QK C-fragment composition layout (tStP_layout)
as the P store. PV A-fragment is derived from tP, so it automatically
uses the same layout. No double-offset since tP includes P offset.
2026-05-23 03:40:10 +00:00
059c2e6cd9
D1: P store as BF16 using PV A-fragment layout
...
- Changed P store from FP32 QK C-fragment layout to BF16 PV A-fragment layout
- rP_bf16_reg stores directly to TMEM using tOrP0 layout
- Ensures softmax writes P to same TMEM columns that PV GEMM reads
2026-05-23 03:38:24 +00:00
