6ca294ed6d
D5a: Use tensor indexing for LSE write
2026-05-23 21:13:52 +00:00
7e91d76669
D5a: Use cute.store for LSE write
2026-05-23 21:13:07 +00:00
751abd9b18
D5a: Fix LSE - compute row_max_safe from final row_max, remove mLSE None check
2026-05-23 21:12:29 +00:00
d6ea7f3ebd
D5a: Fix - add normalize param to __init__
2026-05-23 21:11:37 +00:00
c80f223d08
D5a: Add normalize flag + LSE output
...
- normalize=True (default): O = softmax(P) @ V (existing behavior)
- normalize=False: O = P @ V (un-normalized) + lse = log(row_sum) + row_max
- LSE tensor passed as optional parameter
- Test includes D5a normalize=False verification with LSE comparison
- Cleaned up SMEM-P debug prints and broken make_tiled_copy_C code
- hd=64 TMEM-P regression: cos 0.973 PASS
2026-05-23 21:10:40 +00:00
542bc7b1b0
D1.3: Use const_expr if for tOrP0 compile-time selection
2026-05-23 21:07:58 +00:00
37edd783ce
D1.3: Pre-compute tOrP0_offset in _setup, use const_expr for compile-time selection
2026-05-23 21:07:10 +00:00
972fbd48b9
D1.3: Use const_expr for tOrP0 offset (compile-time conditional)
2026-05-23 21:06:16 +00:00
a762820352
D1.3: Use MLIR-compatible expression for tOrP0 offset (same as Stage C)
2026-05-23 21:05:12 +00:00
4fa4239f95
D1.3: Initialize tOrP0 before conditional for CuTeDSL scoping
2026-05-23 21:03:53 +00:00
2bb3eb95ed
D1.3: Fix tOrP0 for SMEM-P - skip make_tensor when offset is 0
...
CuTeDSL doesn't support OpResult + int. When offset is 0 (SMEM-P),
just use tOrP directly.
2026-05-23 21:03:00 +00:00
eabea91b64
D1.3: Fix tOrP0 offset - scale FP32 columns to BF16 elements
...
tmem_p0_offset is in FP32 columns, but tOrP uses BF16 elements.
Offset = p0_offset * (32/16) = p0_offset * 2.
2026-05-23 21:02:04 +00:00
47eade4afc
D1.3: Fix CuTeDSL scoping - define tOrP0 unconditionally with p0 offset
2026-05-23 21:01:18 +00:00
0e81fc18aa
D1.3: Fix critical bug - add TMEM column offset for P0 in PV GEMM
...
The softmax warps store P at tmem_p0_offset=32. PV MMA must read from
the same offset. tOrP0 was missing the offset, causing PV to read from
TMEM column 0 (where S is) instead of column 32 (where P is).
This was the root cause of NaN/zeros in D1 tests.
2026-05-23 21:00:29 +00:00
29f4480e26
D1.3: Revert to d1.3-pre-sm100-helpers baseline for testing
2026-05-23 20:58:06 +00:00
adb4398505
D1.3: DIAGNOSTIC - test epilogue_tma_store raw PV without any round-trips
2026-05-23 20:57:13 +00:00
0e41816636
D1.3: Remove NO-OP round-trip, keep normalize + epilogue_tma_store
2026-05-23 20:56:13 +00:00
8bc8b21470
D1.3: Full correction_epilog with TMA store, normalize in reg before SMEM write
...
One-way trip: TMEM->reg (normalize) ->SMEM->GMEM
Replicates epilogue_tma_store logic with normalize step added
Uses CUTLASS helpers for correct layout handling
2026-05-23 20:54:23 +00:00
d769e01a16
D1.3: Apply transform_partitioned_tensor_layout before epilogue helpers
2026-05-23 20:52:42 +00:00
cc18fddc7e
D1.3: Replace NO-op TMEM round-trip with correction_epilog using epilogue_tmem_copy_and_partition + epilogue_smem_copy_and_partition
...
- Remove hand-constructed TMEM round-trips (3% layout mismatch error)
- Use CUTLASS get_tmem_load_op + get_smem_store_op paired atoms
- One-way trip: TMEM -> reg (normalize) -> SMEM -> GMEM
- SMEM-P path: zero-fill stub (proper copy TBD)
- Keep per-tile O rescale atoms for n>128 support
2026-05-23 20:50:23 +00:00
993ec32567
SMEM-P: test permutation 4 (swap m↔n2)
2026-05-23 20:20:07 +00:00
c7a299d7d9
SMEM-P: add iterator offset debug print
2026-05-23 20:19:22 +00:00
4943af749d
SMEM-P: add tCrP debug print, reset permute to 0
2026-05-23 20:14:32 +00:00
5a11f7c09a
SMEM-P: test permutation 1 (swap m↔n0)
2026-05-23 20:14:21 +00:00
d5081fe6f0
auto: pre-test commit
2026-05-23 20:13:47 +00:00
fd54d657b2
SMEM-P: add debug_permute flag for coordinate permutation testing
2026-05-23 20:13:44 +00:00
06409401ca
SMEM-P: disable debug flags, revert to original mapping
2026-05-23 20:12:26 +00:00
b8f0f0890a
SMEM-P: fix scoping error, disable debug_p_one, enable debug_swap_mn
2026-05-23 20:11:50 +00:00
8787f6a989
SMEM-P: add debug_swap_mn flag to test swapped coordinate mapping
2026-05-23 20:10:39 +00:00
a272ce10e3
SMEM-P: add debug_p_one flag to write constant P=1.0
2026-05-23 20:09:47 +00:00
440e49b39d
auto: pre-test commit
2026-05-23 20:08:31 +00:00
3df9cb57f8
SMEM-P: implement two-phase softmax with normalization before SMEM write
2026-05-23 20:08:29 +00:00
dc93168f57
Revert TMEM layout change (caused error)
2026-05-23 20:07:02 +00:00
8d48d6d543
SMEM-P: try using PV A-operand layout directly for TMEM-P
2026-05-23 20:06:23 +00:00
6a2f3d2e27
SMEM-P: debug compute offset for known coordinate
2026-05-23 20:05:02 +00:00
db9d9b09d2
SMEM-P: add crd2idx debug attempt
2026-05-23 20:04:28 +00:00
8879f0b701
SMEM-P: test pattern based on fragment indices (k,j)
2026-05-23 20:03:22 +00:00
420bb62330
auto: pre-test commit
2026-05-23 20:02:35 +00:00
caf722f78f
SMEM-P: add shape debug prints
2026-05-23 20:02:32 +00:00
2f71868fdd
SMEM-P: add debug prints for coordinates
2026-05-23 20:00:33 +00:00
a166a19ae5
SMEM-P: implement CUTLASS LLM fixes - dynamic frg_tile, local coordinate conversion
2026-05-23 19:59:52 +00:00
afc7fbefc3
auto: pre-test commit
2026-05-23 19:53:45 +00:00
72226cef44
SMEM-P: try transposed mapping (swap m/n)
2026-05-23 19:53:42 +00:00
e4a225a138
SMEM-P: current state - working but mapping wrong (cos 0.02)
2026-05-23 19:53:25 +00:00
00d08eec28
SMEM-P: debug with linear index pattern m*128+n
2026-05-23 19:52:46 +00:00
111b50b62a
SMEM-P: debug with test pattern (k+j)*0.01
2026-05-23 19:52:02 +00:00
ca1fb7a1ca
SMEM-P: fix coordinate access - qk_coord is (m,n) not ((m,n),0,0)
2026-05-23 19:38:11 +00:00
096a48b5cb
SMEM-P: fix scoping - define tTMEM_LOADcS_frg unconditionally
2026-05-23 19:37:34 +00:00
e0aa7ccd19
auto: pre-test commit
2026-05-23 19:36:58 +00:00
4f8559ae2e
SMEM-P: implement full 128-value write in softmax loop using coordinate mapping
2026-05-23 19:36:56 +00:00
