Commit Graph

391 Commits

Author SHA1 Message Date
677245fc5c fix: LayoutEnum import from cutlass.utils 2026-05-23 06:35:03 +00:00
bd968db5d4 fix import path for tcgen05 2026-05-23 06:34:30 +00:00
afec55ad72 D1.2: TMEM budget probe script for hd=64,128,256,512 2026-05-23 06:33:26 +00:00
4c3239b9c0 debug: hd=64 with CUDA_LAUNCH_BLOCKING 2026-05-23 03:42:53 +00:00
4df5dafcc9 D1: test raw unnormalized output via epilogue_tma_store 2026-05-23 03:33:59 +00:00
6dfc06cdef test: paired atoms epilog from old commit 6ee28d8 2026-05-23 03:32:53 +00:00
e1fc4cee60 D1: paired atoms epilogue (no TMEM round-trip)
Replace NO-OP round-trip + normalize + epilogue_tma_store with:
- get_tmem_load_op + get_smem_store_op paired atoms
- One-way TMEM→reg (normalize) →SMEM→GMEM
- Eliminates ~3% error from TMEM layout mismatch
- O rescale disabled (single KV tile only for now)
- Pre-computed TMA partitions outside if blocks
2026-05-23 03:29:51 +00:00
32481f8a2b d1: sweep hd=64,128,256 2026-05-23 03:26:10 +00:00
3ec7f36e62 fix: use mV.iterator 2026-05-23 03:25:29 +00:00
73f359b565 fix: use mQ not q for LayoutEnum 2026-05-23 03:24:58 +00:00
4203d6ad20 d1: add diagnostic script 2026-05-23 03:24:16 +00:00
b249b8f135 D1: N-tile support for HEAD_DIM>256
- pv_n_tile = min(head_dim, 256) — MMA instruction N limit
- n_pv_tiles = head_dim // pv_n_tile — outer loop count
- V FMHA layout uses pv_n_tile (not head_dim) for N-tile slicing
- Test loops over N-tiles at Python level, kernel processes (128, pv_n_tile)
- For hd=512: 2 kernel launches with V[:,0:256] and V[:,256:512]
2026-05-23 03:22:23 +00:00
f2dced88a3 d1: add hd=512 test 2026-05-23 03:20:46 +00:00
06c3df8aad d1: add quick regression test (hd=64 only) 2026-05-23 03:20:12 +00:00
0102294d29 D1: Parameterize HEAD_DIM in FmhaKernel (64→512)
- Promote HEAD_DIM from module constant to constructor parameter
- FmhaKernel(head_dim=64, s_k=128, ...) — default 64 for regression
- All references to HEAD_DIM replaced with self.head_dim
- PV MMA tiler, V layout, softmax corr_tiles all parameterized
- TMEM budget warning when num_tmem_alloc_cols > 512
- New test: test_fmha_v3_stage_d1.py tests hd=64 (regression) and hd=512
- Stage C test preserved as-is for reference
2026-05-23 03:19:52 +00:00
b1fe18acbb cleanup: remove archive/ (240 stale files), stale example9/10, fix test table, add Stage D plan 2026-05-23 03:05:08 +00:00
a7038de611 fix: revert to composition layout for hand-constructed atoms (matching CUTLASS) 2026-05-23 02:54:54 +00:00
de7cc61480 fix: use logical_divide (not composition) for O rescale/normalize atoms to match get_tmem_load_op layout 2026-05-23 02:53:59 +00:00
71934f78b2 fix: add NO-OP TMEM round-trip to re-map O from MMA to epilog layout 2026-05-23 02:50:53 +00:00
ac1feeb895 fix: use TMEM round-trip normalize + epilogue_tma_store (known ~3% error) 2026-05-23 02:49:46 +00:00
8ac05f2b26 fix: correct bSG_gC indexing (6 modes) 2026-05-23 02:45:30 +00:00
c403b57617 diag: print bSG shapes for TMA store indexing 2026-05-23 02:44:47 +00:00
1d3c169805 fix: typo from_dlcap -> from_dlpack 2026-05-23 02:44:00 +00:00
4b9949092e fix: correction_epilog with paired atoms + pre-partitioned TMA store outside if block 2026-05-23 02:41:07 +00:00
24412df914 test: NO-OP round-trip + normalize at n=128 and n=256 2026-05-23 02:37:50 +00:00
22f8870fbd fix: correction_epilog with paired atoms + pre-partitioned TMA store 2026-05-23 02:34:33 +00:00
fb4888079a diag: NO-OP round-trip before normalize on 2D pattern 2026-05-23 02:32:40 +00:00
3416c46a05 fix: O rescale uses 2D register tensor pattern, remove fence_view_async_tmem_load 2026-05-23 02:31:28 +00:00
b457d196af fix: use paired atoms for correction_epilog + cute.copy TMA store 2026-05-23 02:26:57 +00:00
e3d6d6eebf diag: add CUDA_LAUNCH_BLOCKING for crash debug 2026-05-23 02:25:46 +00:00
1ee99cbef6 fix: inline epilogue_tma_store with inv_row_sum multiply using paired atoms 2026-05-23 02:24:36 +00:00
09568b46ba fix: use cute.copy instead of cpasync.copy for TMA store 2026-05-23 02:23:16 +00:00
23d77286ff fix: correction_epilog with get_tmem_load_op paired atoms + direct TMA store 2026-05-23 02:19:41 +00:00
b10a8af198 diag: NO-OP TMEM round-trip test — load+store back unchanged 2026-05-23 02:15:28 +00:00
641034217d fix: inline epilogue with paired atoms + inv_row_sum normalize, no TMEM round-trip 2026-05-23 02:13:52 +00:00
f9bb2c18e3 fix: all epilogue warps do TMA store, no dynamic if inside method 2026-05-23 01:41:36 +00:00
7123c214bf fix: correction_epilog with get_tmem_load_op paired atoms, no TMEM round-trip 2026-05-23 01:40:13 +00:00
9d29441690 fix: use attn_raw (not softmax'd) for unnorm computation 2026-05-23 01:36:27 +00:00
8f65bcd02f diag: skip kernel normalize, do Python-side normalize to isolate TMEM round-trip issue 2026-05-23 01:35:18 +00:00
9347119ade diag: print expected unnorm P@V for comparison with raw kernel output 2026-05-23 01:28:32 +00:00
e5b4da7274 diag: skip final normalize, test raw PV output via epilogue_tma_store 2026-05-23 01:27:03 +00:00
e7b2cb5a32 fix: O rescale uses 2D register tensor pattern (matching CUTLASS correction_rescale) 2026-05-23 01:25:53 +00:00
c1f531c0e6 fix: pre-compute tmem_load_epi_atom in __call__, pass to kernel 2026-05-23 01:24:33 +00:00
9c9eb18c73 fix: index into TMA partitioned tensors for copy 2026-05-23 01:23:04 +00:00
6503dc8659 fix: use flat_divide+group_modes(0,2) for TMA store, matching CUTLASS 2026-05-23 01:22:22 +00:00
5630398498 fix: use gC not tCgC for TMA partition, group modes 0-3 2026-05-23 01:20:52 +00:00
6b2dda02ec fix: use tma_partition for TMA store in correction_epilog 2026-05-23 01:20:09 +00:00
e70230825a fix: replace TMEM round-trip normalize with CUTLASS correction_epilog pattern 2026-05-23 01:18:56 +00:00
ed8855285c diag: inv_row_sum=1.0 to test raw PV, n=128 only 2026-05-23 01:17:14 +00:00
dc8d95a5ce diag: test original code n=128+256 to confirm baseline 2026-05-23 01:13:29 +00:00