Commit Graph

837 Commits

Author SHA1 Message Date
518dce37f0 SMEM-P: Implement rank mismatch fix by reshaping source tensor 2026-05-23 09:33:24 +00:00
a3659c581d Update STAGE_D.md checklist with current progress and lessons learned 2026-05-23 09:27:48 +00:00
c9dda47971 Add more debug prints for sP shapes 2026-05-23 09:26:30 +00:00
2283de1cfc Add debug prints to SMEM-P path to understand rank mismatch 2026-05-23 09:25:48 +00:00
7c350e6a18 Fix SMEM-P copy rank mismatch (use rP_bf16 directly instead of group_modes) 2026-05-23 09:21:13 +00:00
cb2849bff5 D1.3: Implement SMEM-P path (write P to SMEM via tiled_smem_copy instead of zeroing sP) 2026-05-23 09:20:37 +00:00
2c36cd0d32 Stage D1: Multi-PV-tile support for hd>256 (tcgen05 MMA max N=256) 2026-05-23 09:04:01 +00:00
f556060ddf Fix v_fmha layout to use pv_n_tile instead of head_dim for multi-PV-tile support 2026-05-23 09:02:01 +00:00
f1ad264da6 D1.4: Add pv_n_tile and n_pv_tiles for multi-PV-tile support (tcgen05 MMA max N=256) 2026-05-23 09:00:18 +00:00
2083204a90 diag: add 2-CTA check + fix LayoutEnum in MMA test 2026-05-23 08:45:26 +00:00
02daa63f67 fix: remove bad import in NVFP4 diag 2026-05-23 08:44:37 +00:00
401e24768a fix: import ceil_div in quantize.py (was NameError at runtime) 2026-05-23 08:40:24 +00:00
28724b8c18 fix: use quantize_activation_nvfp4 in diag 2026-05-23 08:39:12 +00:00
690be100aa fix: use correct API for NVFP4-0 diag (sf_vec_size + mma_tiler_mn) 2026-05-23 08:38:19 +00:00
0fc43eb624 fix: use Sm100BlockScaledPersistentDenseGemmKernel in diag 2026-05-23 08:30:43 +00:00
e6c9616eba fix: use randint+view for FP4/FP8 tensors in diag 2026-05-23 08:29:16 +00:00
96567ea64d fix: NVFP4-0 diag script — import SF_VEC_SIZE from quantize.py 2026-05-23 08:28:13 +00:00
f6f4ce8ec2 diag: NVFP4-0 primitive verification script 2026-05-23 08:26:56 +00:00
241b49b1ee docs: add NVFP4 precision roadmap to STAGE_D.md (3 honest buckets + speculative bucket) 2026-05-23 07:39:09 +00:00
73fa8a2b70 shit carmine left dangling 2026-05-23 06:55:22 +00:00
bd2da14ca6 D1.2: TMEM budget verified on B200. Split-PV mandatory at hd=512 (MMA max N=256) 2026-05-23 06:43:01 +00:00
a951a95276 D1.2: fix probe for hd=512 (MMA max N=256, use pv_n_tile) 2026-05-23 06:41:42 +00:00
97899b42a3 D1.2: simplify TMEM budget probe, fix printf args 2026-05-23 06:40:55 +00:00
640bae606e fix: cuda.CUstream import 2026-05-23 06:40:05 +00:00
595c9d677c D1.2: TMEM budget probe using @cute.jit for MLIR context 2026-05-23 06:39:27 +00:00
1a781447cb fix: remove unused v_fmha_layout from probe 2026-05-23 06:38:08 +00:00
3490601e02 D1.2: TMEM budget probe with real tensor major modes 2026-05-23 06:37:34 +00:00
8b351bd871 fix: OperandMajorMode.MN not .M 2026-05-23 06:36:39 +00:00
5b3bd4876c fix: typo + OperandMajorMode for TMEM budget probe 2026-05-23 06:35:55 +00:00
677245fc5c fix: LayoutEnum import from cutlass.utils 2026-05-23 06:35:03 +00:00
bd968db5d4 fix import path for tcgen05 2026-05-23 06:34:30 +00:00
afec55ad72 D1.2: TMEM budget probe script for hd=64,128,256,512 2026-05-23 06:33:26 +00:00
5012703bad fix: add SwiGLU clamping to fused kernel (paper §4.2.3, CG-1)
The fused SwiGLU kernel stored swiglu_limit but never applied it.
Paper §4.2.3: gate capped at swiglu_limit, linear clamped to [-limit, +limit].
Non-fused reference path already applies clamping correctly.
Fix: add fmin/fmax clamping in FP32 before BF16 conversion.
2026-05-23 06:32:54 +00:00
580d2f6999 STAGE_D.md: restructure with correctness gaps, TMEM budget, execution order 2026-05-23 06:31:37 +00:00
df43c3232d D1.1: Fix make_fragment_A — use sP for SMEM source pv_mma 2026-05-23 06:04:44 +00:00
80434d0284 D1.1: Fix PV A-operand construction — compile-time branch for TMEM vs SMEM 2026-05-23 06:03:27 +00:00
d36b727898 D1.1: Add SMEM-P path behind use_smem_p flag (stub: zero sP) 2026-05-23 06:01:02 +00:00
bd0b56dddd D1.0: Replace HEAD_DIM=64 with self.head_dim constructor parameter 2026-05-23 05:55:03 +00:00
249a581d8a Add STAGE_D.md: step-by-step runbook and todo list for D1-D5 2026-05-23 05:52:03 +00:00
bfacfeca7b Rename FmhaV3StageC → FmhaKernel — no dev stage artifacts in production API 2026-05-23 05:45:58 +00:00
787a25516d Update README: reflect Stage C migration, built indexer/router/compressor, SMEM-P path, CuTeDSL scoping lesson 2026-05-23 05:42:44 +00:00
b39301ebc6 Migrate Stage C kernel (proven cos 0.97) into module - exact copy, no modifications 2026-05-23 05:36:22 +00:00
6c9a9d72f1 Fix TMEM-P offset calc: match Stage C with p_cols_fp32 from pv_mma_tiler[2] 2026-05-23 05:18:37 +00:00
03748c4215 Add missing TMEM fence after P store in TMEM-P path 2026-05-23 05:17:45 +00:00
9c93d655de Fix p_cols_fp32: use pv_mma_tiler[2] (K-dim) not [1] (N-dim) 2026-05-23 05:16:19 +00:00
32ae44d97d Fix PV A-operand major mode: K for TMEM-P, a_major for SMEM-P 2026-05-23 05:14:08 +00:00
7df67d5237 Fix CuTeDSL scoping: hoist P store vars out of if block 2026-05-23 05:12:30 +00:00
2addbeed7d Fix O rescale: use Stage C proven correction_rescale pattern 2026-05-23 05:10:46 +00:00
86f3e9cf32 Fix tOrP0 indexing: 3-dim slice (None,None,kb) not 4-dim 2026-05-23 05:09:19 +00:00
75fec90eef Fix CuTeDSL scoping: unconditionally define tOrP0 and tCrP 2026-05-23 05:08:10 +00:00