43bb501acb
D1.3: Use full sP (4D) for make_tiled_copy_D partition
2026-05-23 22:27:11 +00:00
06fd2f63e9
D1.3: SMEM-P via get_smem_store_op + make_tiled_copy_D
...
Uses the CUTLASS blackwell_helpers pattern:
- get_smem_store_op creates a SMEM store atom paired with the TMEM load
- make_tiled_copy_D uses the same thread partition as the TMEM load
- Softmax warps write P to sP using the same thread mapping they use for reading S
- MMA warp reads P from sP via pv_mma.make_fragment_A(sP)
- Replaces the zero-fill stub with a proper register→SMEM copy
2026-05-23 22:26:09 +00:00
c507d0640c
D1.3: Enhanced diagnostic - test QK C-fragment as source for make_tiled_copy_C
2026-05-23 22:24:15 +00:00
bf896c0894
D1.3: Skip fragment creation in diagnostic, just print layouts
2026-05-23 22:21:31 +00:00
0c435b3e51
D1.3: Fix diagnostic - use dummy ptr 0 for shape analysis
2026-05-23 22:20:16 +00:00
55caf8be38
D1.3: Fix sP allocation - p_smem_s.outer is already a layout
2026-05-23 22:19:11 +00:00
d1c600f599
D1.3: Fix layout diagnostic - compute c_major outside kernel
2026-05-23 22:17:54 +00:00
d3d0020b4e
D1.3: Layout diagnostic v2 - run inside JIT-compiled kernel
2026-05-23 22:16:57 +00:00
ec8fd1474c
D1.3: Fix layout diagnostic - remove JIT-dependent code
2026-05-23 22:15:47 +00:00
c3a7c30f20
D1.3: Layout diagnostic - print all QK C-fragment and PV A-operand shapes
2026-05-23 22:14:35 +00:00
b59aca4655
Update all .md files with D5a/D5b progress, tOrP0 fix, LSE formula
...
- README.md: Updated Stage status table (D1 🟡 , D5 🟢 ), D5 section with
D5a/D5b results, tOrP0 bug fix docs, new CuTeDSL constraints #11-12
- STAGE_D1.3.md: Added progress update - TMEM-P works, SMEM-P still blocked,
recommended next steps
- STAGE_D.md was already updated
2026-05-23 22:07:53 +00:00
9264023e3b
Update STAGE_D.md with D5b results: merge cos 0.961, LSE err=0.0
2026-05-23 21:45:22 +00:00
2ced9d0da7
D5b: Fix reference computation - use logsumexp for stable LSE, fix o_unnorm definition
2026-05-23 21:43:04 +00:00
2883e042ca
D5b MILESTONE: SWA+sink merge works! cos 0.969
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- Run FMHA twice (compressed KV + SWA KV) with normalized O + LSE
- Merge with sink weights in Python
- LSE err=0.0, merge cos=0.969 PASS
- Update STAGE_D.md: D5b done, D5c/D5d are optimizations
2026-05-23 21:36:26 +00:00
70763030c0
D5b: Use normalized O + LSE for merge (correct formula), always output LSE
2026-05-23 21:35:40 +00:00
28949da6e4
D5b: Clean up merge test - stable formula for both ref and kernel
2026-05-23 21:33:45 +00:00
9e1859827f
D5b: Use reference per-row LSE for proper O normalization
2026-05-23 21:31:52 +00:00
48d37d652e
D5b: Fix kernel_obj reference
2026-05-23 21:30:59 +00:00
caf89c65bf
D5b: Fix syntax error
2026-05-23 21:30:00 +00:00
3dd9cd6a94
D5b: Debug reference formula mismatch, add numerically stable merge
2026-05-23 21:19:25 +00:00
98390df27e
D5b: Python SWA+sink merge test
...
- Run FMHA twice (compressed KV + SWA KV, normalize=False)
- Merge with sink weights in Python
- Verify end-to-end correctness vs FP32 reference
2026-05-23 21:18:06 +00:00
60e03fe84a
Update STAGE_D.md: D5a done, CG-2/CG-3 status updated, tOrP0 offset rule added
2026-05-23 21:16:52 +00:00
edc283e6c1
D5a: Fix LSE formula - lse = ln(row_sum) + row_max * ln(2)
...
row_max is in scale_log2 domain, need to convert to natural log domain.
attn_max = row_max * ln(2), so lse = ln(row_sum) + row_max * ln(2).
2026-05-23 21:15:14 +00:00
6ca294ed6d
D5a: Use tensor indexing for LSE write
2026-05-23 21:13:52 +00:00
7e91d76669
D5a: Use cute.store for LSE write
2026-05-23 21:13:07 +00:00
751abd9b18
D5a: Fix LSE - compute row_max_safe from final row_max, remove mLSE None check
2026-05-23 21:12:29 +00:00
d6ea7f3ebd
D5a: Fix - add normalize param to __init__
2026-05-23 21:11:37 +00:00
c80f223d08
D5a: Add normalize flag + LSE output
...
- normalize=True (default): O = softmax(P) @ V (existing behavior)
- normalize=False: O = P @ V (un-normalized) + lse = log(row_sum) + row_max
- LSE tensor passed as optional parameter
- Test includes D5a normalize=False verification with LSE comparison
- Cleaned up SMEM-P debug prints and broken make_tiled_copy_C code
- hd=64 TMEM-P regression: cos 0.973 PASS
2026-05-23 21:10:40 +00:00
542bc7b1b0
D1.3: Use const_expr if for tOrP0 compile-time selection
2026-05-23 21:07:58 +00:00
37edd783ce
D1.3: Pre-compute tOrP0_offset in _setup, use const_expr for compile-time selection
2026-05-23 21:07:10 +00:00
972fbd48b9
D1.3: Use const_expr for tOrP0 offset (compile-time conditional)
2026-05-23 21:06:16 +00:00
a762820352
D1.3: Use MLIR-compatible expression for tOrP0 offset (same as Stage C)
2026-05-23 21:05:12 +00:00
4fa4239f95
D1.3: Initialize tOrP0 before conditional for CuTeDSL scoping
2026-05-23 21:03:53 +00:00
2bb3eb95ed
D1.3: Fix tOrP0 for SMEM-P - skip make_tensor when offset is 0
...
CuTeDSL doesn't support OpResult + int. When offset is 0 (SMEM-P),
just use tOrP directly.
2026-05-23 21:03:00 +00:00
eabea91b64
D1.3: Fix tOrP0 offset - scale FP32 columns to BF16 elements
...
tmem_p0_offset is in FP32 columns, but tOrP uses BF16 elements.
Offset = p0_offset * (32/16) = p0_offset * 2.
2026-05-23 21:02:04 +00:00
47eade4afc
D1.3: Fix CuTeDSL scoping - define tOrP0 unconditionally with p0 offset
2026-05-23 21:01:18 +00:00
0e81fc18aa
D1.3: Fix critical bug - add TMEM column offset for P0 in PV GEMM
...
The softmax warps store P at tmem_p0_offset=32. PV MMA must read from
the same offset. tOrP0 was missing the offset, causing PV to read from
TMEM column 0 (where S is) instead of column 32 (where P is).
This was the root cause of NaN/zeros in D1 tests.
2026-05-23 21:00:29 +00:00
29f4480e26
D1.3: Revert to d1.3-pre-sm100-helpers baseline for testing
2026-05-23 20:58:06 +00:00
adb4398505
D1.3: DIAGNOSTIC - test epilogue_tma_store raw PV without any round-trips
2026-05-23 20:57:13 +00:00
0e41816636
D1.3: Remove NO-OP round-trip, keep normalize + epilogue_tma_store
2026-05-23 20:56:13 +00:00
8bc8b21470
D1.3: Full correction_epilog with TMA store, normalize in reg before SMEM write
...
One-way trip: TMEM->reg (normalize) ->SMEM->GMEM
Replicates epilogue_tma_store logic with normalize step added
Uses CUTLASS helpers for correct layout handling
2026-05-23 20:54:23 +00:00
d769e01a16
D1.3: Apply transform_partitioned_tensor_layout before epilogue helpers
2026-05-23 20:52:42 +00:00
cc18fddc7e
D1.3: Replace NO-op TMEM round-trip with correction_epilog using epilogue_tmem_copy_and_partition + epilogue_smem_copy_and_partition
...
- Remove hand-constructed TMEM round-trips (3% layout mismatch error)
- Use CUTLASS get_tmem_load_op + get_smem_store_op paired atoms
- One-way trip: TMEM -> reg (normalize) -> SMEM -> GMEM
- SMEM-P path: zero-fill stub (proper copy TBD)
- Keep per-tile O rescale atoms for n>128 support
2026-05-23 20:50:23 +00:00
993ec32567
SMEM-P: test permutation 4 (swap m↔n2)
2026-05-23 20:20:07 +00:00
c7a299d7d9
SMEM-P: add iterator offset debug print
2026-05-23 20:19:22 +00:00
4943af749d
SMEM-P: add tCrP debug print, reset permute to 0
2026-05-23 20:14:32 +00:00
5a11f7c09a
SMEM-P: test permutation 1 (swap m↔n0)
2026-05-23 20:14:21 +00:00
d5081fe6f0
auto: pre-test commit
2026-05-23 20:13:47 +00:00
fd54d657b2
SMEM-P: add debug_permute flag for coordinate permutation testing
2026-05-23 20:13:44 +00:00
06409401ca
SMEM-P: disable debug flags, revert to original mapping
2026-05-23 20:12:26 +00:00
