398f5cf631
fix: BFloat16 not Float32 for bf16 reg
2026-05-23 03:50:09 +00:00
9bc7fc9361
WIP: P→SMEM write stub (zero fill, proper mapping TODO)
2026-05-23 03:49:05 +00:00
ed35a8a4ba
fix: partition_A not partition_S
2026-05-23 03:47:53 +00:00
48432522b8
fix: make_smem_layout_epi not make_epilogue_smem_layout
2026-05-23 03:47:09 +00:00
07f319d1f3
WIP: SMEM P path for PV (compiles but P write not implemented)
2026-05-23 03:46:01 +00:00
1be005296c
debug: hd=64 with CUDA_LAUNCH_BLOCKING
2026-05-23 03:42:53 +00:00
482928f142
D1: P store as BF16 using PV A-fragment layout (tOrP0)
...
Reverted tP to p_tmem_s.outer (needed for make_fragment_A profile).
P store now writes BF16 to TMEM using tOrP0's layout, matching PV A-fragment reads.
This fixes the layout mismatch at hd>64 where QK C-fragment composition
writes to different TMEM columns than PV A-fragment reads.
2026-05-23 03:42:07 +00:00
f266c3dae2
D1: align P store and PV A-fragment layouts via tP
...
Key insight: tP (PV A-fragment base) used p_tmem_s.outer layout,
but P store used QK C-fragment composition layout. These diverge at hd>64.
Fix: tP now uses the same QK C-fragment composition layout (tStP_layout)
as the P store. PV A-fragment is derived from tP, so it automatically
uses the same layout. No double-offset since tP includes P offset.
2026-05-23 03:40:10 +00:00
059c2e6cd9
D1: P store as BF16 using PV A-fragment layout
...
- Changed P store from FP32 QK C-fragment layout to BF16 PV A-fragment layout
- rP_bf16_reg stores directly to TMEM using tOrP0 layout
- Ensures softmax writes P to same TMEM columns that PV GEMM reads
2026-05-23 03:38:24 +00:00
2efd6be8af
D1: P store uses tOrP0.layout (PV A-fragment TMEM layout)
2026-05-23 03:36:40 +00:00
7751eab711
D1 fix: P store uses PV A-fragment layout (p_tmem_s.outer)
...
CRITICAL BUG: P was stored using QK C-fragment composition layout, but PV
A-fragment reads using p_tmem_s.outer (PV A-operand layout). These layouts
match at hd=64 (cos 0.999998) but diverge at hd>64 (cos 0.784 at hd=128).
The fix: tStP0 and tScP now use p_tmem_s.outer instead of
composition(tStS.layout, (128, p_cols_fp32)). This ensures the softmax
writes P in the same layout that the PV GEMM expects.
2026-05-23 03:35:49 +00:00
fe1826b0de
D1: test raw unnormalized output via epilogue_tma_store
2026-05-23 03:33:59 +00:00
091cb59be5
test: paired atoms epilog from old commit 6ee28d8
2026-05-23 03:32:53 +00:00
f23d55fd3f
D1: paired atoms epilogue (no TMEM round-trip)
...
Replace NO-OP round-trip + normalize + epilogue_tma_store with:
- get_tmem_load_op + get_smem_store_op paired atoms
- One-way TMEM→reg (normalize) →SMEM→GMEM
- Eliminates ~3% error from TMEM layout mismatch
- O rescale disabled (single KV tile only for now)
- Pre-computed TMA partitions outside if blocks
2026-05-23 03:29:51 +00:00
7df3c7c952
d1: sweep hd=64,128,256
2026-05-23 03:26:10 +00:00
81378133cc
fix: use mV.iterator
2026-05-23 03:25:29 +00:00
a66a9efd4c
fix: use mQ not q for LayoutEnum
2026-05-23 03:24:58 +00:00
d2aaab5a32
d1: add diagnostic script
2026-05-23 03:24:16 +00:00
a2d063a48b
D1: N-tile support for HEAD_DIM>256
...
- pv_n_tile = min(head_dim, 256) — MMA instruction N limit
- n_pv_tiles = head_dim // pv_n_tile — outer loop count
- V FMHA layout uses pv_n_tile (not head_dim) for N-tile slicing
- Test loops over N-tiles at Python level, kernel processes (128, pv_n_tile)
- For hd=512: 2 kernel launches with V[:,0:256] and V[:,256:512]
2026-05-23 03:22:23 +00:00
7bc097163d
d1: add hd=512 test
2026-05-23 03:20:46 +00:00
32995c2ba3
d1: add quick regression test (hd=64 only)
2026-05-23 03:20:12 +00:00
eed981bee5
D1: Parameterize HEAD_DIM in FmhaKernel (64→512)
...
- Promote HEAD_DIM from module constant to constructor parameter
- FmhaKernel(head_dim=64, s_k=128, ...) — default 64 for regression
- All references to HEAD_DIM replaced with self.head_dim
- PV MMA tiler, V layout, softmax corr_tiles all parameterized
- TMEM budget warning when num_tmem_alloc_cols > 512
- New test: test_fmha_v3_stage_d1.py tests hd=64 (regression) and hd=512
- Stage C test preserved as-is for reference
2026-05-23 03:19:52 +00:00
1a6c5e3822
docs: revised Stage D/E plan — indexer removes paged TMA, one kernel for CSA/HCA/SWA, sink merge
2026-05-23 03:10:41 +00:00
a846193c4a
cleanup: remove archive/ (240 stale files), stale example9/10, fix test table, add Stage D plan
2026-05-23 03:05:08 +00:00
f3d0d67ae9
docs: update README with Stage C TMEM layout mismatch findings and status
2026-05-23 03:01:04 +00:00
9c331de7ba
fix: revert to composition layout for hand-constructed atoms (matching CUTLASS)
2026-05-23 02:54:54 +00:00
3a2d3c66da
fix: use logical_divide (not composition) for O rescale/normalize atoms to match get_tmem_load_op layout
2026-05-23 02:53:59 +00:00
3aba5cc6da
fix: add NO-OP TMEM round-trip to re-map O from MMA to epilog layout
2026-05-23 02:50:53 +00:00
45cf89a556
fix: use TMEM round-trip normalize + epilogue_tma_store (known ~3% error)
2026-05-23 02:49:46 +00:00
350c7c36ac
fix: correct bSG_gC indexing (6 modes)
2026-05-23 02:45:30 +00:00
6318b4da29
diag: print bSG shapes for TMA store indexing
2026-05-23 02:44:47 +00:00
28060dd944
fix: typo from_dlcap -> from_dlpack
2026-05-23 02:44:00 +00:00
048a546e76
fix: correction_epilog with paired atoms + pre-partitioned TMA store outside if block
2026-05-23 02:41:07 +00:00
0700745852
test: NO-OP round-trip + normalize at n=128 and n=256
2026-05-23 02:37:50 +00:00
2ebfcb2278
fix: correction_epilog with paired atoms + pre-partitioned TMA store
2026-05-23 02:34:33 +00:00
49bf6e8294
diag: NO-OP round-trip before normalize on 2D pattern
2026-05-23 02:32:40 +00:00
6cf1f17904
fix: O rescale uses 2D register tensor pattern, remove fence_view_async_tmem_load
2026-05-23 02:31:28 +00:00
7842d86294
fix: use paired atoms for correction_epilog + cute.copy TMA store
2026-05-23 02:26:57 +00:00
1f4e40decc
diag: add CUDA_LAUNCH_BLOCKING for crash debug
2026-05-23 02:25:46 +00:00
728a24db6a
fix: inline epilogue_tma_store with inv_row_sum multiply using paired atoms
2026-05-23 02:24:36 +00:00
0ecde542f1
fix: use cute.copy instead of cpasync.copy for TMA store
2026-05-23 02:23:16 +00:00
702bf8aa29
fix: correction_epilog with get_tmem_load_op paired atoms + direct TMA store
2026-05-23 02:19:41 +00:00
ea66b6ee8d
diag: NO-OP TMEM round-trip test — load+store back unchanged
2026-05-23 02:15:28 +00:00
6ee28d8423
fix: inline epilogue with paired atoms + inv_row_sum normalize, no TMEM round-trip
2026-05-23 02:13:52 +00:00
043b66406a
fix: all epilogue warps do TMA store, no dynamic if inside method
2026-05-23 01:41:36 +00:00
db3572bafb
fix: correction_epilog with get_tmem_load_op paired atoms, no TMEM round-trip
2026-05-23 01:40:13 +00:00
d99a90ade5
fix: use attn_raw (not softmax'd) for unnorm computation
2026-05-23 01:36:27 +00:00
7becdaf739
diag: skip kernel normalize, do Python-side normalize to isolate TMEM round-trip issue
2026-05-23 01:35:18 +00:00
039c8b90ce
diag: print expected unnorm P@V for comparison with raw kernel output
2026-05-23 01:28:32 +00:00
ec5b892e32
diag: skip final normalize, test raw PV output via epilogue_tma_store
2026-05-23 01:27:03 +00:00
