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D1.5: multi-row + multi-tile FMHA with SMEM accumulator in-kernel rescale

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biondizzle
2026-05-30 04:37:33 +00:00
parent 10ae8f3346
commit dd3e0fdfc8
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dsv4/kernels/attention/fmha_6warp_tma_multirow_multitile.cuh Normal file
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/**
* DSV4 FMHA — 6-warp TMA, multi-row softmax, multi-tile KV, in-kernel rescale.
*
* Combines fmha_6warp_tma_multirow (T>1 softmax) with fmha_6warp_tma_multitile
* (in-kernel per-KV-tile O rescale, avoiding the broken D1.5 TMEM round-trip).
*
* Design:
* SMEM accumulator float sOacc[MAX_ROWS][HD].
* Per KV tile:
* 1. QK GEMM → softmax (un-normalized P for multi-tile) → PV GEMM
* 2. Read O_tile from TMEM → registers
* 3. Online softmax rescale of sOacc: multiply by exp(old_max - new_max)
* 4. Add rescaled O_tile to sOacc
* 5. Update per-row running_max, running_sum in SMEM
* Final: normalize sOacc by running_sum → BF16 → GMEM + LSE
*
* SMEM budget (HD=128): ~64KB o_acc + ~26KB pipeline = ~90KB (fits 227KB)
* SMEM budget (HD=256): ~128KB o_acc + ~26KB pipeline = ~154KB (fits)
* HD=512 needs HD tiling (future).
*/
#pragma once
#include "fmha_common.cuh"
#include "fmha_umma_desc.cuh"
#include "fmha_tma.cuh"
namespace dsv4::kernels::attention {
struct FmhaTmaMultiRowMultiTileParams {
const bf16_t* __restrict__ q;
CUtensorMap* __restrict__ tma_k;
CUtensorMap* __restrict__ tma_v;
bf16_t* __restrict__ o;
float* __restrict__ lse;
int s_k, T, n_h;
float scale;
int q_head_stride, q_batch_stride;
int o_head_stride, o_batch_stride;
int lse_head_stride, lse_batch_stride;
};
template<int HD, int SK_TILE = 128>
__global__ void __launch_bounds__(192)
fmha_6warp_tma_multirow_multitile_kernel(FmhaTmaMultiRowMultiTileParams params) {
static_assert(HD <= 256, "HD>256 needs HD tiling");
static constexpr int NKT_QK = HD / MMA_K_BF16;
static constexpr int NKT_PV = SK_TILE / MMA_K_BF16;
static constexpr int N_NSUB = HD / 16;
static constexpr int MAX_ROWS = 128;
static constexpr int TILE_SZ = 128 * MMA_K_BF16;
static constexpr int V_SUB_SZ = 16 * MMA_K_BF16;
static constexpr int TMEM_N = (HD <= 128) ? 128 : (HD <= 256) ? 256 : 512;
static constexpr int CORES_MN = 128 / 8;
static constexpr int NUM_READS = SK_TILE / 8;
static constexpr int TMA_TILE_BYTES = TILE_SZ * sizeof(bf16_t);
const int head_idx = blockIdx.y;
const int batch_idx = blockIdx.z;
const int tid = threadIdx.x;
const int wid = tid / 32;
const int lane = tid % 32;
const bool is_softmax_warp = (wid < 4);
const bool is_mma_warp = (wid == 4);
const bool is_load_warp = (wid == 5);
const int T = params.T;
const int s_k = params.s_k;
const int n_kv_tiles = (s_k + SK_TILE - 1) / SK_TILE;
const float scale = params.scale;
const bf16_t* __restrict__ q_head = params.q + head_idx * params.q_head_stride + batch_idx * params.q_batch_stride;
bf16_t* __restrict__ o_head = params.o + head_idx * params.o_head_stride + batch_idx * params.o_batch_stride;
float* __restrict__ lse_head = params.lse ? params.lse + head_idx * params.lse_head_stride + batch_idx * params.lse_batch_stride : nullptr;
CUtensorMap* __restrict__ my_tma_k = params.tma_k + batch_idx * params.n_h + head_idx;
CUtensorMap* __restrict__ my_tma_v = params.tma_v + batch_idx * params.n_h + head_idx;
// ================================================================
// SMEM
// ================================================================
extern __shared__ __align__(128) char sbuf[];
size_t off = 0;
uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off += 4;
off = (off + 127) & ~(size_t)127;
uint64_t* sMbar = (uint64_t*)(sbuf + off); off += 16;
off = (off + 127) & ~(size_t)127;
bf16_t* sTmaBuf = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
off = (off + 127) & ~(size_t)127;
bf16_t* sQ0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
off = (off + 127) & ~(size_t)127;
bf16_t* sK0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
off = (off + 127) & ~(size_t)127;
bf16_t* sPk = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
off = (off + 127) & ~(size_t)127;
bf16_t* sV = (bf16_t*)(sbuf + off); off += V_SUB_SZ * sizeof(bf16_t);
off = (off + 127) & ~(size_t)127;
// SMEM accumulator + per-row running stats
float* sOacc = (float*)(sbuf + off); off += MAX_ROWS * HD * sizeof(float);
float* sRunningMax = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
float* sRunningSum = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
// Per-tile row max/sum (softmax → accumulator)
float* sTileRowMax = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
float* sTileRowSum = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
// Init
if (is_mma_warp) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
if (tid == 0) {
tma_mbarrier_init((uint32_t)__cvta_generic_to_shared(sMbar), 1);
asm volatile("fence.mbarrier_init.release.cluster;" ::: "memory");
}
__syncthreads();
uint32_t tb = *sTmemBase;
const uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(sMbar);
int phase = 0;
const bool my_warp_active = (T <= 32) ? (wid == 0) : is_softmax_warp;
const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
const bool my_row_active = my_warp_active && (my_row < T);
// Initialize SMEM accumulator
for (int i = tid; i < MAX_ROWS * HD; i += 192) sOacc[i] = 0.0f;
for (int i = tid; i < MAX_ROWS; i += 192) {
sRunningMax[i] = -INFINITY;
sRunningSum[i] = 0.0f;
}
__syncthreads();
// ================================================================
// Multi-tile KV loop
// ================================================================
for (int kv_tile = 0; kv_tile < n_kv_tiles; kv_tile++) {
int kv_start = kv_tile * SK_TILE;
int kv_len = min(SK_TILE, s_k - kv_start);
// ---- QK GEMM ----
for (int kt = 0; kt < NKT_QK; kt++) {
if (is_load_warp) {
for (int i = lane; i < TILE_SZ; i += 32) sQ0[i] = 0;
for (int r = 0; r < T; r++) {
for (int d = lane; d < MMA_K_BF16; d += 32) {
int full_d = kt * MMA_K_BF16 + d;
if (full_d < HD) {
int ck = d/8, lc = d%8, cm = r/8, lr = r%8;
sQ0[ck*CORES_MN*64 + cm*64 + lr*8 + lc] = q_head[r * HD + full_d];
}
}
}
}
if (is_load_warp && lane == 0) {
tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)my_tma_k,
mbar_addr, kt * MMA_K_BF16, kv_start);
tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
}
tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
__syncthreads();
for (int i = tid; i < TILE_SZ; i += 192) sK0[i] = 0;
for (int i = tid; i < kv_len * MMA_K_BF16; i += 192) {
int r = i / MMA_K_BF16, c = i % MMA_K_BF16;
int ck = c/8, lc = c%8, tmn = r/8, lr = r%8;
sK0[ck*CORES_MN*64 + tmn*64 + lr*8 + lc] = sTmaBuf[i];
}
__syncthreads();
if (is_mma_warp) {
uint32_t idesc = make_idesc(128, 128);
uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
if (tid == 128) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
}
__syncthreads();
}
asm volatile("fence.sc.gpu;" ::: "memory");
__syncthreads();
// ---- Softmax (2-pass, un-normalized P) ----
float my_row_max = -INFINITY;
if (my_warp_active) {
for (int n = 0; n < NUM_READS; n++) {
float tmp[8];
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
: "r"(tb + n * 8));
asm volatile("tcgen05.wait::ld.sync.aligned;");
if (my_row_active) {
for (int c = 0; c < 8; c++) {
int col = n * 8 + c;
if (col < kv_len) my_row_max = fmaxf(my_row_max, tmp[c] * scale);
}
}
}
}
if (my_row_active) sTileRowMax[my_row] = my_row_max;
__syncthreads();
float my_p_vals[SK_TILE];
float my_row_sum = 0.0f;
if (my_warp_active) {
float rm = my_row_active ? sTileRowMax[my_row] : 0.0f;
for (int n = 0; n < NUM_READS; n++) {
float tmp[8];
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
: "r"(tb + n * 8));
asm volatile("tcgen05.wait::ld.sync.aligned;");
if (my_row_active) {
for (int c = 0; c < 8; c++) {
int col = n * 8 + c;
if (col < kv_len) {
float p = expf(tmp[c] * scale - rm);
my_p_vals[col] = p;
my_row_sum += p;
}
}
}
}
}
if (my_row_active) sTileRowSum[my_row] = my_row_sum;
__syncthreads();
// ---- PV GEMM ----
for (int n_sub = 0; n_sub < N_NSUB; n_sub++) {
int d_base = n_sub * 16;
for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
const int col_start = pv_kt * MMA_K_BF16;
if (is_load_warp) {
for (int i = lane; i < TILE_SZ; i += 32) sPk[i] = 0;
}
__syncthreads();
if (my_row_active) {
for (int c = 0; c < MMA_K_BF16; c++) {
int gc = col_start + c;
int ck = c/8, lc = c%8;
int core_mn = my_row/8, local_r = my_row%8;
sPk[ck*CORES_MN*64 + core_mn*64 + local_r*8 + lc] = f32_to_bf16(my_p_vals[gc]);
}
}
__syncthreads();
// V via TMA at (kv_start + col_start, d_base)
if (is_load_warp && lane == 0) {
tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)my_tma_v,
mbar_addr, kv_start + col_start, d_base);
tma_mbarrier_arrive_expect_tx(mbar_addr, V_SUB_SZ * sizeof(bf16_t));
}
tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
__syncthreads();
for (int i = tid; i < V_SUB_SZ; i += 192) sV[i] = 0;
for (int i = tid; i < 16 * MMA_K_BF16; i += 192) {
int dd = i / MMA_K_BF16, lr = i % MMA_K_BF16;
int g_mn = dd/8, g_k = lr/8, llr = dd%8, lc = lr%8;
sV[g_k*2*64 + g_mn*64 + llr*8 + lc] = sTmaBuf[i];
}
__syncthreads();
if (is_mma_warp) {
uint32_t idesc_pv = make_idesc(128, 16);
uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), 128);
uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
if (tid == 128) umma_ss_f16(tb + n_sub*16, dp, dv, idesc_pv, pv_kt > 0);
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
}
__syncthreads();
}
}
asm volatile("fence.sc.gpu;" ::: "memory");
__syncthreads();
// ---- Read O from TMEM, rescale sOacc, accumulate ----
if (my_warp_active) {
float tile_max = my_row_active ? sTileRowMax[my_row] : 0.0f;
float tile_sum = my_row_active ? sTileRowSum[my_row] : 0.0f;
// Read O_tile from TMEM (same pattern as multirow epilogue)
float o_tile_buf[HD];
if (my_row_active) {
for (int n = 0; n < N_NSUB * 2; n++) {
float tmp[8];
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
: "r"(tb + n * 8));
asm volatile("tcgen05.wait::ld.sync.aligned;");
for (int c = 0; c < 8; c++) {
int d = n * 8 + c;
if (d < HD) o_tile_buf[d] = tmp[c];
}
}
}
// Online softmax rescale + accumulate
if (my_row_active) {
float old_max = sRunningMax[my_row];
float new_max = fmaxf(old_max, tile_max);
float rescale_old = expf(old_max - new_max);
float rescale_new = expf(tile_max - new_max);
// Rescale existing accumulator and add new tile
for (int d = 0; d < HD; d++) {
sOacc[my_row * HD + d] = sOacc[my_row * HD + d] * rescale_old + o_tile_buf[d] * rescale_new;
}
// Update running stats
sRunningSum[my_row] = sRunningSum[my_row] * rescale_old + tile_sum * rescale_new;
sRunningMax[my_row] = new_max;
}
}
__syncthreads();
}
// ================================================================
// Final epilogue: normalize and write to GMEM
// ================================================================
if (my_warp_active) {
if (my_row_active) {
float inv_rs = 1.0f / sRunningSum[my_row];
for (int d = 0; d < HD; d++) {
o_head[my_row * HD + d] = f32_to_bf16(sOacc[my_row * HD + d] * inv_rs);
}
if (lse_head) lse_head[my_row] = logf(sRunningSum[my_row]) + sRunningMax[my_row];
}
}
__syncthreads();
if (is_mma_warp) tmem_dealloc(tb, TMEM_N);
}
} // namespace

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tests/unit/test_fmha_6warp_tma_multirow_multitile.cu Normal file
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/**
* Test fmha_6warp_tma_multirow_multitile — multi-row + multi-tile KV + in-kernel rescale.
*/
#include <cuda_runtime.h>
#include <cuda.h>
#include <cstdio>
#include <cmath>
#include <cstdlib>
#include <cstring>
#ifndef HD_VAL
#define HD_VAL 64
#endif
#include "dsv4/kernels/attention/fmha_common.cuh"
#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
#include "dsv4/kernels/attention/fmha_tma.cuh"
using namespace dsv4::kernels::attention;
static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
constexpr int HD = HD_VAL;
constexpr int SK = 128;
constexpr int MAX_T = 128;
constexpr int MY_MMA_K = 16;
constexpr int TILE_SZ = 128 * MY_MMA_K;
#include "dsv4/kernels/attention/fmha_6warp_tma_multirow_multitile.cuh"
static size_t compute_smem() {
size_t off = 0;
off += 4; off = (off+127)&~(size_t)127;
off += 16; off = (off+127)&~(size_t)127;
off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sTmaBuf
off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sQ0
off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sK0
off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sPk
off += 16 * MY_MMA_K * 2; // sV
off = (off+127)&~(size_t)127;
off += MAX_T * HD * 4; // sOacc
off += MAX_T * 4; // sRunningMax
off += MAX_T * 4; // sRunningSum
off += MAX_T * 4; // sTileRowMax
off += MAX_T * 4; // sTileRowSum
return off;
}
static void reference_attention(
const bf16_t* q, const bf16_t* k, const bf16_t* v,
float* o_ref, float* lse_ref,
int hd, int T, int s_k, float scale
) {
for (int t = 0; t < T; t++) {
float s[1024];
for (int j = 0; j < s_k; j++) {
float dot = 0.0f;
for (int d = 0; d < hd; d++) dot += bf16_to_f32_host(q[t*hd+d]) * bf16_to_f32_host(k[j*hd+d]);
s[j] = dot * scale;
}
float mx = -INFINITY;
for (int j = 0; j < s_k; j++) mx = fmaxf(mx, s[j]);
float sm = 0.0f;
for (int j = 0; j < s_k; j++) { s[j] = expf(s[j] - mx); sm += s[j]; }
for (int j = 0; j < s_k; j++) s[j] /= sm;
for (int d = 0; d < hd; d++) {
float ov = 0.0f;
for (int j = 0; j < s_k; j++) ov += s[j] * bf16_to_f32_host(v[d*s_k+j]);
o_ref[t * hd + d] = ov;
}
if (lse_ref) lse_ref[t] = logf(sm) + mx;
}
}
static int test_single(int T, int s_k, int n_h = 1, int batch = 1) {
printf("=== T=%d, s_k=%d, n_h=%d, batch=%d, HD=%d ===\n", T, s_k, n_h, batch, HD);
const float SCALE = 1.0f / sqrtf((float)HD);
int total_heads = batch * n_h;
bf16_t* h_q = (bf16_t*)calloc(total_heads * MAX_T * HD, sizeof(bf16_t));
bf16_t* h_k = (bf16_t*)calloc(total_heads * s_k * HD, sizeof(bf16_t));
bf16_t* h_v = (bf16_t*)calloc(total_heads * HD * s_k, sizeof(bf16_t));
bf16_t* h_o = (bf16_t*)calloc(total_heads * MAX_T * HD, sizeof(bf16_t));
float* h_lse = (float*)calloc(total_heads * MAX_T, sizeof(float));
srand(42);
for (int h = 0; h < total_heads; h++) {
for (int i = 0; i < T*HD; i++) h_q[h*MAX_T*HD+i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
for (int i = 0; i < s_k*HD; i++) h_k[h*s_k*HD+i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
for (int i = 0; i < HD*s_k; i++) h_v[h*HD*s_k+i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
}
bf16_t *d_q, *d_k, *d_v, *d_o;
float *d_lse;
cudaMalloc(&d_q, total_heads * MAX_T * HD * sizeof(bf16_t));
cudaMalloc(&d_k, total_heads * s_k * HD * sizeof(bf16_t));
cudaMalloc(&d_v, total_heads * HD * s_k * sizeof(bf16_t));
cudaMalloc(&d_o, total_heads * MAX_T * HD * sizeof(bf16_t));
cudaMalloc(&d_lse, total_heads * MAX_T * sizeof(float));
cudaMemcpy(d_q, h_q, total_heads * MAX_T * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemcpy(d_k, h_k, total_heads * s_k * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemcpy(d_v, h_v, total_heads * HD * s_k * sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemset(d_o, 0, total_heads * MAX_T * HD * sizeof(bf16_t));
cudaMemset(d_lse, 0, total_heads * MAX_T * sizeof(float));
// TMA descriptors for K: (s_k, HD) tile (128, 16)
CUtensorMap* tma_k_arr = (CUtensorMap*)malloc(total_heads * sizeof(CUtensorMap));
CUtensorMap* d_tma_k;
cudaMalloc(&d_tma_k, total_heads * sizeof(CUtensorMap));
for (int h = 0; h < total_heads; h++) {
create_tma_desc_2d_bf16(&tma_k_arr[h], d_k + h * s_k * HD, s_k, HD, 128, 16);
}
cudaMemcpy(d_tma_k, tma_k_arr, total_heads * sizeof(CUtensorMap), cudaMemcpyHostToDevice);
// TMA descriptors for V: (HD, s_k) tile (16, 16)
CUtensorMap* tma_v_arr = (CUtensorMap*)malloc(total_heads * sizeof(CUtensorMap));
CUtensorMap* d_tma_v;
cudaMalloc(&d_tma_v, total_heads * sizeof(CUtensorMap));
for (int h = 0; h < total_heads; h++) {
create_tma_desc_2d_bf16(&tma_v_arr[h], d_v + h * HD * s_k, HD, s_k, 16, 16);
}
cudaMemcpy(d_tma_v, tma_v_arr, total_heads * sizeof(CUtensorMap), cudaMemcpyHostToDevice);
FmhaTmaMultiRowMultiTileParams params;
params.q = d_q;
params.tma_k = d_tma_k;
params.tma_v = d_tma_v;
params.o = d_o;
params.lse = d_lse;
params.s_k = s_k;
params.T = T;
params.scale = SCALE;
params.n_h = n_h;
params.q_head_stride = MAX_T * HD;
params.q_batch_stride = n_h * MAX_T * HD;
params.o_head_stride = MAX_T * HD;
params.o_batch_stride = n_h * MAX_T * HD;
params.lse_head_stride = MAX_T;
params.lse_batch_stride = n_h * MAX_T;
size_t smem = compute_smem();
printf(" SMEM: %zu bytes (%.1f KB)\n", smem, smem / 1024.0);
if (smem > 48 * 1024)
cudaFuncSetAttribute(fmha_6warp_tma_multirow_multitile_kernel<HD>,
cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
dim3 grid(1, n_h, batch);
fmha_6warp_tma_multirow_multitile_kernel<HD><<<grid, 192, smem>>>(params);
cudaError_t err = cudaDeviceSynchronize();
if (err != cudaSuccess) {
printf(" CUDA ERROR: %s\n", cudaGetErrorString(err));
return 1;
}
cudaMemcpy(h_o, d_o, total_heads * MAX_T * HD * sizeof(bf16_t), cudaMemcpyDeviceToHost);
cudaMemcpy(h_lse, d_lse, total_heads * MAX_T * sizeof(float), cudaMemcpyDeviceToHost);
int total_bad = 0;
float min_cos = 1.0f;
for (int h = 0; h < total_heads; h++) {
float* o_ref = (float*)calloc(T * HD, sizeof(float));
reference_attention(
h_q + h * MAX_T * HD, h_k + h * s_k * HD, h_v + h * HD * s_k,
o_ref, nullptr, HD, T, s_k, SCALE);
float cs = 0, na = 0, nb = 0;
for (int t = 0; t < T; t++) {
for (int d = 0; d < HD; d++) {
float a = bf16_to_f32_host(h_o[h * MAX_T * HD + t * HD + d]);
float b = o_ref[t * HD + d];
if (fabsf(b) > 1e-4f) { cs += a * b; na += a * a; nb += b * b; }
}
}
cs /= (sqrtf(na) * sqrtf(nb) + 1e-10f);
if (cs < min_cos) min_cos = cs;
free(o_ref);
}
printf(" min_cos=%.8f %s\n", min_cos, min_cos > 0.999f ? "PASS" : "FAIL");
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_lse);
cudaFree(d_tma_k); cudaFree(d_tma_v);
free(h_q); free(h_k); free(h_v); free(h_o); free(h_lse);
free(tma_k_arr); free(tma_v_arr);
return min_cos > 0.999f ? 0 : 1;
}
int main() {
int total_fail = 0;
printf("\n=== 6-warp TMA FMHA multi-row multi-tile HD=%d ===\n", HD);
// Single KV tile (s_k=128, should match single-tile baseline)
for (int T : {1, 4, 32, 128}) {
total_fail += test_single(T, 128);
}
// Multi-tile KV (the whole point of this kernel)
for (int s_k : {256, 384, 512}) {
for (int T : {1, 4, 32}) {
total_fail += test_single(T, s_k);
}
}
// Multi-head + batch
total_fail += test_single(4, 256, 4, 1); // n_h=4
total_fail += test_single(4, 256, 2, 2); // n_h=2, batch=2
printf("\nOverall: %s\n", total_fail == 0 ? "ALL PASSED" : "SOME FAILED");
return total_fail == 0 ? 0 : 1;
}