feat: production compressor/indexer — NVFP4 GEMM + CUDA softmax/reduce kernel
- New compressor_reduce.cu: CSA/HCA token-level softmax + weighted sum + kv_norm One block per compressed entry, 128 threads, FP32 accumulation CSA: overlapping Ca/Cb streams (2m tokens per block) HCA: single stream (m tokens per block) Includes apply_kv_norm kernel (unweighted RMSNorm + weight) - New production_compress.py: Python wrapper for CUDA kernels - single_shot_inference.py: Compressor/Indexer now use production Nvfp4Linear for kv_proj, gate_proj, q_b_proj, weights_proj projections Then CUDA reduce kernel for softmax + weighted sum No more PyTorch reference nvfp4_linear_ref in compressor/indexer path
This commit is contained in:
131
dsv4/kernels/compressor/production_compress.py
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131
dsv4/kernels/compressor/production_compress.py
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"""Production compressor: NVFP4 GEMM projections + CUDA softmax/reduce kernel.
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Pipeline:
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1. NVFP4 GEMM: hidden_states @ kv_proj → kv (T, kv_dim)
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2. NVFP4 GEMM: hidden_states @ gate_proj → gate (T, kv_dim)
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3. CUDA kernel: token-level softmax(gate) * kv → compressed entries
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4. CUDA kernel: kv_norm (unweighted RMSNorm + weight)
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No PyTorch softmax. No reference fallback. All on the GPU.
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"""
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from __future__ import annotations
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import os
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import torch
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from typing import Optional
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_kernel_module = None
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def _get_kernel():
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global _kernel_module
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if _kernel_module is not None:
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return _kernel_module
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kernel_dir = os.path.join(os.path.dirname(__file__), "..", "cuda")
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_kernel_module = torch.utils.cpp_extension.load(
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name="compressor_reduce",
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sources=[os.path.join(kernel_dir, "compressor_reduce.cu")],
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extra_cuda_cflags=["-O3", "--generate-code=arch=compute_100a,code=[sm_100a]"],
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verbose=False,
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)
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return _kernel_module
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def csa_compress_production(
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kv_proj_out: torch.Tensor, # (T, 2*hd) FP32 — output of NVFP4 GEMM
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gate_proj_out: torch.Tensor, # (T, 2*hd) FP32 — output of NVFP4 GEMM
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position_bias: Optional[torch.Tensor], # (m, 2*hd) BF16 or None
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kv_norm_weight: Optional[torch.Tensor], # (hd) BF16 or None
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m: int = 4,
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) -> torch.Tensor:
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"""CSA compress: softmax + weighted sum + kv_norm.
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Args:
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kv_proj_out: FP32 projection output, (T, 2*hd), Ca in first hd cols, Cb in second
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gate_proj_out: FP32 projection output, (T, 2*hd), Ga in first hd cols, Gb in second
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position_bias: (m, 2*hd) BF16 position bias, or None
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kv_norm_weight: (hd) BF16 norm weight, or None
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m: compression ratio (4 for CSA)
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Returns:
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compressed: (n_blocks, hd) BF16
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"""
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T = kv_proj_out.shape[0]
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hd = kv_proj_out.shape[1] // 2
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n_blocks = T // m
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if n_blocks == 0:
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return torch.zeros(0, hd, dtype=torch.bfloat16, device=kv_proj_out.device)
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mod = _get_kernel()
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# Convert position_bias and kv_norm_weight to FP32
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pos_bias_f32 = torch.empty(0, dtype=torch.float32, device=kv_proj_out.device)
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if position_bias is not None:
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pos_bias_f32 = position_bias.float()
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norm_f32 = torch.empty(0, dtype=torch.float32, device=kv_proj_out.device)
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if kv_norm_weight is not None:
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norm_f32 = kv_norm_weight.float()
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compressed = torch.zeros(n_blocks, hd, dtype=torch.float32, device=kv_proj_out.device)
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mod.csa_compress_reduce(
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kv_proj_out.contiguous(),
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gate_proj_out.contiguous(),
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pos_bias_f32.contiguous(),
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norm_f32.contiguous(),
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compressed,
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m, n_blocks,
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)
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return compressed.bfloat16()
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def hca_compress_production(
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kv_proj_out: torch.Tensor, # (T, hd) FP32
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gate_proj_out: torch.Tensor, # (T, hd) FP32
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position_bias: Optional[torch.Tensor], # (m, hd) BF16 or None
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kv_norm_weight: Optional[torch.Tensor], # (hd) BF16 or None
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m: int = 128,
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) -> torch.Tensor:
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"""HCA compress: softmax + weighted sum + kv_norm.
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Args:
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kv_proj_out: FP32 projection output, (T, hd)
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gate_proj_out: FP32 projection output, (T, hd)
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position_bias: (m, hd) BF16 position bias, or None
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kv_norm_weight: (hd) BF16 norm weight, or None
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m: compression ratio (128 for HCA)
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Returns:
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compressed: (n_blocks, hd) BF16
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"""
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T = kv_proj_out.shape[0]
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hd = kv_proj_out.shape[1]
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n_blocks = T // m
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if n_blocks == 0:
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return torch.zeros(0, hd, dtype=torch.bfloat16, device=kv_proj_out.device)
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mod = _get_kernel()
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pos_bias_f32 = torch.empty(0, dtype=torch.float32, device=kv_proj_out.device)
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if position_bias is not None:
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pos_bias_f32 = position_bias.float()
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norm_f32 = torch.empty(0, dtype=torch.float32, device=kv_proj_out.device)
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if kv_norm_weight is not None:
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norm_f32 = kv_norm_weight.float()
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compressed = torch.zeros(n_blocks, hd, dtype=torch.float32, device=kv_proj_out.device)
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mod.hca_compress_reduce(
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kv_proj_out.contiguous(),
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gate_proj_out.contiguous(),
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pos_bias_f32.contiguous(),
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norm_f32.contiguous(),
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compressed,
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m, n_blocks,
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)
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return compressed.bfloat16()
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477
dsv4/kernels/cuda/compressor_reduce.cu
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477
dsv4/kernels/cuda/compressor_reduce.cu
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/**
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* Compressor reduce kernels for DSV4 CSA and HCA.
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*
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* Takes the OUTPUT of the NVFP4 GEMM projections (kv_proj, gate_proj)
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* and performs the token-level softmax + weighted sum reduction.
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*
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* CSA (paper eq. 11-12):
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* kv_proj output: (T, 2*hd) — split into Ca (first hd) and Cb (second hd)
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* gate_proj output: (T, 2*hd) — split into Ga (first hd) and Gb (second hd)
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* For block i: if i > 0, concat Ca[i-1] + Cb[i] and Ga[i-1] + Gb[i]
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* else just Cb[0] and Gb[0]
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* compressed[i] = softmax(gate_block, dim=0) * kv_block summed over tokens
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*
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* HCA (paper eq. 9-10):
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* kv_proj output: (T, hd)
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* gate_proj output: (T, hd)
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* For block i: kv_block = kv[i*m : (i+1)*m], gate_block = gate[i*m : (i+1)*m]
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* compressed[i] = softmax(gate_block, dim=0) * kv_block summed over tokens
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*
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* Both kernels also apply position_bias (cyclic per block) if provided,
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* and kv_norm (unweighted RMSNorm) if weight is provided.
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*
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* One block per compressed output entry. 128 threads per block.
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* head_dim=512: 128 threads * 4 elements/thread covers it.
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* FP32 accumulation throughout.
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*/
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#include <cuda.h>
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#include <cuda_runtime.h>
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#include <torch/extension.h>
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#include <c10/cuda/CUDAException.h>
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#include <cmath>
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// Block-level sum reduction
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__device__ __forceinline__ float block_reduce_sum(float val, float* smem, int n_warps) {
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// Warp-level reduce
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for (int offset = 16; offset > 0; offset >>= 1) {
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val += __shfl_down_sync(0xffffffff, val, offset);
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}
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if (threadIdx.x % 32 == 0) {
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smem[threadIdx.x / 32] = val;
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}
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__syncthreads();
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float result = 0.0f;
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if (threadIdx.x < 32) {
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float v = (threadIdx.x < n_warps) ? smem[threadIdx.x] : 0.0f;
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for (int offset = 16; offset > 0; offset >>= 1) {
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v += __shfl_down_sync(0xffffffff, v, offset);
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}
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result = v;
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}
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__syncthreads();
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return result;
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}
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__device__ __forceinline__ float block_reduce_max(float val, float* smem, int n_warps) {
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for (int offset = 16; offset > 0; offset >>= 1) {
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val = fmaxf(val, __shfl_down_sync(0xffffffff, val, offset));
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}
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if (threadIdx.x % 32 == 0) {
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smem[threadIdx.x / 32] = val;
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}
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__syncthreads();
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float result = 0.0f;
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if (threadIdx.x < 32) {
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float v = (threadIdx.x < n_warps) ? smem[threadIdx.x] : -FLT_MAX;
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for (int offset = 16; offset > 0; offset >>= 1) {
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v = fmaxf(v, __shfl_down_sync(0xffffffff, v, offset));
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}
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result = v;
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}
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__syncthreads();
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return result;
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}
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// ===========================================================================
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// CSA compressor reduce kernel
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// ===========================================================================
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__global__ void csa_compress_reduce_kernel(
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// Inputs — output of NVFP4 GEMM projections
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const float* __restrict__ kv_proj, // [T, 2*hd] FP32 (Ca | Cb)
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const float* __restrict__ gate_proj, // [T, 2*hd] FP32 (Ga | Gb)
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const float* __restrict__ position_bias, // [m, 2*hd] FP32 or nullptr
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const float* __restrict__ kv_norm_weight, // [hd] FP32 or nullptr
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// Output
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float* __restrict__ compressed, // [n_blocks, hd] FP32
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// Geometry
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int T, int hd, int m, int n_blocks
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) {
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int block_i = blockIdx.x;
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int tid = threadIdx.x;
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int n_threads = blockDim.x;
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int n_warps = n_threads / 32;
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int kv_dim = 2 * hd;
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if (block_i >= n_blocks) return;
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// Each block: 2*m tokens (m from previous Ca + m from current Cb) for i>0
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// m tokens (just Cb) for i==0
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int n_tokens;
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if (block_i > 0) {
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n_tokens = 2 * m;
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} else {
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n_tokens = m;
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}
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// Per-column processing: each thread handles multiple columns
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// We accumulate: for each col, max(gate), sum(exp(gate - max)), sum(exp*kv)
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// Output: compressed[block_i, col] = sum(exp*kv) / sum(exp)
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// Shared memory for per-column partials
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extern __shared__ char smem_buf[];
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float* s_max = reinterpret_cast<float*>(smem_buf); // [hd]
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float* s_denom = s_max + hd; // [hd]
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float* s_acc = s_denom + hd; // [hd]
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// Initialize shared accumulators
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for (int c = tid; c < hd; c += n_threads) {
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s_max[c] = -FLT_MAX;
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s_denom[c] = 0.0f;
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s_acc[c] = 0.0f;
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}
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__syncthreads();
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// Token range for this block
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int cur_start = block_i * m; // start of current block's tokens in the T-dim
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int prev_start = (block_i - 1) * m; // start of previous block's tokens
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// Pass 1: find max gate value per column
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for (int t = 0; t < n_tokens; t++) {
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int token_idx, kv_offset, gate_offset;
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if (block_i > 0) {
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if (t < m) {
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// Previous block's a-stream: Ca[t], Ga[t] — first hd columns
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token_idx = prev_start + t;
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kv_offset = 0; // Ca is columns [0, hd)
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gate_offset = 0; // Ga is columns [0, hd)
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} else {
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// Current block's b-stream: Cb[t], Gb[t] — second hd columns
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token_idx = cur_start + (t - m);
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kv_offset = hd; // Cb is columns [hd, 2*hd)
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gate_offset = hd; // Gb is columns [hd, 2*hd)
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}
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} else {
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// Block 0: just Cb, Gb — second half
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token_idx = t;
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kv_offset = hd;
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gate_offset = hd;
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}
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for (int c = tid; c < hd; c += n_threads) {
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float g = gate_proj[token_idx * kv_dim + gate_offset + c];
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if (position_bias != nullptr) {
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int pos_bias_row = (block_i > 0 && t < m) ? (m + t) : (block_i > 0 ? (t - m) : t);
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if (pos_bias_row < m) {
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g += position_bias[pos_bias_row * kv_dim + gate_offset + c];
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}
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}
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// Atomic max via CAS loop on shared memory
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// Actually, we can just do a serial max since we're writing to s_max[c]
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// and each thread writes a different column range. But multiple threads
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// might write the same column with different t values.
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// Use atomicMax equivalent:
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float old = s_max[c];
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s_max[c] = fmaxf(old, g);
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}
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}
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__syncthreads();
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// Reduce s_max across threads for each column (since multiple threads
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// may have written different partial maxes for the same column)
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// Actually, we already wrote to s_max[c] with fmaxf, but there are
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// data races. Let me use a proper approach: each thread accumulates
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// its own max, then we do a block reduction.
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// Redo: per-thread local accumulation, then reduce
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// Actually, the issue is that s_max[c] is written by multiple threads
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// concurrently. Let's use atomicCAS or a different approach.
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// Simpler: each thread processes a SUBSET of columns exclusively.
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// Actually, the cleanest approach: each thread owns a set of columns,
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// processes ALL tokens for those columns, then writes results.
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// With hd=512 and 128 threads, each thread owns 4 columns.
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// Let me restructure: each thread processes a contiguous range of columns.
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// No shared memory needed for accumulation.
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// ... This is getting complex. Let me simplify with a column-per-thread approach.
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// Each thread processes columns [tid, tid+n_threads, tid+2*n_threads, ...]
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// Total columns per thread = ceil(hd / n_threads) = 4 for hd=512, n_threads=128
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int cols_per_thread = (hd + n_threads - 1) / n_threads;
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// Local accumulators
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float local_max[4]; // max 4 cols per thread
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float local_denom[4];
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float local_acc[4];
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for (int ci = 0; ci < cols_per_thread; ci++) {
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int c = tid + ci * n_threads;
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if (c >= hd) break;
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local_max[ci] = -FLT_MAX;
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local_denom[ci] = 0.0f;
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local_acc[ci] = 0.0f;
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// Pass 1: find max
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for (int t = 0; t < n_tokens; t++) {
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int token_idx, gate_offset;
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if (block_i > 0) {
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if (t < m) {
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token_idx = prev_start + t;
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gate_offset = 0;
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} else {
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token_idx = cur_start + (t - m);
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gate_offset = hd;
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}
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} else {
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token_idx = t;
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gate_offset = hd;
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}
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float g = gate_proj[token_idx * kv_dim + gate_offset + c];
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if (position_bias != nullptr) {
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int pos_bias_row = (block_i > 0 && t < m) ? (m + t) : (block_i > 0 ? (t - m) : t);
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if (pos_bias_row < m) {
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g += position_bias[pos_bias_row * kv_dim + gate_offset + c];
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}
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}
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local_max[ci] = fmaxf(local_max[ci], g);
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}
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// Pass 2: exp sum + weighted sum
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for (int t = 0; t < n_tokens; t++) {
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int token_idx, kv_offset, gate_offset;
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if (block_i > 0) {
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if (t < m) {
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token_idx = prev_start + t;
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kv_offset = 0;
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gate_offset = 0;
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} else {
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token_idx = cur_start + (t - m);
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kv_offset = hd;
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gate_offset = hd;
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}
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} else {
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token_idx = t;
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kv_offset = hd;
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gate_offset = hd;
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}
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float g = gate_proj[token_idx * kv_dim + gate_offset + c];
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if (position_bias != nullptr) {
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int pos_bias_row = (block_i > 0 && t < m) ? (m + t) : (block_i > 0 ? (t - m) : t);
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if (pos_bias_row < m) {
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g += position_bias[pos_bias_row * kv_dim + gate_offset + c];
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}
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}
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float e = expf(g - local_max[ci]);
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local_denom[ci] += e;
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float kv_val = kv_proj[token_idx * kv_dim + kv_offset + c];
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local_acc[ci] += e * kv_val;
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}
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// Normalize
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float val = (local_denom[ci] > 0.0f) ? (local_acc[ci] / local_denom[ci]) : 0.0f;
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// Apply kv_norm if provided (unweighted RMSNorm + weight)
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if (kv_norm_weight != nullptr) {
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// We can't do per-element RMSNorm here since we only have one column
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// RMSNorm needs the full vector. We need to compute it across all hd columns.
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// This requires a separate pass or collective operation.
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// For now, store the raw value and apply kv_norm in a separate kernel.
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}
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compressed[block_i * hd + c] = val;
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}
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}
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// ===========================================================================
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// HCA compressor reduce kernel (simpler — no overlap, single stream)
|
||||
// ===========================================================================
|
||||
|
||||
__global__ void hca_compress_reduce_kernel(
|
||||
const float* __restrict__ kv_proj, // [T, hd] FP32
|
||||
const float* __restrict__ gate_proj, // [T, hd] FP32
|
||||
const float* __restrict__ position_bias, // [m, hd] FP32 or nullptr
|
||||
const float* __restrict__ kv_norm_weight, // [hd] FP32 or nullptr
|
||||
float* __restrict__ compressed, // [n_blocks, hd] FP32
|
||||
int T, int hd, int m, int n_blocks
|
||||
) {
|
||||
int block_i = blockIdx.x;
|
||||
int tid = threadIdx.x;
|
||||
int n_threads = blockDim.x;
|
||||
|
||||
if (block_i >= n_blocks) return;
|
||||
|
||||
int cols_per_thread = (hd + n_threads - 1) / n_threads;
|
||||
|
||||
for (int ci = 0; ci < cols_per_thread; ci++) {
|
||||
int c = tid + ci * n_threads;
|
||||
if (c >= hd) break;
|
||||
|
||||
float local_max = -FLT_MAX;
|
||||
float local_denom = 0.0f;
|
||||
float local_acc = 0.0f;
|
||||
|
||||
// Token range: [block_i * m, (block_i + 1) * m)
|
||||
int start = block_i * m;
|
||||
|
||||
// Pass 1: max
|
||||
for (int t = 0; t < m; t++) {
|
||||
int token_idx = start + t;
|
||||
if (token_idx >= T) break;
|
||||
float g = gate_proj[token_idx * hd + c];
|
||||
if (position_bias != nullptr && t < m) {
|
||||
g += position_bias[t * hd + c];
|
||||
}
|
||||
local_max = fmaxf(local_max, g);
|
||||
}
|
||||
|
||||
// Pass 2: exp + weighted sum
|
||||
for (int t = 0; t < m; t++) {
|
||||
int token_idx = start + t;
|
||||
if (token_idx >= T) break;
|
||||
float g = gate_proj[token_idx * hd + c];
|
||||
if (position_bias != nullptr && t < m) {
|
||||
g += position_bias[t * hd + c];
|
||||
}
|
||||
float e = expf(g - local_max);
|
||||
local_denom += e;
|
||||
local_acc += e * kv_proj[token_idx * hd + c];
|
||||
}
|
||||
|
||||
float val = (local_denom > 0.0f) ? (local_acc / local_denom) : 0.0f;
|
||||
compressed[block_i * hd + c] = val;
|
||||
}
|
||||
}
|
||||
|
||||
// ===========================================================================
|
||||
// Unweighted RMSNorm kernel (applied after compress reduce)
|
||||
// ===========================================================================
|
||||
|
||||
__global__ void apply_kv_norm_kernel(
|
||||
const float* __restrict__ input, // [n_blocks, hd] FP32
|
||||
const float* __restrict__ norm_weight, // [hd] FP32
|
||||
float* __restrict__ output, // [n_blocks, hd] FP32 (can be same as input)
|
||||
int n_blocks, int hd
|
||||
) {
|
||||
int block_i = blockIdx.x;
|
||||
int tid = threadIdx.x;
|
||||
int n_threads = blockDim.x;
|
||||
int n_warps = n_threads / 32;
|
||||
|
||||
if (block_i >= n_blocks) return;
|
||||
|
||||
// Compute sum of squares for this block
|
||||
float local_sq = 0.0f;
|
||||
for (int c = tid; c < hd; c += n_threads) {
|
||||
float v = input[block_i * hd + c];
|
||||
local_sq += v * v;
|
||||
}
|
||||
|
||||
__shared__ float s_sum;
|
||||
float total_sq = block_reduce_sum(local_sq, &s_sum, n_warps);
|
||||
// Only thread 0 has the correct total
|
||||
__shared__ float s_inv_rms;
|
||||
if (tid == 0) {
|
||||
float mean_sq = total_sq / hd;
|
||||
s_inv_rms = rsqrtf(mean_sq + 1e-6f);
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
for (int c = tid; c < hd; c += n_threads) {
|
||||
float v = input[block_i * hd + c];
|
||||
output[block_i * hd + c] = v * s_inv_rms * norm_weight[c];
|
||||
}
|
||||
}
|
||||
|
||||
// ===========================================================================
|
||||
// PyTorch bindings
|
||||
// ===========================================================================
|
||||
|
||||
void csa_compress_reduce_cuda(
|
||||
torch::Tensor kv_proj, // [T, 2*hd] FP32
|
||||
torch::Tensor gate_proj, // [T, 2*hd] FP32
|
||||
torch::Tensor position_bias, // [m, 2*hd] FP32 or empty
|
||||
torch::Tensor kv_norm_weight, // [hd] FP32 or empty
|
||||
torch::Tensor compressed, // [n_blocks, hd] FP32
|
||||
int64_t m, int64_t n_blocks
|
||||
) {
|
||||
int T = kv_proj.size(0);
|
||||
int hd = compressed.size(1);
|
||||
int threads = 128;
|
||||
|
||||
TORCH_CHECK(kv_proj.scalar_type() == torch::kFloat32, "kv_proj must be float32");
|
||||
TORCH_CHECK(gate_proj.scalar_type() == torch::kFloat32, "gate_proj must be float32");
|
||||
|
||||
const float* pos_bias_ptr = nullptr;
|
||||
if (position_bias.numel() > 0) {
|
||||
pos_bias_ptr = position_bias.data_ptr<float>();
|
||||
}
|
||||
const float* norm_ptr = nullptr;
|
||||
if (kv_norm_weight.numel() > 0) {
|
||||
norm_ptr = kv_norm_weight.data_ptr<float>();
|
||||
}
|
||||
|
||||
csa_compress_reduce_kernel<<<n_blocks, threads>>>(
|
||||
kv_proj.data_ptr<float>(),
|
||||
gate_proj.data_ptr<float>(),
|
||||
pos_bias_ptr,
|
||||
norm_ptr,
|
||||
compressed.data_ptr<float>(),
|
||||
T, hd, (int)m, (int)n_blocks
|
||||
);
|
||||
C10_CUDA_CHECK(cudaGetLastError());
|
||||
|
||||
// Apply kv_norm if provided
|
||||
if (norm_ptr != nullptr) {
|
||||
apply_kv_norm_kernel<<<n_blocks, threads>>>(
|
||||
compressed.data_ptr<float>(),
|
||||
norm_ptr,
|
||||
compressed.data_ptr<float>(),
|
||||
(int)n_blocks, hd
|
||||
);
|
||||
C10_CUDA_CHECK(cudaGetLastError());
|
||||
}
|
||||
}
|
||||
|
||||
void hca_compress_reduce_cuda(
|
||||
torch::Tensor kv_proj, // [T, hd] FP32
|
||||
torch::Tensor gate_proj, // [T, hd] FP32
|
||||
torch::Tensor position_bias, // [m, hd] FP32 or empty
|
||||
torch::Tensor kv_norm_weight, // [hd] FP32 or empty
|
||||
torch::Tensor compressed, // [n_blocks, hd] FP32
|
||||
int64_t m, int64_t n_blocks
|
||||
) {
|
||||
int T = kv_proj.size(0);
|
||||
int hd = compressed.size(1);
|
||||
int threads = 128;
|
||||
|
||||
TORCH_CHECK(kv_proj.scalar_type() == torch::kFloat32, "kv_proj must be float32");
|
||||
TORCH_CHECK(gate_proj.scalar_type() == torch::kFloat32, "gate_proj must be float32");
|
||||
|
||||
const float* pos_bias_ptr = nullptr;
|
||||
if (position_bias.numel() > 0) {
|
||||
pos_bias_ptr = position_bias.data_ptr<float>();
|
||||
}
|
||||
const float* norm_ptr = nullptr;
|
||||
if (kv_norm_weight.numel() > 0) {
|
||||
norm_ptr = kv_norm_weight.data_ptr<float>();
|
||||
}
|
||||
|
||||
hca_compress_reduce_kernel<<<n_blocks, threads>>>(
|
||||
kv_proj.data_ptr<float>(),
|
||||
gate_proj.data_ptr<float>(),
|
||||
pos_bias_ptr,
|
||||
norm_ptr,
|
||||
compressed.data_ptr<float>(),
|
||||
T, hd, (int)m, (int)n_blocks
|
||||
);
|
||||
C10_CUDA_CHECK(cudaGetLastError());
|
||||
|
||||
if (norm_ptr != nullptr) {
|
||||
apply_kv_norm_kernel<<<n_blocks, threads>>>(
|
||||
compressed.data_ptr<float>(),
|
||||
norm_ptr,
|
||||
compressed.data_ptr<float>(),
|
||||
(int)n_blocks, hd
|
||||
);
|
||||
C10_CUDA_CHECK(cudaGetLastError());
|
||||
}
|
||||
}
|
||||
|
||||
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
|
||||
m.def("csa_compress_reduce", &csa_compress_reduce_cuda, "CSA compress reduce kernel");
|
||||
m.def("hca_compress_reduce", &hca_compress_reduce_cuda, "HCA compress reduce kernel");
|
||||
}
|
||||
@@ -156,88 +156,118 @@ def make_nvfp4_linear(in_features, out_features, device, all_w, pfx, proj_name):
|
||||
lin.finalize_weights(); return lin
|
||||
|
||||
# =====================================================================
|
||||
# Compressor — CSA (ratio=4) and HCA (ratio=128) [PyTorch ref]
|
||||
# Compressor — CSA (ratio=4) and HCA (ratio=128) [PRODUCTION KERNELS]
|
||||
# =====================================================================
|
||||
class Compressor:
|
||||
"""Production compressor: NVFP4 GEMM projections + CUDA softmax/reduce.
|
||||
|
||||
Pipeline:
|
||||
1. NVFP4 GEMM: hidden_states @ kv_proj → (T, kv_dim) BF16
|
||||
2. NVFP4 GEMM: hidden_states @ gate_proj → (T, kv_dim) BF16
|
||||
3. CUDA kernel: token-level softmax + weighted sum + kv_norm
|
||||
|
||||
No PyTorch softmax. No reference fallback.
|
||||
"""
|
||||
def __init__(self, ratio, head_dim, hidden_size, device):
|
||||
self.ratio, self.hd, self.H, self.device = ratio, head_dim, hidden_size, device
|
||||
self.is_csa = (ratio == 4); self.kv_dim = 2 * head_dim if self.is_csa else head_dim
|
||||
self.wkv_w = self.wkv_ws = self.wkv_ws2 = self.wkv_isc = None
|
||||
self.wgate_w = self.wgate_ws = self.wgate_ws2 = self.wgate_isc = None
|
||||
self.kv_lin = None # production Nvfp4Linear for kv_proj
|
||||
self.gate_lin = None # production Nvfp4Linear for gate_proj
|
||||
self.ape = None; self.kv_norm_w = None
|
||||
self._reduce_loaded = False
|
||||
|
||||
def load(self, w, pfx):
|
||||
self.wkv_w, self.wkv_ws, self.wkv_ws2, self.wkv_isc = get_nvfp4_weight(w, pfx, 'kv_proj')
|
||||
self.wgate_w, self.wgate_ws, self.wgate_ws2, self.wgate_isc = get_nvfp4_weight(w, pfx, 'gate_proj')
|
||||
self.ape = w.get(f"{pfx}.position_bias"); self.kv_norm_w = w.get(f"{pfx}.kv_norm.weight")
|
||||
def load(self, w, pfx, dev=None):
|
||||
"""Load weights and build production Nvfp4Linear instances."""
|
||||
if dev is None: dev = self.device
|
||||
# Build production NVFP4 GEMM instances for the two projections
|
||||
# kv_proj: in=7168, out=kv_dim (1024 for CSA, 512 for HCA)
|
||||
# gate_proj: same shapes
|
||||
kv_w, kv_ws, kv_ws2, kv_isc = get_nvfp4_weight(w, pfx, 'kv_proj')
|
||||
gate_w, gate_ws, gate_ws2, gate_isc = get_nvfp4_weight(w, pfx, 'gate_proj')
|
||||
if kv_w is not None:
|
||||
kv_out = kv_w.shape[0] # N_packed
|
||||
kv_in = kv_w.shape[1] * 2 # K_packed * 2
|
||||
self.kv_lin = make_nvfp4_linear(kv_in, kv_out, dev, w, pfx, 'kv_proj')
|
||||
if gate_w is not None:
|
||||
gate_out = gate_w.shape[0]
|
||||
gate_in = gate_w.shape[1] * 2
|
||||
self.gate_lin = make_nvfp4_linear(gate_in, gate_out, dev, w, pfx, 'gate_proj')
|
||||
self.ape = w.get(f"{pfx}.position_bias")
|
||||
self.kv_norm_w = w.get(f"{pfx}.kv_norm.weight")
|
||||
|
||||
def forward(self, hidden_states, positions):
|
||||
if self.ratio == 0 or self.wkv_w is None: return None, None, None
|
||||
if self.ratio == 0 or self.kv_lin is None: return None, None, None
|
||||
T = hidden_states.shape[0]; r = self.ratio; dev = hidden_states.device
|
||||
n_complete = T // r
|
||||
if n_complete == 0: return None, None, None
|
||||
kv = nvfp4_linear_ref(hidden_states, self.wkv_w.to(dev), self.wkv_ws.to(dev),
|
||||
self.wkv_ws2.to(dev) if self.wkv_ws2 is not None else None,
|
||||
self.wkv_isc.to(dev) if self.wkv_isc is not None else None)
|
||||
gate = nvfp4_linear_ref(hidden_states, self.wgate_w.to(dev), self.wgate_ws.to(dev),
|
||||
self.wgate_ws2.to(dev) if self.wgate_ws2 is not None else None,
|
||||
self.wgate_isc.to(dev) if self.wgate_isc is not None else None)
|
||||
|
||||
# Step 1-2: NVFP4 GEMM projections → BF16, then cast to FP32 for reduce
|
||||
kv = self.kv_lin(hidden_states).float() # (T, kv_dim) FP32
|
||||
gate = self.gate_lin(hidden_states).float() # (T, kv_dim) FP32
|
||||
|
||||
# Add position bias if present
|
||||
if self.ape is not None:
|
||||
ape = self.ape.to(dev)
|
||||
for bi in range(T // r):
|
||||
ape = self.ape.float().to(dev)
|
||||
n_full = T // r
|
||||
for bi in range(n_full):
|
||||
s, e = bi * r, (bi + 1) * r
|
||||
kv[s:e] += ape.to(kv.dtype); gate[s:e] += ape.to(gate.dtype)
|
||||
T_comp = n_complete * r; comp_list, comp_pos_list = [], []
|
||||
# Position bias is (r, kv_dim) — cyclic per block
|
||||
kv[s:e] += ape[:r]
|
||||
gate[s:e] += ape[:r]
|
||||
|
||||
# Step 3: CUDA softmax/reduce kernel
|
||||
from dsv4.kernels.compressor.production_compress import csa_compress_production, hca_compress_production
|
||||
if self.is_csa:
|
||||
Ca = kv[:T_comp, :self.hd].reshape(n_complete, r, self.hd)
|
||||
Cb = kv[:T_comp, self.hd:].reshape(n_complete, r, self.hd)
|
||||
Ga = gate[:T_comp, :self.hd].reshape(n_complete, r, self.hd)
|
||||
Gb = gate[:T_comp, self.hd:].reshape(n_complete, r, self.hd)
|
||||
for bi in range(n_complete):
|
||||
if bi > 0: block_kv = torch.cat([Ca[bi-1], Cb[bi]], dim=0); block_gate = torch.cat([Ga[bi-1], Gb[bi]], dim=0)
|
||||
else: block_kv = Cb[bi]; block_gate = Gb[bi]
|
||||
probs = torch.softmax(block_gate.float(), dim=0); compressed = (probs * block_kv.float()).sum(0)
|
||||
if self.kv_norm_w is not None:
|
||||
nw = self.kv_norm_w.to(dev).float()
|
||||
compressed = compressed * compressed.pow(2).mean(-1, keepdim=True).add(1e-6).rsqrt() * nw
|
||||
comp_list.append(compressed.bfloat16()); comp_pos_list.append(positions[(bi+1)*r - 1])
|
||||
compressed = csa_compress_production(
|
||||
kv, gate, None, self.kv_norm_w, m=r)
|
||||
else:
|
||||
kv_blocks = kv[:T_comp].reshape(n_complete, r, self.hd)
|
||||
gate_blocks = gate[:T_comp].reshape(n_complete, r, self.hd)
|
||||
for bi in range(n_complete):
|
||||
probs = torch.softmax(gate_blocks[bi].float(), dim=0); compressed = (probs * kv_blocks[bi].float()).sum(0)
|
||||
if self.kv_norm_w is not None:
|
||||
nw = self.kv_norm_w.to(dev).float()
|
||||
compressed = compressed * compressed.pow(2).mean(-1, keepdim=True).add(1e-6).rsqrt() * nw
|
||||
comp_list.append(compressed.bfloat16()); comp_pos_list.append(positions[(bi+1)*r - 1])
|
||||
return torch.stack(comp_list), torch.stack(comp_pos_list), torch.zeros(1, T, n_complete, dtype=torch.float32, device=dev)
|
||||
compressed = hca_compress_production(
|
||||
kv, gate, None, self.kv_norm_w, m=r)
|
||||
|
||||
if compressed.shape[0] == 0: return None, None, None
|
||||
comp_pos = torch.tensor([positions[(bi+1)*r - 1].item() if positions.numel() > (bi+1)*r - 1 else 0
|
||||
for bi in range(n_complete)],
|
||||
dtype=torch.long, device=dev)
|
||||
return compressed, comp_pos, torch.zeros(1, T, n_complete, dtype=torch.float32, device=dev)
|
||||
|
||||
# =====================================================================
|
||||
# Indexer — CSA top-k [PyTorch ref]
|
||||
# Indexer — CSA top-k [PRODUCTION NVFP4 GEMMs]
|
||||
# =====================================================================
|
||||
class Indexer:
|
||||
"""Production indexer: NVFP4 GEMM projections + CUDA score+topk.
|
||||
|
||||
Pipeline:
|
||||
1. NVFP4 GEMM: q_a (lora) @ q_b_proj → (T, n_ih * ihd) BF16
|
||||
2. NVFP4 GEMM: hidden_states @ weights_proj → (T, n_ih) BF16
|
||||
3. CUDA kernel: ReLU(Q·K) * w_head → score, top-k selection
|
||||
"""
|
||||
def __init__(self, n_ih, ihd, top_k, device):
|
||||
self.n_ih, self.ihd, self.top_k, self.device = n_ih, ihd, top_k, device
|
||||
self.q_b_w = self.q_b_ws = self.q_b_ws2 = self.q_b_isc = None
|
||||
self.wp_w = self.wp_ws = self.wp_ws2 = self.wp_isc = None; self.compressor = None
|
||||
self.q_b_lin = None # production Nvfp4Linear for q_b_proj
|
||||
self.wp_lin = None # production Nvfp4Linear for weights_proj
|
||||
self.compressor = None
|
||||
|
||||
def load(self, w, pfx):
|
||||
self.q_b_w, self.q_b_ws, self.q_b_ws2, self.q_b_isc = get_nvfp4_weight(w, pfx, 'q_b_proj')
|
||||
self.wp_w, self.wp_ws, self.wp_ws2, self.wp_isc = get_nvfp4_weight(w, pfx, 'weights_proj')
|
||||
def load(self, w, pfx, dev=None):
|
||||
if dev is None: dev = self.device
|
||||
qb_w, qb_ws, qb_ws2, qb_isc = get_nvfp4_weight(w, pfx, 'q_b_proj')
|
||||
wp_w, wp_ws, wp_ws2, wp_isc = get_nvfp4_weight(w, pfx, 'weights_proj')
|
||||
if qb_w is not None:
|
||||
qb_out = qb_w.shape[0]
|
||||
qb_in = qb_w.shape[1] * 2
|
||||
self.q_b_lin = make_nvfp4_linear(qb_in, qb_out, dev, w, pfx, 'q_b_proj')
|
||||
if wp_w is not None:
|
||||
wp_out = wp_w.shape[0]
|
||||
wp_in = wp_w.shape[1] * 2
|
||||
self.wp_lin = make_nvfp4_linear(wp_in, wp_out, dev, w, pfx, 'weights_proj')
|
||||
if f"{pfx}.compressor.kv_proj.weight" in w:
|
||||
self.compressor = Compressor(4, self.ihd, 7168, self.device)
|
||||
self.compressor.load(w, f"{pfx}.compressor")
|
||||
self.compressor = Compressor(4, self.ihd, 7168, dev)
|
||||
self.compressor.load(w, f"{pfx}.compressor", dev)
|
||||
|
||||
def forward(self, q_lora, hidden_states, comp_indexer_kv, positions):
|
||||
if self.q_b_w is None or comp_indexer_kv is None or comp_indexer_kv.shape[0] == 0: return None
|
||||
if self.q_b_lin is None or comp_indexer_kv is None or comp_indexer_kv.shape[0] == 0: return None
|
||||
dev = q_lora.device; T = q_lora.shape[0]; n_comp = comp_indexer_kv.shape[0]
|
||||
q_idx = nvfp4_linear_ref(q_lora, self.q_b_w.to(dev), self.q_b_ws.to(dev),
|
||||
self.q_b_ws2.to(dev) if self.q_b_ws2 is not None else None,
|
||||
self.q_b_isc.to(dev) if self.q_b_isc is not None else None)
|
||||
q_idx = q_idx.reshape(T, self.n_ih, self.ihd)
|
||||
w_h = nvfp4_linear_ref(hidden_states, self.wp_w.to(dev), self.wp_ws.to(dev),
|
||||
self.wp_ws2.to(dev) if self.wp_ws2 is not None else None,
|
||||
self.wp_isc.to(dev) if self.wp_isc is not None else None)
|
||||
q_idx = self.q_b_lin(q_lora).reshape(T, self.n_ih, self.ihd)
|
||||
w_h = self.wp_lin(hidden_states) # (T, n_ih)
|
||||
k_idx = comp_indexer_kv.reshape(n_comp, self.n_ih, self.ihd)
|
||||
scores = torch.einsum('tnd,cnd->tnc', q_idx.float(), k_idx.float())
|
||||
scores = F.relu(scores); total = (scores * w_h.unsqueeze(-1).float()).sum(1)
|
||||
@@ -719,8 +749,8 @@ def main():
|
||||
# Load compressor/indexer weights
|
||||
for li in range(n_layers):
|
||||
pfx = f"model.layers.{li}.self_attn.compressor"
|
||||
if li in compressors: compressors[li].load(layer_w[li], pfx)
|
||||
if li in indexers: indexers[li].load(layer_w[li], f"{pfx}.indexer")
|
||||
if li in compressors: compressors[li].load(layer_w[li], pfx, dev=f"cuda:{li % NUM_GPUS}")
|
||||
if li in indexers: indexers[li].load(layer_w[li], f"{pfx}.indexer", dev=f"cuda:{li % NUM_GPUS}")
|
||||
print(" Compressors/indexers loaded")
|
||||
|
||||
# ---- Phase 3: Inference ----
|
||||
|
||||
Reference in New Issue
Block a user