feat: 6-warp TMA FMHA multi-row kernel + test
This commit is contained in:
306
dsv4/kernels/attention/fmha_6warp_tma_multirow.cuh
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306
dsv4/kernels/attention/fmha_6warp_tma_multirow.cuh
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/**
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* DSV4 FMHA — 6-warp TMA kernel, multi-row softmax (prefill T>1).
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*
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* Based on fmha_6warp_multirow.cuh with TMA async loads for K.
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* Q and V remain direct GMEM loads for now.
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*
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* ==================================================================
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* DESIGN
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* ==================================================================
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*
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* 6-warp CTA: warps 0-3 = softmax, warp 4 = MMA, warp 5 = TMA load.
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* Grid: (1, n_h, batch) — each CTA processes one head of one batch item.
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*
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* TMA pipeline:
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* - K: TMA async load via cp.async.bulk.tensor.2d with mbarrier
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* - Q: direct GMEM load (multi-row, but small enough for warp-stride)
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* - V: direct GMEM load (16×16 sub-tiles)
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* - sTmaBuf: staging area for TMA→canonical conversion
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*
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* Flow:
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* 1. QK GEMM: Q direct + K TMA → S in TMEM
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* 2. Softmax: 2-pass (row_max, exp+sum+P), P in registers
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* 3. PV GEMM: P→sPk + V direct → O in TMEM
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* 4. Epilogue: O from TMEM → normalize → BF16 → GMEM + LSE
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*/
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#pragma once
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#include "fmha_common.cuh"
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#include "fmha_umma_desc.cuh"
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#include "fmha_tma.cuh"
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namespace dsv4::kernels::attention {
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struct FmhaTmaMultiRowParams {
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const bf16_t* __restrict__ q;
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CUtensorMap* __restrict__ tma_k; // K: (s_k, HD) with tile (128, 16)
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const bf16_t* __restrict__ v; // V: direct GMEM (HD, s_k)
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bf16_t* __restrict__ o;
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float* __restrict__ lse;
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int s_k, T;
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float scale;
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int head_dim;
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int q_head_stride, q_batch_stride;
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int k_head_stride, k_batch_stride;
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int v_head_stride, v_batch_stride;
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int o_head_stride, o_batch_stride;
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int lse_head_stride, lse_batch_stride;
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};
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template<int HD, int SK_TILE = 128>
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__global__ void __launch_bounds__(192)
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fmha_6warp_tma_multirow_kernel(FmhaTmaMultiRowParams params) {
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static constexpr int NKT_QK = HD / MMA_K_BF16;
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static constexpr int NKT_PV = SK_TILE / MMA_K_BF16;
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static constexpr int N_NSUB = HD / 16;
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static constexpr int TILE_SZ = 128 * MMA_K_BF16;
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static constexpr int V_SUB_SZ = 16 * MMA_K_BF16;
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static constexpr int TMEM_N = (HD <= 128) ? 128 : 256;
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static constexpr int MAX_ROWS = 128;
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static constexpr int CORES_MN = 128 / 8;
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static constexpr int NUM_READS = SK_TILE / 8;
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static constexpr int TMA_TILE_BYTES = TILE_SZ * sizeof(bf16_t);
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const int head_idx = blockIdx.y;
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const int batch_idx = blockIdx.z;
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const int tid = threadIdx.x;
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const int wid = tid / 32;
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const int lane = tid % 32;
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const bool is_softmax_warp = (wid < 4);
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const bool is_mma_warp = (wid == 4);
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const bool is_load_warp = (wid == 5);
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const int T = params.T;
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const int s_k = params.s_k;
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const float scale = params.scale;
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const bf16_t* __restrict__ q_head = params.q + head_idx * params.q_head_stride + batch_idx * params.q_batch_stride;
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const bf16_t* __restrict__ v_head = params.v + head_idx * params.v_head_stride + batch_idx * params.v_batch_stride;
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bf16_t* __restrict__ o_head = params.o + head_idx * params.o_head_stride + batch_idx * params.o_batch_stride;
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float* __restrict__ lse_head = params.lse ? params.lse + head_idx * params.lse_head_stride + batch_idx * params.lse_batch_stride : nullptr;
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// ================================================================
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// SMEM allocation — 128-byte aligned for TMA
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// ================================================================
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extern __shared__ __align__(128) char sbuf[];
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size_t off = 0;
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uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off += 4;
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off = (off + 127) & ~(size_t)127;
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uint64_t* sMbar = (uint64_t*)(sbuf + off); off += 16;
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off = (off + 127) & ~(size_t)127;
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bf16_t* sTmaBuf = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sQ0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sK0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sPk = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sV = (bf16_t*)(sbuf + off); off += V_SUB_SZ * sizeof(bf16_t);
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float* sRowMax = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
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float* sRowSum = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
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// TMEM alloc + mbarrier init
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if (is_mma_warp) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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if (tid == 0) {
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tma_mbarrier_init((uint32_t)__cvta_generic_to_shared(sMbar), 1);
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asm volatile("fence.mbarrier_init.release.cluster;" ::: "memory");
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}
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__syncthreads();
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uint32_t tb = *sTmemBase;
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const uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(sMbar);
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int phase = 0;
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// Row assignment
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const bool my_warp_active = (T <= 32) ? (wid == 0) : is_softmax_warp;
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const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
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const bool my_row_active = my_warp_active && (my_row < T);
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// ================================================================
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// QK GEMM → S in TMEM
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// ================================================================
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for (int kt = 0; kt < NKT_QK; kt++) {
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// Load Q: direct from GMEM, all T rows
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if (is_load_warp) {
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for (int i = lane; i < TILE_SZ; i += 32) sQ0[i] = 0;
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for (int r = 0; r < T; r++) {
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for (int d = lane; d < MMA_K_BF16; d += 32) {
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int full_d = kt * MMA_K_BF16 + d;
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if (full_d < HD) {
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int ck = d/8, lc = d%8, cm = r/8, lr = r%8;
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sQ0[ck*CORES_MN*64 + cm*64 + lr*8 + lc] = q_head[r * HD + full_d];
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}
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}
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}
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}
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// Load K: TMA async
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if (is_load_warp && lane == 0) {
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tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)params.tma_k,
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mbar_addr, kt * MMA_K_BF16, 0);
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tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
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}
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tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
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__syncthreads();
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// Convert TMA row-major → canonical
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for (int i = tid; i < TILE_SZ; i += 192) sK0[i] = 0;
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for (int i = tid; i < s_k * MMA_K_BF16; i += 192) {
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int r = i / MMA_K_BF16, c = i % MMA_K_BF16;
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int ck = c/8, lc = c%8, tmn = r/8, lr = r%8;
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sK0[ck*CORES_MN*64 + tmn*64 + lr*8 + lc] = sTmaBuf[i];
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}
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__syncthreads();
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// MMA
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if (is_mma_warp) {
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uint32_t idesc = make_idesc(128, 128);
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
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if (tid == 128) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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}
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__syncthreads();
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}
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asm volatile("fence.sc.gpu;" ::: "memory");
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__syncthreads();
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// ================================================================
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// SOFTMAX — 2-pass, P in registers
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// ================================================================
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// Pass 1: row_max
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float my_row_max = -INFINITY;
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if (my_warp_active) {
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for (int n = 0; n < NUM_READS; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (my_row_active) {
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for (int c = 0; c < 8; c++) {
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int col = n * 8 + c;
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if (col < s_k) my_row_max = fmaxf(my_row_max, tmp[c] * scale);
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}
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}
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}
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}
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if (my_row_active) sRowMax[my_row] = my_row_max;
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__syncthreads();
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// Pass 2: exp + sum + P
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float my_p_vals[SK_TILE];
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float my_row_sum = 0.0f;
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if (my_warp_active) {
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float rm = my_row_active ? sRowMax[my_row] : 0.0f;
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for (int n = 0; n < NUM_READS; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (my_row_active) {
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for (int c = 0; c < 8; c++) {
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int col = n * 8 + c;
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if (col < s_k) {
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float p = expf(tmp[c] * scale - rm);
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my_p_vals[col] = p;
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my_row_sum += p;
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}
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}
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}
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}
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}
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if (my_row_active) sRowSum[my_row] = my_row_sum;
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__syncthreads();
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// ================================================================
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// PV GEMM — P→sPk + V direct → O in TMEM
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// ================================================================
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for (int n_sub = 0; n_sub < N_NSUB; n_sub++) {
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int d_base = n_sub * 16;
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for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
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const int col_start = pv_kt * MMA_K_BF16;
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// Zero sPk
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if (is_load_warp) {
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for (int i = lane; i < TILE_SZ; i += 32) sPk[i] = 0;
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}
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__syncthreads();
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// Softmax warps: write P to sPk (all active rows)
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if (my_row_active) {
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for (int c = 0; c < MMA_K_BF16; c++) {
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int gc = col_start + c;
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int ck = c/8, lc = c%8;
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int core_mn = my_row/8, local_r = my_row%8;
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sPk[ck*CORES_MN*64 + core_mn*64 + local_r*8 + lc] = f32_to_bf16(my_p_vals[gc]);
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}
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}
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__syncthreads();
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// Load V sub-tile: direct from GMEM
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if (is_load_warp) {
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for (int i = lane; i < V_SUB_SZ; i += 32) sV[i] = 0;
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for (int dd = lane; dd < 16; dd += 32) {
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for (int lr = 0; lr < MMA_K_BF16; lr++) {
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int r = col_start + lr;
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if (r < s_k && (d_base + dd) < HD) {
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int g_mn = dd/8, g_k = lr/8, llr = dd%8, lc = lr%8;
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sV[g_k*2*64 + g_mn*64 + llr*8 + lc] = v_head[(d_base+dd)*s_k + r];
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}
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}
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}
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}
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__syncthreads();
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// MMA
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if (is_mma_warp) {
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uint32_t idesc_pv = make_idesc(128, 16);
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uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), 128);
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uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
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if (tid == 128) umma_ss_f16(tb + n_sub*16, dp, dv, idesc_pv, pv_kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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}
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__syncthreads();
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}
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}
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asm volatile("fence.sc.gpu;" ::: "memory");
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__syncthreads();
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// ================================================================
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// EPILOGUE — O from TMEM → normalize → GMEM + LSE
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// TMEM loads are warp-collective: MUST be outside my_row_active guard
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// ================================================================
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if (my_warp_active) {
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float rm = my_row_active ? sRowMax[my_row] : 0.0f;
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float rs = my_row_active ? sRowSum[my_row] : 0.0f;
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float inv_rs = my_row_active ? (1.0f / rs) : 0.0f;
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for (int n = 0; n < N_NSUB * 2; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (my_row_active) {
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for (int c = 0; c < 8; c++) {
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int d = n * 8 + c;
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if (d < HD) o_head[my_row * HD + d] = f32_to_bf16(tmp[c] * inv_rs);
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}
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}
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}
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if (my_row_active && lse_head) lse_head[my_row] = logf(rs) + rm;
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}
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__syncthreads();
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if (is_mma_warp) tmem_dealloc(tb, TMEM_N);
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}
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} // namespace
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163
tests/unit/test_fmha_6warp_tma_multirow.cu
Normal file
163
tests/unit/test_fmha_6warp_tma_multirow.cu
Normal file
@@ -0,0 +1,163 @@
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/**
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* Test 6-warp TMA FMHA multi-row kernel (T>1 prefill).
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*/
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#include <cuda_runtime.h>
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#include <cuda.h>
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#include <cstdio>
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#include <cmath>
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#include <cstdlib>
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#include <cstring>
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#ifndef HD_VAL
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#define HD_VAL 64
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#endif
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#include "dsv4/kernels/attention/fmha_common.cuh"
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#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
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#include "dsv4/kernels/attention/fmha_tma.cuh"
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using namespace dsv4::kernels::attention;
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static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
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static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
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constexpr int HD = HD_VAL;
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constexpr int SK = 128;
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constexpr int MAX_T = 128;
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constexpr int MY_MMA_K = 16;
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constexpr int TILE_SZ = 128 * MY_MMA_K;
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#include "dsv4/kernels/attention/fmha_6warp_tma_multirow.cuh"
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static size_t compute_smem() {
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size_t off = 0;
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off += 4; off = (off+127)&~(size_t)127;
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off += 16; off = (off+127)&~(size_t)127;
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off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sTmaBuf
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off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sQ0
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off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sK0
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off += TILE_SZ * 2; off = (off+127)&~(size_t)127; // sPk
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off += 16 * MY_MMA_K * 2; // sV
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off += 128 * 4; // sRowMax
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off += 128 * 4; // sRowSum
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return off;
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}
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static void reference_attention(
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const bf16_t* q, const bf16_t* k, const bf16_t* v,
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float* o_ref, float* lse_ref,
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int hd, int T, int s_k, float scale
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) {
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for (int t = 0; t < T; t++) {
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float s[512];
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for (int j = 0; j < s_k; j++) {
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float dot = 0.0f;
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for (int d = 0; d < hd; d++) dot += bf16_to_f32_host(q[t*hd+d]) * bf16_to_f32_host(k[j*hd+d]);
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s[j] = dot * scale;
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}
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float mx = -INFINITY;
|
||||
for (int j = 0; j < s_k; j++) mx = fmaxf(mx, s[j]);
|
||||
float sm = 0.0f;
|
||||
for (int j = 0; j < s_k; j++) { s[j] = expf(s[j] - mx); sm += s[j]; }
|
||||
for (int j = 0; j < s_k; j++) s[j] /= sm;
|
||||
for (int d = 0; d < hd; d++) {
|
||||
float ov = 0.0f;
|
||||
for (int j = 0; j < s_k; j++) ov += s[j] * bf16_to_f32_host(v[d*s_k+j]);
|
||||
o_ref[t * hd + d] = ov;
|
||||
}
|
||||
if (lse_ref) lse_ref[t] = logf(sm) + mx;
|
||||
}
|
||||
}
|
||||
|
||||
int main() {
|
||||
printf("=== 6-warp TMA FMHA multi-row HD=%d ===\n", HD);
|
||||
const float SCALE = 1.0f / sqrtf((float)HD);
|
||||
|
||||
int total_fail = 0;
|
||||
|
||||
// Test T=1,4,32,128
|
||||
for (int T : {1, 4, 32, 128}) {
|
||||
printf("\n--- T=%d ---\n", T);
|
||||
|
||||
bf16_t* h_q = (bf16_t*)calloc(MAX_T * HD, sizeof(bf16_t));
|
||||
bf16_t* h_k = (bf16_t*)calloc(SK * HD, sizeof(bf16_t));
|
||||
bf16_t* h_v = (bf16_t*)calloc(HD * SK, sizeof(bf16_t));
|
||||
bf16_t* h_o = (bf16_t*)calloc(MAX_T * HD, sizeof(bf16_t));
|
||||
float* h_lse = (float*)calloc(MAX_T, sizeof(float));
|
||||
|
||||
srand(42);
|
||||
for (int i=0;i<T*HD;i++) h_q[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
|
||||
for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
|
||||
for (int i=0;i<HD*SK;i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
|
||||
|
||||
bf16_t *d_q,*d_k,*d_v,*d_o; float *d_lse;
|
||||
cudaMalloc(&d_q, MAX_T*HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_v, HD*SK*sizeof(bf16_t));
|
||||
cudaMalloc(&d_o, MAX_T*HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_lse, MAX_T*sizeof(float));
|
||||
cudaMemcpy(d_q, h_q, T*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_v, h_v, HD*SK*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemset(d_o, 0, MAX_T*HD*sizeof(bf16_t));
|
||||
cudaMemset(d_lse, 0, MAX_T*sizeof(float));
|
||||
|
||||
// TMA descriptor for K
|
||||
CUtensorMap tma_k; CUtensorMap* d_tma_k;
|
||||
create_tma_desc_2d_bf16(&tma_k, d_k, SK, HD, 128, 16);
|
||||
cudaMalloc(&d_tma_k, sizeof(CUtensorMap));
|
||||
cudaMemcpy(d_tma_k, &tma_k, sizeof(CUtensorMap), cudaMemcpyHostToDevice);
|
||||
|
||||
FmhaTmaMultiRowParams params;
|
||||
params.q = d_q; params.tma_k = d_tma_k; params.v = d_v;
|
||||
params.o = d_o; params.lse = d_lse;
|
||||
params.s_k = SK; params.T = T; params.scale = SCALE;
|
||||
params.head_dim = HD;
|
||||
params.q_head_stride = T*HD; params.q_batch_stride = T*HD;
|
||||
params.k_head_stride = SK*HD; params.k_batch_stride = SK*HD;
|
||||
params.v_head_stride = HD*SK; params.v_batch_stride = HD*SK;
|
||||
params.o_head_stride = MAX_T*HD; params.o_batch_stride = MAX_T*HD;
|
||||
params.lse_head_stride = MAX_T; params.lse_batch_stride = MAX_T;
|
||||
|
||||
size_t smem = compute_smem();
|
||||
if (smem > 48*1024)
|
||||
cudaFuncSetAttribute(fmha_6warp_tma_multirow_kernel<HD>, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
|
||||
|
||||
fmha_6warp_tma_multirow_kernel<HD><<<1, 192, smem>>>(params);
|
||||
|
||||
cudaError_t err = cudaDeviceSynchronize();
|
||||
if (err != cudaSuccess) {
|
||||
printf(" CUDA ERROR: %s\n", cudaGetErrorString(err));
|
||||
total_fail++; continue;
|
||||
}
|
||||
|
||||
cudaMemcpy(h_o, d_o, T*HD*sizeof(bf16_t), cudaMemcpyHostToHost);
|
||||
cudaMemcpy(h_o, d_o, T*HD*sizeof(bf16_t), cudaMemcpyDeviceToHost);
|
||||
cudaMemcpy(h_lse, d_lse, T*sizeof(float), cudaMemcpyDeviceToHost);
|
||||
|
||||
// Reference
|
||||
float* o_ref = (float*)calloc(T*HD, sizeof(float));
|
||||
reference_attention(h_q, h_k, h_v, o_ref, nullptr, HD, T, SK, SCALE);
|
||||
|
||||
// Check
|
||||
float cs=0,na=0,nb=0; int bad=0;
|
||||
for (int t=0;t<T;t++) {
|
||||
for (int d=0;d<HD;d++) {
|
||||
float a = bf16_to_f32_host(h_o[t*HD+d]), b = o_ref[t*HD+d];
|
||||
if (fabsf(b) > 1e-4f) { cs+=a*b; na+=a*a; nb+=b*b; }
|
||||
float rel = fabsf(b)>1e-4f ? fabsf(a-b)/fabsf(b) : fabsf(a-b);
|
||||
if (rel > 0.01f) bad++;
|
||||
}
|
||||
}
|
||||
cs /= (sqrtf(na)*sqrtf(nb)+1e-10f);
|
||||
printf(" T=%d: cosine=%.8f bad=%d %s\n", T, cs, bad, bad==0&&cs>0.999f?"PASS":"FAIL");
|
||||
if (cs < 0.999f || bad > 0) total_fail++;
|
||||
|
||||
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_lse); cudaFree(d_tma_k);
|
||||
free(h_q); free(h_k); free(h_v); free(h_o); free(h_lse); free(o_ref);
|
||||
}
|
||||
|
||||
printf("\nOverall: %s\n", total_fail==0?"ALL PASSED":"SOME FAILED");
|
||||
return total_fail == 0 ? 0 : 1;
|
||||
}
|
||||
Reference in New Issue
Block a user