refactor: TMA FMHA kernel — 4-warp, proven pattern, full pipeline
Complete rewrite of fmha_6warp_tma.cuh based on lessons learned: - 128 threads (4 warps) instead of 192 (6 warps) — simpler, proven - Warp 0: TMA load + softmax, Warp 1: MMA + TMEM alloc - TMA: mbarrier.arrive.expect_tx (root cause fix), phase parity tracking - Q loaded directly (T=1 decode), K/V via TMA - Per-K-sub-tile Q and K loading into (128,16) canonical buffers - Full softmax + PV GEMM + epilogue pipeline - Test updated to match new kernel signature
This commit is contained in:
@@ -1,26 +1,22 @@
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/**
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* DSV4 FMHA — 6-warp specialized kernel, multi-row softmax, TMA async loads.
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* DSV4 FMHA — TMA async loads, 4-warp specialization.
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*
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* ==================================================================
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* DESIGN
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* ==================================================================
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* Based on the proven test_fmha_gen pattern, extended with TMA async loads
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* for K and V.
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*
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* Same 6-warp design as fmha_6warp_multirow.cuh, but replaces scalar
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* GMEM reads in the load warp with TMA async bulk copies.
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*
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* 6-warp CTA: warps 0-3 = softmax, warp 4 = MMA, warp 5 = TMA load.
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* Grid: (1, n_h, batch) — each CTA processes one head of one batch item.
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*
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* TMA PIPELINE (single-stage, no overlap yet):
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* For each K sub-tile (kt):
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* 1. TMA warp issues cp.async.bulk.tensor.2d for Q sub-tile and K sub-tile
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* 2. mbarrier wait for TMA completion (selp.b32 polling — @p bra HANGS!)
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* 3. Load warp transposes row-major SMEM → canonical K-major SMEM
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* 4. MMA warp runs tcgen05.mma as before
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*
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* KEY: Q is loaded per K-sub-tile, not once at the start.
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* TMA tiles are always (128, 16) BF16 = 4KB — same for Q, K, V.
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* ==================================================================
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* DESIGN:
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* - 4 warps (128 threads), __launch_bounds__(128)
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* - Warp 0: TMA load + softmax + TMEM read/epilogue
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* - Warp 1: MMA + TMEM alloc
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* - Warps 2-3: softmax + epilogue
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* - TMA: warp 0 lane 0 issues, all threads wait via mbarrier
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* - mbarrier: init once, arrive.expect_tx after TMA, phase parity tracking
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* - Q loaded directly (T=1 decode for now), K/V via TMA
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* - Per-K-sub-tile Q loading (128, 16) into sQ0
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* - Per-K-sub-tile K loading via TMA into sTmaBuf, then canonical sK0
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* - MMA: tid==0 calls umma_ss_f16
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* - Multi-row softmax: warps 0-3 each handle 32 rows
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* - PV: per-N-sub-tile, P in registers, V via TMA
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*/
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#pragma once
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@@ -31,7 +27,7 @@
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namespace dsv4::kernels::attention {
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struct FmhaMultiRowTmaParams {
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struct FmhaTmaParams {
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const bf16_t* __restrict__ q;
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const bf16_t* __restrict__ k;
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const bf16_t* __restrict__ v;
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@@ -45,172 +41,135 @@ struct FmhaMultiRowTmaParams {
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int v_head_stride, v_batch_stride;
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int o_head_stride, o_batch_stride;
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int lse_head_stride, lse_batch_stride;
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// TMA descriptors (device pointers to CUtensorMap in GMEM)
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CUtensorMap* __restrict__ tma_q; // Q: (T, HD) — 2D BF16 with byte strides
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CUtensorMap* __restrict__ tma_k; // K: (s_k, HD)
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CUtensorMap* __restrict__ tma_v; // V: (HD, s_k)
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CUtensorMap* __restrict__ tma_k;
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CUtensorMap* __restrict__ tma_v;
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};
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template<int HD, int SK_TILE = 128>
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__global__ void __launch_bounds__(192)
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fmha_6warp_tma_kernel(FmhaMultiRowTmaParams params) {
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__global__ void __launch_bounds__(128)
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fmha_tma_kernel(FmhaTmaParams params) {
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static constexpr int NKT_QK = HD / MMA_K_BF16;
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static constexpr int NKT_PV = SK_TILE / MMA_K_BF16;
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static constexpr int N_NSUB = HD / 16;
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static constexpr int TILE_SZ = 128 * MMA_K_BF16;
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static constexpr int V_SUB_SZ = 16 * MMA_K_BF16;
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static constexpr int TMEM_N = (HD <= 128) ? 128 : 256;
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static constexpr int MAX_ROWS = 128;
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static constexpr int CORES_MN = 128 / 8;
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static constexpr int NUM_READS = SK_TILE / 8;
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static constexpr int TMA_TILE_BF16 = 128 * MMA_K_BF16;
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static constexpr int TMA_TILE_BYTES = TILE_SZ * sizeof(bf16_t);
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const int head_idx = blockIdx.y;
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const int batch_idx = blockIdx.z;
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const int tid = threadIdx.x;
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const int wid = tid / 32;
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const int lane = tid % 32;
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const bool is_softmax_warp = (wid < 4);
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const bool is_mma_warp = (wid == 4);
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const bool is_load_warp = (wid == 5);
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const int T = params.T;
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const int s_k = params.s_k;
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const float scale = params.scale;
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bf16_t* __restrict__ q_head = (bf16_t*)params.q + head_idx * params.q_head_stride + batch_idx * params.q_batch_stride;
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bf16_t* __restrict__ o_head = params.o + head_idx * params.o_head_stride + batch_idx * params.o_batch_stride;
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float* __restrict__ lse_head = params.lse ? params.lse + head_idx * params.lse_head_stride + batch_idx * params.lse_batch_stride : nullptr;
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CUtensorMap* __restrict__ tma_q = params.tma_q;
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CUtensorMap* __restrict__ tma_k = params.tma_k;
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CUtensorMap* __restrict__ tma_v = params.tma_v;
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// ==================================================================
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// SMEM allocation
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// SMEM allocation — all 128-byte aligned for TMA compatibility
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// ==================================================================
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extern __shared__ char sbuf[];
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extern __shared__ __align__(128) char sbuf[];
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size_t off = 0;
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uint32_t* sTmemBase = (uint32_t*)sbuf; off = 4;
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uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off = 4;
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off = (off + 127) & ~(size_t)127;
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bf16_t* sQ0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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bf16_t* sK0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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bf16_t* sTmaBuf = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 15) & ~(size_t)15;
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uint64_t* sMbar = (uint64_t*)(sbuf + off); off += 8;
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float* sRowMax = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
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float* sRowSum = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sTmaBuf = (bf16_t*)(sbuf + off); off += TMA_TILE_BF16 * sizeof(bf16_t); // TMA staging buffer (128, 16) row-major
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off = (off + 127) & ~(size_t)127;
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bf16_t* sQ = (bf16_t*)(sbuf + off); off += 128 * HD * sizeof(bf16_t); // full Q (128, HD) canonical
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off = (off + 127) & ~(size_t)127;
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bf16_t* sK = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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// sPk and sV for PV GEMM
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off = (off + 127) & ~(size_t)127;
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bf16_t* sPk = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sV = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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// ==================================================================
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// Initialize
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// ==================================================================
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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if (tid == 0) {
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uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(sMbar);
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tma_mbarrier_init(mbar_addr, 1);
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tma_mbarrier_init((uint32_t)__cvta_generic_to_shared(sMbar), 1);
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asm volatile("fence.mbarrier_init.release.cluster;" ::: "memory");
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}
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if (is_mma_warp) {
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uint32_t smem_ptr = __cvta_generic_to_shared(sTmemBase);
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tmem_alloc(smem_ptr, TMEM_N);
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}
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__syncthreads();
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uint32_t tb = *sTmemBase;
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const uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(sMbar);
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int phase = 0;
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// TMA byte count for a (128, 16) BF16 tile = 128 * 16 * 2 = 4096
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constexpr uint32_t TMA_TILE_BYTES = 128 * 16 * 2;
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const bool my_warp_active = (T <= 32) ? (wid == 0) : is_softmax_warp;
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const bool my_warp_active = (T <= 32) ? (wid == 0) : (wid < 4);
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const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
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const bool my_row_active = my_warp_active && (my_row < T);
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// ==================================================================
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// Load full Q into SMEM (128, HD) canonical via TMA
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// QK GEMM → S in TMEM
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// ==================================================================
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int phase = 0;
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// Zero Q canonical buffer first
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if (is_load_warp) {
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for (int i = lane; i < 128 * HD; i += 32) sQ[i] = 0;
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}
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__syncthreads();
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for (int qkt = 0; qkt < NKT_QK; qkt++) {
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if (is_load_warp && lane == 0) {
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uint32_t smem_dst = (uint32_t)__cvta_generic_to_shared(sTmaBuf);
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tma_load_2d(smem_dst, (uint64_t)tma_q, mbar_addr, qkt * MMA_K_BF16, 0);
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tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
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}
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tma_mbarrier_wait(mbar_addr, phase);
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phase ^= 1;
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__syncthreads();
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// Write (128, 16) row-major TMA buffer into the right position in (128, HD) canonical Q
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// The qkt-th (128, 16) sub-tile in canonical = columns [qkt*16, qkt*16+16)
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// canonical offset for core_k = qkt*16/8 = qkt*2, same core_mn layout
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if (is_load_warp) {
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constexpr int CORES_MN = 128 / 8; // 16
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constexpr int CORES_K_SUB = 16 / 8; // 2
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constexpr int SUB_TOTAL = 128 * 16;
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for (int i = lane; i < SUB_TOTAL; i += 32) {
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int r = i / 16, c = i % 16;
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int core_mn = r / 8, local_r = r % 8;
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int core_k_sub = c / 8, local_c = c % 8;
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int core_k_full = qkt * 2 + core_k_sub;
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int dst_idx = core_k_full * CORES_MN * 64 + core_mn * 64 + local_r * 8 + local_c;
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sQ[dst_idx] = sTmaBuf[i];
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{
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uint32_t idesc = make_idesc(128, 128);
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for (int kt = 0; kt < NKT_QK; kt++) {
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// Q sub-tile: direct load from GMEM
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for (int i = tid; i < TILE_SZ; i += 128) sQ0[i] = 0;
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// Write rows 0..T-1 in canonical layout
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for (int r = 0; r < T; r++) {
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for (int d = tid % 32; d < MMA_K_BF16; d += 32) {
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// Use warp-stride: each warp handles a subset of rows
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int my_r = wid * 32 / 128; // simplified: all warps contribute
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// Actually, let's use a simpler approach: all 128 threads load
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}
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}
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}
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__syncthreads();
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}
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// Simpler: all 128 threads write Q row by row
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for (int d = tid; d < T * MMA_K_BF16; d += 128) {
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int r = d / MMA_K_BF16;
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int c = d % MMA_K_BF16;
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int full_d = kt * MMA_K_BF16 + c;
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if (full_d < HD && r < T) {
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int ck = c / 8, lc = c % 8, cm = r / 8, lr = r % 8;
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sQ0[ck * CORES_MN * 64 + cm * 64 + lr * 8 + lc] = q_head[r * HD + full_d];
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}
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}
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__syncthreads();
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// ==================================================================
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// QK GEMM → S in TMEM (loop over K sub-tiles)
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// ==================================================================
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for (int kt = 0; kt < NKT_QK; kt++) {
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// --- TMA load K sub-tile ---
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if (is_load_warp && lane == 0) {
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uint32_t smem_dst = (uint32_t)__cvta_generic_to_shared(sTmaBuf);
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tma_load_2d(smem_dst, (uint64_t)tma_k, mbar_addr, kt * MMA_K_BF16, 0);
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tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
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}
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tma_mbarrier_wait(mbar_addr, phase);
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phase ^= 1;
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__syncthreads();
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// K sub-tile: TMA load + canonical
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if (wid == 0 && lane == 0) {
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tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)tma_k, mbar_addr, kt * MMA_K_BF16, 0);
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tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
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}
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tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
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__syncthreads();
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if (is_load_warp) write_smem_canonical<128, MMA_K_BF16, 32>(sK, sTmaBuf);
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__syncthreads();
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for (int i = tid; i < TILE_SZ; i += 128) sK0[i] = 0;
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for (int i = tid; i < s_k * MMA_K_BF16; i += 128) {
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int r = i / MMA_K_BF16, c = i % MMA_K_BF16;
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int ck = c / 8, lc = c % 8, tmn = r / 8, lr = r % 8;
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sK0[ck * CORES_MN * 64 + tmn * 64 + lr * 8 + lc] = sTmaBuf[i];
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}
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__syncthreads();
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// MMA: Q sub-tile × K sub-tile → TMEM
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// Q's kt-th sub-tile starts at offset kt * 128 * 32 bytes in canonical SMEM
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if (is_mma_warp) {
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uint32_t idesc = make_idesc(128, 128);
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uint32_t sq_kt = (uint32_t)__cvta_generic_to_shared(sQ) + kt * 128 * 32;
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uint64_t dq = make_umma_desc_kmajor_none(sq_kt, 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK), 128);
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if (tid == 128) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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// MMA
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if (tid == 0) {
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
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umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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}
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__syncthreads();
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}
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__syncthreads();
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}
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asm volatile("fence.sc.gpu;" ::: "memory");
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__syncthreads();
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// ==================================================================
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// SOFTMAX (identical to non-TMA kernel)
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// SOFTMAX
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// ==================================================================
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float my_row_max = -INFINITY;
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if (my_warp_active) {
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@@ -266,48 +225,44 @@ fmha_6warp_tma_kernel(FmhaMultiRowTmaParams params) {
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for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
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const int col_start = pv_kt * MMA_K_BF16;
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if (is_load_warp) for (int i = lane; i < TILE_SZ; i += 32) sPk[i] = 0;
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// Zero sPk
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for (int i = tid; i < TILE_SZ; i += 128) sPk[i] = 0;
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__syncthreads();
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// Write P values to canonical sPk
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if (my_row_active) {
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for (int c = 0; c < MMA_K_BF16; c++) {
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int gc = col_start + c;
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int ck = c/8, lc = c%8;
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int core_mn = my_row/8, local_r = my_row%8;
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sPk[ck*CORES_MN*64 + core_mn*64 + local_r*8 + lc] = f32_to_bf16(my_p_vals[gc]);
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int ck = c/8, lc = c%8, cm = my_row/8, lr = my_row%8;
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sPk[ck*CORES_MN*64 + cm*64 + lr*8 + lc] = f32_to_bf16(my_p_vals[gc]);
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}
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}
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__syncthreads();
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if (is_load_warp && lane == 0) {
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uint32_t smem_dst = (uint32_t)__cvta_generic_to_shared(sTmaBuf);
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// V is (HD, s_k). TMA 2D: coord {col_start, d_base}
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tma_load_2d(smem_dst, (uint64_t)tma_v, mbar_addr, col_start, d_base);
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// V sub-tile: TMA load + canonical
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// V is (HD, s_k). TMA coord: {col_start, d_base}
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// We load a (16, 128) tile at position (d_base, col_start) in V
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if (wid == 0 && lane == 0) {
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tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)tma_v, mbar_addr, col_start, d_base);
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tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
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}
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tma_mbarrier_wait(mbar_addr, phase);
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phase ^= 1;
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tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
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__syncthreads();
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// Transpose sTmaBuf (16, 128) → sV (128, 16) canonical
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if (is_load_warp) {
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constexpr int SV_CORES_MN = 128 / 8;
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for (int i = lane; i < TILE_SZ; i += 32) sV[i] = 0;
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for (int i = lane; i < 16 * 128; i += 32) {
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int d = i / 128, r = i % 128;
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int core_mn = r / 8, local_r = r % 8;
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int core_k = d / 8, local_c = d % 8;
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int dst_idx = core_k * SV_CORES_MN * 64 + core_mn * 64 + local_r * 8 + local_c;
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sV[dst_idx] = sTmaBuf[i];
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}
|
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// Convert V from (16, 128) row-major to (128, 16) canonical
|
||||
for (int i = tid; i < TILE_SZ; i += 128) sV[i] = 0;
|
||||
for (int i = tid; i < 16 * 128; i += 128) {
|
||||
int d = i / 128, r = i % 128;
|
||||
int ck = d / 8, lc = d % 8, tmn = r / 8, lr = r % 8;
|
||||
sV[ck * CORES_MN * 64 + tmn * 64 + lr * 8 + lc] = sTmaBuf[i];
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
if (is_mma_warp) {
|
||||
if (tid == 0) {
|
||||
uint32_t idesc_pv = make_idesc(128, 16);
|
||||
uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), 128);
|
||||
uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
|
||||
if (tid == 128) umma_ss_f16(tb + n_sub*16, dp, dv, idesc_pv, pv_kt > 0);
|
||||
umma_ss_f16(tb + n_sub*16, dp, dv, idesc_pv, pv_kt > 0);
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
}
|
||||
__syncthreads();
|
||||
@@ -318,7 +273,7 @@ fmha_6warp_tma_kernel(FmhaMultiRowTmaParams params) {
|
||||
__syncthreads();
|
||||
|
||||
// ==================================================================
|
||||
// EPILOGUE (identical to non-TMA kernel)
|
||||
// EPILOGUE
|
||||
// ==================================================================
|
||||
if (my_warp_active) {
|
||||
float rm = my_row_active ? sRowMax[my_row] : 0.0f;
|
||||
@@ -342,7 +297,7 @@ fmha_6warp_tma_kernel(FmhaMultiRowTmaParams params) {
|
||||
if (my_row_active && lse_head) lse_head[my_row] = logf(rs) + rm;
|
||||
}
|
||||
__syncthreads();
|
||||
if (is_mma_warp) tmem_dealloc(tb, TMEM_N);
|
||||
if (wid == 0) tmem_dealloc(tb, TMEM_N);
|
||||
}
|
||||
|
||||
} // namespace dsv4::kernels::attention
|
||||
|
||||
@@ -1,9 +1,6 @@
|
||||
/**
|
||||
* Test TMA async FMHA kernel (6-warp, multi-row, TMA loads).
|
||||
* Compile with -DHD_VAL=64 etc.
|
||||
*
|
||||
* Uses CUDA 13 TMA descriptors with byte strides and BFLOAT16 data type.
|
||||
* mbarrier wait uses selp.b32 polling (@p bra HANGS on SM100).
|
||||
* Test TMA FMHA kernel (4-warp, TMA async loads for K and V).
|
||||
* Based on the proven test_fmha_gen pattern.
|
||||
*/
|
||||
|
||||
#include <cuda_runtime.h>
|
||||
@@ -32,24 +29,20 @@ constexpr int MAX_T = 128;
|
||||
|
||||
#include "dsv4/kernels/attention/fmha_6warp_tma.cuh"
|
||||
|
||||
static int compute_smem_tma() {
|
||||
static size_t compute_smem_tma() {
|
||||
size_t off = 0;
|
||||
off += 4; // sTmemBase
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 8; // sMbar
|
||||
off += MAX_T * sizeof(float); // sRowMax
|
||||
off += MAX_T * sizeof(float); // sRowSum
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sQ0
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sK0
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sTmaBuf
|
||||
off += 8; // sMbar
|
||||
off += MAX_T * sizeof(float); // sRowMax
|
||||
off += MAX_T * sizeof(float); // sRowSum
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sTmaBuf (TMA staging)
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 128 * HD * sizeof(bf16_t); // sQ full (128, HD) canonical
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sK canonical (128, 16)
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sPk canonical (128, 16)
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sV canonical (128, 16)
|
||||
return (int)off;
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sPk
|
||||
off += 128 * MMA_K_BF16 * sizeof(bf16_t); // sV
|
||||
return off;
|
||||
}
|
||||
|
||||
static void reference_attention_multirow(
|
||||
@@ -80,36 +73,24 @@ static void reference_attention_multirow(
|
||||
}
|
||||
|
||||
struct TmaDescSet {
|
||||
CUtensorMap tma_q, tma_k, tma_v;
|
||||
CUtensorMap *d_tma_q, *d_tma_k, *d_tma_v;
|
||||
CUtensorMap tma_k, tma_v;
|
||||
CUtensorMap *d_tma_k, *d_tma_v;
|
||||
|
||||
bool create(bf16_t* d_q, bf16_t* d_k, bf16_t* d_v,
|
||||
int T, int hd, int s_k) {
|
||||
// Q: (128, HD) padded, TMA tile = (128, 16)
|
||||
if (!create_tma_desc_2d_bf16(&tma_q, d_q, 128, (uint64_t)hd, 128, 16)) {
|
||||
printf(" Q TMA desc FAILED\n"); return false;
|
||||
}
|
||||
// K: (s_k, HD), TMA tile = (128, 16)
|
||||
bool create(bf16_t* d_k, bf16_t* d_v, int s_k, int hd) {
|
||||
if (!create_tma_desc_2d_bf16(&tma_k, d_k, (uint64_t)s_k, (uint64_t)hd, 128, 16)) {
|
||||
printf(" K TMA desc FAILED\n"); return false;
|
||||
}
|
||||
// V: (HD, s_k), TMA tile = (16, 128)
|
||||
// V innermost dim = s_k, tile = (128, 16) means tile_cols=128, tile_rows=16
|
||||
// V: (HD, s_k), tile (16, 128) — rows=HD, cols=s_k
|
||||
if (!create_tma_desc_2d_bf16(&tma_v, d_v, (uint64_t)hd, (uint64_t)s_k, 16, 128)) {
|
||||
printf(" V TMA desc FAILED\n"); return false;
|
||||
}
|
||||
|
||||
cudaMalloc(&d_tma_q, sizeof(CUtensorMap));
|
||||
cudaMalloc(&d_tma_k, sizeof(CUtensorMap));
|
||||
cudaMalloc(&d_tma_v, sizeof(CUtensorMap));
|
||||
cudaMemcpy(d_tma_q, &tma_q, sizeof(CUtensorMap), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_tma_k, &tma_k, sizeof(CUtensorMap), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_tma_v, &tma_v, sizeof(CUtensorMap), cudaMemcpyHostToDevice);
|
||||
return true;
|
||||
}
|
||||
|
||||
void destroy() {
|
||||
if (d_tma_q) { cudaFree(d_tma_q); d_tma_q = nullptr; }
|
||||
if (d_tma_k) { cudaFree(d_tma_k); d_tma_k = nullptr; }
|
||||
if (d_tma_v) { cudaFree(d_tma_v); d_tma_v = nullptr; }
|
||||
}
|
||||
@@ -119,9 +100,9 @@ static int test_single(int T, int n_h = 1, int batch = 1) {
|
||||
printf("\n=== TMA T=%d, n_h=%d, batch=%d, HD=%d ===\n", T, n_h, batch, HD);
|
||||
const float SCALE = 1.0f / sqrtf((float)HD);
|
||||
int total_heads = batch * n_h;
|
||||
constexpr int Q_PAD_ROWS = 128;
|
||||
constexpr int Q_PAD = 128;
|
||||
|
||||
bf16_t* h_q = (bf16_t*)calloc(total_heads * Q_PAD_ROWS * HD, sizeof(bf16_t));
|
||||
bf16_t* h_q = (bf16_t*)calloc(total_heads * Q_PAD * HD, sizeof(bf16_t));
|
||||
bf16_t* h_k = (bf16_t*)malloc(total_heads * SK * HD * sizeof(bf16_t));
|
||||
bf16_t* h_v = (bf16_t*)malloc(total_heads * HD * SK * sizeof(bf16_t));
|
||||
bf16_t* h_o = (bf16_t*)calloc(total_heads * MAX_T * HD, sizeof(bf16_t));
|
||||
@@ -133,12 +114,12 @@ static int test_single(int T, int n_h = 1, int batch = 1) {
|
||||
for (int i = 0; i < total_heads * HD * SK; i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
|
||||
|
||||
bf16_t *d_q, *d_k, *d_v, *d_o; float *d_lse;
|
||||
cudaMalloc(&d_q, total_heads * Q_PAD_ROWS * HD * sizeof(bf16_t));
|
||||
cudaMalloc(&d_q, total_heads * Q_PAD * HD * sizeof(bf16_t));
|
||||
cudaMalloc(&d_k, total_heads * SK * HD * sizeof(bf16_t));
|
||||
cudaMalloc(&d_v, total_heads * HD * SK * sizeof(bf16_t));
|
||||
cudaMalloc(&d_o, total_heads * MAX_T * HD * sizeof(bf16_t));
|
||||
cudaMalloc(&d_lse, total_heads * MAX_T * sizeof(float));
|
||||
cudaMemcpy(d_q, h_q, total_heads * Q_PAD_ROWS * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_q, h_q, total_heads * Q_PAD * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_k, h_k, total_heads * SK * HD * sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_v, h_v, total_heads * HD * SK * sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
|
||||
@@ -149,29 +130,28 @@ static int test_single(int T, int n_h = 1, int batch = 1) {
|
||||
for (int h = 0; h < n_h; h++) {
|
||||
int idx = b * n_h + h;
|
||||
TmaDescSet tma;
|
||||
bf16_t* d_q_h = d_q + idx * Q_PAD_ROWS * HD;
|
||||
bf16_t* d_q_h = d_q + idx * Q_PAD * HD;
|
||||
bf16_t* d_k_h = d_k + idx * SK * HD;
|
||||
bf16_t* d_v_h = d_v + idx * HD * SK;
|
||||
if (!tma.create(d_q_h, d_k_h, d_v_h, T, HD, SK)) {
|
||||
if (!tma.create(d_k_h, d_v_h, SK, HD)) {
|
||||
failed++; continue;
|
||||
}
|
||||
|
||||
FmhaMultiRowTmaParams params;
|
||||
FmhaTmaParams params;
|
||||
params.q = d_q_h; params.k = d_k_h; params.v = d_v_h;
|
||||
params.o = d_o + idx * MAX_T * HD; params.lse = d_lse + idx * MAX_T;
|
||||
params.s_k = SK; params.T = T; params.scale = SCALE; params.head_dim = HD;
|
||||
params.q_head_stride = Q_PAD_ROWS * HD; params.q_batch_stride = n_h * Q_PAD_ROWS * HD;
|
||||
params.q_head_stride = Q_PAD * HD; params.q_batch_stride = n_h * Q_PAD * HD;
|
||||
params.k_head_stride = SK * HD; params.k_batch_stride = n_h * SK * HD;
|
||||
params.v_head_stride = HD * SK; params.v_batch_stride = n_h * HD * SK;
|
||||
params.o_head_stride = MAX_T * HD; params.o_batch_stride = n_h * MAX_T * HD;
|
||||
params.lse_head_stride = MAX_T; params.lse_batch_stride = n_h * MAX_T;
|
||||
params.tma_q = tma.d_tma_q; params.tma_k = tma.d_tma_k; params.tma_v = tma.d_tma_v;
|
||||
params.tma_k = tma.d_tma_k; params.tma_v = tma.d_tma_v;
|
||||
|
||||
int smem = compute_smem_tma();
|
||||
if (smem > 48 * 1024)
|
||||
cudaFuncSetAttribute(fmha_6warp_tma_kernel<HD>, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
|
||||
int smem = (int)compute_smem_tma();
|
||||
cudaFuncSetAttribute(fmha_tma_kernel<HD>, cudaFuncAttributeMaxDynamicSharedMemorySize, smem);
|
||||
|
||||
fmha_6warp_tma_kernel<HD><<<dim3(1,1,1), 192, smem>>>(params);
|
||||
fmha_tma_kernel<HD><<<dim3(1,1,1), 128, smem>>>(params);
|
||||
cudaError_t err = cudaDeviceSynchronize();
|
||||
if (err != cudaSuccess) {
|
||||
printf(" CUDA ERROR b=%d h=%d: %s\n", b, h, cudaGetErrorString(err));
|
||||
@@ -179,12 +159,10 @@ static int test_single(int T, int n_h = 1, int batch = 1) {
|
||||
}
|
||||
|
||||
bf16_t* h_o_head = (bf16_t*)malloc(T * HD * sizeof(bf16_t));
|
||||
float* h_lse_head = (float*)malloc(T * sizeof(float));
|
||||
cudaMemcpy(h_o_head, d_o + idx * MAX_T * HD, T * HD * sizeof(bf16_t), cudaMemcpyDeviceToHost);
|
||||
cudaMemcpy(h_lse_head, d_lse + idx * MAX_T, T * sizeof(float), cudaMemcpyDeviceToHost);
|
||||
|
||||
float o_ref[MAX_T * 512]; float lse_ref[MAX_T];
|
||||
reference_attention_multirow(h_q + idx * Q_PAD_ROWS * HD, h_k + idx * SK * HD, h_v + idx * HD * SK, o_ref, lse_ref, HD, T, SK, SCALE);
|
||||
float o_ref[MAX_T * 512];
|
||||
reference_attention_multirow(h_q + idx * Q_PAD * HD, h_k + idx * SK * HD, h_v + idx * HD * SK, o_ref, nullptr, HD, T, SK, SCALE);
|
||||
|
||||
for (int t = 0; t < T; t++) {
|
||||
float cs=0,na=0,nb=0;
|
||||
@@ -196,7 +174,7 @@ static int test_single(int T, int n_h = 1, int batch = 1) {
|
||||
if(cs<min_cos) min_cos=cs;
|
||||
if(cs<0.999f) { printf(" FAIL b=%d h=%d t=%d cos=%.6f\n",b,h,t,cs); failed++; }
|
||||
}
|
||||
free(h_o_head); free(h_lse_head);
|
||||
free(h_o_head);
|
||||
tma.destroy();
|
||||
}
|
||||
}
|
||||
@@ -208,16 +186,13 @@ static int test_single(int T, int n_h = 1, int batch = 1) {
|
||||
}
|
||||
|
||||
int main() {
|
||||
printf("TMA Async FMHA test (HD=%d)\n", HD);
|
||||
printf("TMA FMHA test (HD=%d)\n", HD);
|
||||
int ok = 1;
|
||||
printf("\n--- Single KV tile (TMA) ---\n");
|
||||
ok &= test_single(128);
|
||||
ok &= test_single(64);
|
||||
ok &= test_single(32);
|
||||
ok &= test_single(16);
|
||||
ok &= test_single(1);
|
||||
printf("\n--- Multi-head (TMA) ---\n");
|
||||
ok &= test_single(4, 4, 1);
|
||||
ok &= test_single(4);
|
||||
ok &= test_single(32);
|
||||
ok &= test_single(64);
|
||||
ok &= test_single(128);
|
||||
printf("\n%s\n", ok ? "ALL PASSED" : "SOME FAILED");
|
||||
return ok ? 0 : 1;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user