fix: warp-stride for TMA canonical writes — only load warp calls them
write_smem_canonical used NTHREADS=192 as the stride, but in the TMA kernel only the load warp (32 threads) calls it. With threadIdx.x in [160,191] and stride 192, only 32 out of 2048 elements got written. Fix: template STRIDE parameter, default 192, TMA kernel uses 32.
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@@ -162,7 +162,7 @@ fmha_6warp_tma_kernel(FmhaMultiRowTmaParams params) {
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phase ^= 1;
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__syncthreads();
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if (is_load_warp) write_smem_canonical<128, MMA_K_BF16>(sQ, sQ_tma);
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if (is_load_warp) write_smem_canonical<128, MMA_K_BF16, 32>(sQ, sQ_tma);
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__syncthreads();
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// --- TMA load K sub-tile ---
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@@ -175,7 +175,7 @@ fmha_6warp_tma_kernel(FmhaMultiRowTmaParams params) {
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phase ^= 1;
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__syncthreads();
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if (is_load_warp) write_smem_canonical<128, MMA_K_BF16>(sK, sK_tma);
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if (is_load_warp) write_smem_canonical<128, MMA_K_BF16, 32>(sK, sK_tma);
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__syncthreads();
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// MMA: sQ × sK → TMEM
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@@ -121,14 +121,15 @@ constexpr int MMA_K_BF16 = 16;
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*
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* ROWS must be a multiple of 8 (ideally 128 for full MMA tile).
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* COLS must be a multiple of 8.
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* STRIDE is the thread stride (default NTHREADS=192 for full CTA).
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*/
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template<int ROWS, int COLS>
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template<int ROWS, int COLS, int STRIDE = NTHREADS>
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__device__ void write_smem_canonical(bf16_t* __restrict__ dst,
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const bf16_t* __restrict__ src) {
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constexpr int CORES_MN = ROWS / 8;
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constexpr int CORES_K = COLS / 8;
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constexpr int TOTAL = ROWS * COLS;
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for (int i = threadIdx.x; i < TOTAL; i += NTHREADS) {
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for (int i = threadIdx.x; i < TOTAL; i += STRIDE) {
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int r = i / COLS;
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int c = i % COLS;
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int core_mn = r / 8;
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