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test: exact HD=16 pattern with HD=64 data

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biondizzle
2026-05-28 12:53:13 +00:00
parent db4f661843
commit 7d16a30cb6
1 changed files with 53 additions and 93 deletions
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146
tests/unit/test_umma_qk_hd64.cu
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@@ -1,16 +1,6 @@
/**
* UMMA QK GEMM Test — HD=64 (4 K-tiles)
*
* Using gau-nernst's approach: single contiguous SMEM, offset descriptors.
* Q is (128, HD) and K is (128, HD) in canonical K-major layout.
* For each K-tile kt, the descriptor start address is:
* base + kt * BLOCK_MN * 32 (each 16-BF16 K-tile is BLOCK_MN * 32 bytes apart)
*
* Fixes from previous version:
* 1. Zero TMEM before accumulate (tcgen05.alloc does NOT zero)
* 2. tcgen05.fence::after_thread_sync after each MMA + before TMEM read
* 3. Single-thread MMA call (tid==0)
* 4. Contiguous SMEM with offset descriptors
* UMMA QK GEMM Test — HD=64, debug: exact copy of working HD=16 pattern
* Only uses first 16 dims. If this fails, the issue is in SMEM/alignment.
*/
#include <cuda_runtime.h>
@@ -27,67 +17,52 @@ using namespace dsv4::kernels::attention;
static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
constexpr int HD = 64;
constexpr int SK = 128;
constexpr int NKT = HD / MMA_K_BF16; // 4
constexpr int BLOCK_MN = 128;
__global__ void __launch_bounds__(128)
test_umma_hd64(const bf16_t* __restrict__ q, const bf16_t* __restrict__ k,
test_umma_hd64_debug(const bf16_t* __restrict__ q, const bf16_t* __restrict__ k,
float* __restrict__ s_out, float* __restrict__ s_scalar, float scale)
{
const int tid = threadIdx.x;
const int wid = tid / WARP, lane = tid % WARP;
const int wid = tid / 32, lane = tid % 32;
// SMEM layout:
// [0..3] tmem_base
// [64..) sQ (128, HD) canonical = 128*64*2 = 16384 bytes
// sK (128, HD) canonical = 16384 bytes
// Align to 128 bytes for SMEM access patterns
// EXACT same layout as test_umma_qk.cu (working HD=16 test)
extern __shared__ char sbuf[];
uint32_t* sTmemBase = (uint32_t*)sbuf;
bf16_t* sQ = (bf16_t*)(sbuf + 64); // 64-byte aligned
bf16_t* sK = sQ + BLOCK_MN * HD; // follows Q
bf16_t* sQ = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
bf16_t* sK = sQ + 128 * 16 + 4096; // Same padding as HD=16 test
float* sQ_row = (float*)(sK + 128 * 16);
// Load Q (1, 16) into (128, 16) canonical — only first K-tile for debug
write_q_to_smem<16>(sQ, q);
write_k_to_smem<SK, 16>(sK, k);
__syncthreads();
// Load first 16 dims of Q to SMEM + sQ_row for scalar
for (int d = tid; d < 16; d += 128) sQ_row[d] = bf16_to_f32(q[d]);
// TMEM alloc — 128 columns for (128, 128) Layout D output
if (wid == 0) {
// TMEM alloc (128 cols) — same as HD=16 test
if (wid == 1) {
tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128);
}
__syncthreads();
uint32_t tb = *sTmemBase;
// Note: tcgen05.alloc does NOT zero TMEM.
// We use accumulate=false for the first K-tile, then accumulate=true.
// Load Q and K into SMEM in canonical layout — ONLY first 16 dims
write_q_to_smem<16>(sQ, q);
write_k_to_smem<128, 16>(sK, k); // k is (128, 64), but we only read first 16 cols
bf16_t* sQ_pad = sQ + 128 * 16;
for (int i = tid; i < 4096; i += 128) sQ_pad[i] = 0;
__syncthreads();
// Multi-K-tile QK GEMM
// For K-major NONE layout, each 16-column K-tile starts at:
// base_smem + kt * BLOCK_MN * 32 (in bytes)
// Each K-tile spans 2 core-matrix columns (16 BF16).
// LBO = BLOCK_MN * 16 (bytes) = stride between the 2 core columns.
// The descriptor describes a (BLOCK_MN, 16) sub-matrix.
// Construct descriptors — EXACT same as HD=16 test
uint32_t sQ_smem = __cvta_generic_to_shared(sQ);
uint32_t sK_smem = __cvta_generic_to_shared(sK);
uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
uint64_t desc_q = make_umma_desc_kmajor_none(sQ_smem, 128);
uint64_t desc_k = make_umma_desc_kmajor_none(sK_smem, 128);
uint32_t idesc = make_idesc(128, 128);
// Single K-tile: descriptors point to start of SMEM
uint64_t dq = make_umma_desc_kmajor_none(sQ_smem, BLOCK_MN);
uint64_t dk = make_umma_desc_kmajor_none(sK_smem, BLOCK_MN);
if (tid == 0) {
umma_ss_f16(tb, dq, dk, idesc, false);
// MMA — 4 warp leaders call simultaneously (same as HD=16 test)
if (lane == 0) {
umma_ss_f16(tb, desc_q, desc_k, idesc, false);
}
// Final fence before TMEM read
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
__syncthreads();
// Read S from TMEM (Layout D: 32x32b.x8)
// Read from TMEM using Layout D — same as HD=16 test
for (int n = 0; n < 128 / 8; n++) {
const int row = wid * 32;
const int col = n * 8;
@@ -97,37 +72,36 @@ test_umma_hd64(const bf16_t* __restrict__ q, const bf16_t* __restrict__ k,
asm volatile("tcgen05.wait::ld.sync.aligned;");
int out_row = wid * 32 + lane;
if (out_row < SK) {
if (n < 1 && out_row < 128) {
for (int c = 0; c < 8; c++) {
int out_col = n * 8 + c;
if (out_col < SK) {
s_out[out_row * SK + out_col] = tmp[c] * scale;
}
s_out[out_row * 8 + c] = tmp[c] * scale;
}
}
}
__syncthreads();
// Scalar reference
// Scalar reference — first 16 dims only
if (tid == 0) {
for (int j = 0; j < SK; j++) {
for (int c = 0; c < 128; c++) {
float dot = 0.0f;
for (int d = 0; d < 16; d++) // DEBUG: only first K-tile
dot += bf16_to_f32(q[d]) * bf16_to_f32(k[j * HD + d]);
s_scalar[j] = dot * scale;
for (int d = 0; d < 16; d++)
dot += sQ_row[d] * bf16_to_f32(k[c * 64 + d]); // k has stride 64
s_scalar[c] = dot * scale;
}
}
__syncthreads();
if (wid == 0) tmem_dealloc(tb, 128);
}
int main() {
printf("=== UMMA QK GEMM HD=64 (4 K-tiles, contiguous SMEM) ===\n");
printf("=== UMMA QK HD=64 DEBUG (exact HD=16 pattern, first 16 dims) ===\n");
const int HD = 64, SK = 128;
const float SCALE = 1.0f / sqrtf((float)HD);
bf16_t* h_q = (bf16_t*)malloc(HD * sizeof(bf16_t));
bf16_t* h_k = (bf16_t*)malloc(SK * HD * sizeof(bf16_t));
float* h_s_out = (float*)calloc(SK * SK, sizeof(float));
float* h_s_out = (float*)calloc(128*8, sizeof(float));
float* h_s_scalar = (float*)calloc(SK, sizeof(float));
srand(42);
@@ -136,49 +110,35 @@ int main() {
bf16_t *d_q, *d_k; float *d_s_out, *d_s_scalar;
cudaMalloc(&d_q, HD*sizeof(bf16_t)); cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
cudaMalloc(&d_s_out, SK*SK*sizeof(float)); cudaMalloc(&d_s_scalar, SK*sizeof(float));
cudaMalloc(&d_s_out, 128*8*sizeof(float)); cudaMalloc(&d_s_scalar, SK*sizeof(float));
cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
// SMEM: 64 (tmem_base+pad) + 2 * 128*64*2 (Q+K) + 256 (extra)
int smem = (64 + 2 * BLOCK_MN * HD * sizeof(bf16_t) + 256 + 127) & ~127;
printf("SMEM: %d bytes (%d KB)\n", smem, smem / 1024);
test_umma_hd64<<<1, 128, smem>>>(d_q, d_k, d_s_out, d_s_scalar, SCALE);
int smem = (4 + 16 + 128*16*2 + 4096*2 + 128*16*2 + 16*4 + 256 + 127) & ~127;
test_umma_hd64_debug<<<1, 128, smem>>>(d_q, d_k, d_s_out, d_s_scalar, SCALE);
cudaError_t err = cudaDeviceSynchronize();
if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
cudaMemcpy(h_s_out, d_s_out, SK*SK*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(h_s_out, d_s_out, 128*8*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(h_s_scalar, d_s_scalar, SK*sizeof(float), cudaMemcpyDeviceToHost);
printf("S[0,0..7] MMA: "); for(int c=0;c<8;c++) printf("%.6f ",h_s_out[0*SK+c]); printf("\n");
printf("S[0,0..7] ref: "); for(int c=0;c<8;c++) printf("%.6f ",h_s_scalar[c]); printf("\n");
printf("S[0,120..127] MMA: "); for(int c=120;c<128;c++) printf("%.6f ",h_s_out[0*SK+c]); printf("\n");
printf("S[0,120..127] ref: "); for(int c=120;c<128;c++) printf("%.6f ",h_s_scalar[c]); printf("\n");
printf("Row 0 (MMA): ");
for (int c = 0; c < 8; c++) printf("%.6f ", h_s_out[0*8+c]);
printf("\nRow 0 scalar: ");
for (int c = 0; c < 8; c++) printf("%.6f ", h_s_scalar[c]);
printf("\n");
float max_diff = 0.0f, max_val = 0.0f;
for (int c = 0; c < SK; c++) {
float diff = fabsf(h_s_out[0*SK+c] - h_s_scalar[c]);
max_diff = fmaxf(max_diff, diff);
max_val = fmaxf(max_val, fabsf(h_s_scalar[c]));
float row0_max_diff = 0.0f, row0_max_val = 0.0f;
for (int c = 0; c < 8; c++) {
row0_max_diff = fmaxf(row0_max_diff, fabsf(h_s_out[0*8+c] - h_s_scalar[c]));
row0_max_val = fmaxf(row0_max_val, fabsf(h_s_scalar[c]));
}
float rel_err = max_val > 0 ? max_diff / max_val : max_diff;
printf("Row 0 rel err (128 cols): %.8f\n", rel_err);
float max_nonzero = 0.0f;
for (int r = 1; r < SK; r++)
for (int c = 0; c < SK; c++)
max_nonzero = fmaxf(max_nonzero, fabsf(h_s_out[r*SK+c]));
printf("Rows 1-127 max abs: %.8f\n", max_nonzero);
bool row0_ok = rel_err < 0.001f;
bool rows_zero = max_nonzero < 1e-5f;
printf("Row 0: %s | Rows 1-127 zero: %s\n",
row0_ok ? "PASS" : "FAIL", rows_zero ? "PASS" : "FAIL");
printf("Overall: %s\n", (row0_ok && rows_zero) ? "PASSED" : "FAILED");
float row0_rel = row0_max_val > 0 ? row0_max_diff / row0_max_val : row0_max_diff;
printf("Row 0 rel err: %.8f\n", row0_rel);
printf("Test %s\n", row0_rel < 0.001f ? "PASSED" : "FAILED");
cudaFree(d_q); cudaFree(d_k); cudaFree(d_s_out); cudaFree(d_s_scalar);
free(h_q); free(h_k); free(h_s_out); free(h_s_scalar);
return (row0_ok && rows_zero) ? 0 : 1;
return row0_rel < 0.001f ? 0 : 1;
}