perf: fused mHC Sinkhorn CUDA kernel (1 launch vs 38)
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171
dsv4/kernels/cuda/mhc_sinkhorn.cu
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171
dsv4/kernels/cuda/mhc_sinkhorn.cu
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/**
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* Fused mHC Sinkhorn-Knopp projection kernel.
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*
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* Operates on (T, n, n) matrices. For DSV4-Pro: T=1, n=4.
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* 20 iterations of alternating row/col normalization.
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*
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* Replaces 38 Python kernel launches with 1 CUDA kernel launch.
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* At 61 layers × 2 mHC calls = 122 calls/step, saves ~4,600 kernel launches.
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*
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* Matches HuggingFace DeepseekV4HyperConnection exactly:
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* 1. softmax(logits, dim=-1) + eps
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* 2. column normalize
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* 3. (t_max - 1) alternating row/col normalize
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*/
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#include <cuda.h>
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#include <cuda_runtime.h>
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#include <ATen/ATen.h>
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#include <c10/cuda/CUDAStream.h>
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#include <torch/extension.h>
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#include <cmath>
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// One thread per (t, i, j) element of the (T, n, n) matrix
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// For T=1, n=4: 16 threads total — trivial parallelism
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// For larger T, each batch element is independent
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__global__ void mhc_sinkhorn_kernel(
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const float* __restrict__ logits, // (T, n, n)
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float* __restrict__ out, // (T, n, n)
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int T, int n, int t_max, float eps
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) {
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int t = blockIdx.x;
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if (t >= T) return;
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// Each block handles one batch element
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// Use shared memory for the (n, n) matrix — n=4 → 16 floats = 64 bytes
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extern __shared__ float smem[];
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float* M = smem; // (n, n) — current matrix
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float* row_sum = smem + n * n; // (n,) — row sums
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float* col_sum = row_sum + n; // (n,) — col sums
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int i = threadIdx.x / n;
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int j = threadIdx.x % n;
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// Step 1: softmax(logits, dim=-1) + eps
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// Each row's softmax is computed by threads [i*0..i*(n-1)]
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if (i < n && j < n) {
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M[i * n + j] = logits[t * n * n + i * n + j];
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}
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__syncthreads();
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// Compute row max for numerical stability
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float row_max[n]; // n=4, so this fits in registers
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for (int ri = 0; ri < n; ri++) {
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float mx = -INFINITY;
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for (int rj = 0; rj < n; rj++) {
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mx = fmaxf(mx, M[ri * n + rj]);
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}
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row_max[ri] = mx;
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}
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// Apply softmax + eps
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for (int ri = 0; ri < n; ri++) {
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float exp_sum = 0.0f;
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for (int rj = 0; rj < n; rj++) {
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M[ri * n + rj] = expf(M[ri * n + rj] - row_max[ri]);
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exp_sum += M[ri * n + rj];
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}
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for (int rj = 0; rj < n; rj++) {
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M[ri * n + rj] = M[ri * n + rj] / exp_sum + eps;
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}
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}
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// Step 2: column normalize
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for (int cj = 0; cj < n; cj++) {
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float cs = 0.0f;
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for (int ci = 0; ci < n; ci++) cs += M[ci * n + cj];
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for (int ci = 0; ci < n; ci++) M[ci * n + cj] = M[ci * n + cj] / (cs + eps);
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}
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// Step 3: (t_max - 1) alternating row/col normalize
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for (int iter = 0; iter < t_max - 1; iter++) {
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// Row normalize
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for (int ri = 0; ri < n; ri++) {
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float rs = 0.0f;
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for (int rj = 0; rj < n; rj++) rs += M[ri * n + rj];
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for (int rj = 0; rj < n; rj++) M[ri * n + rj] = M[ri * n + rj] / (rs + eps);
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}
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// Column normalize
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for (int cj = 0; cj < n; cj++) {
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float cs = 0.0f;
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for (int ci = 0; ci < n; ci++) cs += M[ci * n + cj];
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for (int ci = 0; ci < n; ci++) M[ci * n + cj] = M[ci * n + cj] / (cs + eps);
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}
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}
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// Write output
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if (i < n && j < n) {
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out[t * n * n + i * n + j] = M[i * n + j];
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}
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}
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torch::Tensor mhc_sinkhorn_cuda(
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torch::Tensor logits, // (T, n, n) FP32
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int64_t t_max,
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double eps
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) {
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TORCH_CHECK(logits.dim() == 3, "logits must be 3D (T, n, n)");
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int T = logits.size(0);
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int n = logits.size(1);
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TORCH_CHECK(logits.size(2) == n, "logits must be square");
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TORCH_CHECK(logits.scalar_type() == torch::kFloat32, "logits must be FP32");
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auto out = torch::empty_like(logits);
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// One block per batch element, n*n threads per block
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int threads = n * n;
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int smem_size = n * n * sizeof(float) + 2 * n * sizeof(float);
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mhc_sinkhorn_kernel<<<T, threads, smem_size, c10::cuda::getCurrentCUDAStream()>>>(
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logits.data_ptr<float>(),
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out.data_ptr<float>(),
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T, n, t_max, (float)eps
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);
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return out;
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}
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// Also: fused mHC dynamic params kernel
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// Computes A_l, B_l, C_l from X_flat in a single kernel launch.
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// Currently done in ~8 separate ops in _dynamic_params().
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__global__ void mhc_dynamic_params_kernel(
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const __nv_bfloat16* __restrict__ X_flat, // (T, K) BF16
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const float* __restrict__ W_stacked, // (N_proj, K) FP32
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int T, int K, int n_hc,
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float alpha_pre, float alpha_post, float alpha_comb,
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const float* __restrict__ S_pre, // (1, n_hc)
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const float* __restrict__ S_post, // (n_hc,)
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const float* __restrict__ S_comb, // (n_hc*n_hc,)
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float eps,
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__nv_bfloat16* __restrict__ A_l_out, // (T, n_hc) BF16
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float* __restrict__ B_l_out, // (T, n_hc, n_hc) FP32
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__nv_bfloat16* __restrict__ C_l_out, // (T, n_hc) BF16
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int t_max_sinkhorn
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) {
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// This kernel is more complex — it needs to do:
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// 1. RMSNorm on X_flat
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// 2. GEMM: (T, K) × (N_proj, K)^T → (T, N_proj)
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// 3. Split + apply constraints
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// 4. Sinkhorn on comb
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//
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// The GEMM at T=1, K=28672, N=24 is small enough to do per-thread
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// with shared memory tiling.
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//
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// For now, just do the post-GEMM part (steps 3-4) as a fused kernel.
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// The GEMM stays in Python/CuTeDSL.
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// TODO: Full fusion in a future iteration.
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// This kernel handles post-GEMM: split, apply constraints, Sinkhorn
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int t = blockIdx.x;
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if (t >= T) return;
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// Thread handles one element of the output
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// Not implementing the full GEMM here — that stays in Python
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// This is a placeholder for the fused post-GEMM kernel
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}
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PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
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m.def("mhc_sinkhorn", &mhc_sinkhorn_cuda, "Fused mHC Sinkhorn-Knopp projection");
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}
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@@ -90,12 +90,21 @@ def sinkhorn_knopp(
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2. add eps
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3. column-normalize
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4. (t_max - 1) alternating row/col normalizations
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Uses fused CUDA kernel when available (1 launch instead of 38).
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Falls back to Python for correctness verification.
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"""
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# Start from softmax (row-normalized) + eps, NOT from exp
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# Try fused CUDA kernel first
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try:
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from dsv4.kernels.cuda.loader import get_cuda_module
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mod = get_cuda_module("mhc_sinkhorn", ["mhc_sinkhorn.cu"])
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return mod.mhc_sinkhorn(logits.float(), t_max, eps)
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except Exception:
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pass # Fall back to Python
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# Python fallback
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M = torch.softmax(logits, dim=-1) + eps # (T, n, n)
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# First column normalization (after the initial softmax row-norm)
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M = M / (M.sum(dim=-2, keepdim=True) + eps) # T_c (col)
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# Remaining (t_max - 1) alternating iterations
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for _ in range(t_max - 1):
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M = M / (M.sum(dim=-1, keepdim=True) + eps) # T_r (row)
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M = M / (M.sum(dim=-2, keepdim=True) + eps) # T_c (col)
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