Clean up tests: archive superseded files, keep only essential unit tests
Kept in tests/unit/: - test_fmha_v3.py (stages A+B) - test_fmha_v3_diag.py (identity softmax, n=128+256) - test_fmha_v3_stage_c.py (real softmax, n=128 cos 0.999998) - layertest.py + cudagraph_test.py (required for every change) - infrastructure: cache, custom_op, cutedsl, router, fp4, fused, interleave Archived: 19 superseded unit tests + 10 root-level scratch files Root level: only fmha_v3_stage_c_example7.py remains (now in unit/)
This commit is contained in:
@@ -1,44 +1,8 @@
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"""
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FMHA v3 Stage-C Multi-Tile (paired TMEM/SMEM atoms, reference-style epilogue).
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Two structural rules we had to learn the hard way:
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(A) Pipeline handle's `.count` is NOT a GMEM tile coordinate. Whatever it is at
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runtime (phase, wrapped slot index, internal state), it is not a global
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tile counter and TMA copies don't consume it as one. Use the loop
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induction variable for GMEM, handle.index for SMEM.
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(B) Hand-constructed TMEM load/store atoms (Ld32x32bOp + St32x32bOp built
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independently) DO NOT preserve register tile shape across a round-trip.
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A no-op TMEM-load-then-TMEM-store visibly corrupts data. Use the paired
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atoms from `utils.sm100.get_tmem_load_op` + `get_smem_store_op` — they
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are configured together for the same (mma_tiler, layout, dtype) combo
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and the register tile shape lines up. This is what the CUTLASS Blackwell
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FMHA reference does in `correction_epilog`.
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Kernel structure:
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1. Combined K+V pipeline (tx_count = K_bytes + V_bytes; one acquire per kt;
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K and V share the same barrier slot). SMEM slot via kvh.index, GMEM via
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the cutlass.range loop variable.
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2. Reference-style epilogue (TMEM → reg → scale by 1/row_sum → FP32→BF16 in
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reg → SMEM via paired atoms → TMA SMEM→GMEM). One pass, no TMEM
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round-trip, no `epilogue_tma_store` helper. Inline TMA store + named
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barrier sync to substitute for what the helper would have done.
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3. Online softmax row_max / row_sum tracking is correct, but the per-tile
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in-place TMEM O rescale (multiplying existing O by exp2(old_max - new_max)
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before PV[kt]) is currently DISABLED. Fixing that requires applying the
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same paired-atom pattern to a separate scratch SMEM buffer and bouncing
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PV's accumulator through it, which is substantial work. For now, the
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kernel is correct when row_max growth across tiles is mild. Long n with
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pronounced max growth will drift; the fix path is well-defined.
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4. final_o_bar (32 MMA + 128 softmax threads). MMA arrives between
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acc_pipe.producer_commit and producer_tail; softmax arrives_and_waits
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before reading O. Order: producer_commit → final_o_bar.arrive() →
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producer_tail (reverse deadlocks).
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FMHA v3: QK -> softmax -> PV with KV-tile interleaving.
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Bug 4b fix (FMHA pattern): P store uses QK C-fragment layout composition,
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NOT PV A-fragment layout. Register bridge: FP32 backing (store partition shape)
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recast to BF16 view (QK-load layout).
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"""
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import torch, cutlass, cutlass.cute as cute, cutlass.utils as utils, cutlass.pipeline as pipeline
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from cutlass.cute.nvgpu import cpasync, tcgen05
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@@ -47,16 +11,11 @@ from cutlass.utils import LayoutEnum
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from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset
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import cuda.bindings.driver as cuda
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import cutlass.torch as ct
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import math
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HEAD_DIM = 64
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class FmhaV3StageCMulti:
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def __init__(self, s_k=128, scale_softmax=None):
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# s_k MUST equal actual sequence length n.
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self.s_k = s_k
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self.n_kv_tiles = s_k // 128
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class FmhaV3:
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def __init__(self):
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self.acc_dtype = Float32; self.qk_acc_dtype = Float32
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self.q_dtype = BFloat16; self.o_dtype = BFloat16; self.c_dtype = BFloat16
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self.use_2cta_instrs = False; self.epilog_sync_bar_id = 1
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@@ -64,8 +23,6 @@ class FmhaV3StageCMulti:
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self.epilogue_warp_id = (0,1,2,3); self.mma_warp_id = 4; self.tma_warp_id = 5
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self.threads_per_cta = 192; self.num_c_stage = 2
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self.kv_stage = 2; self.q_stage = 1; self.num_c_stage = 2
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self.scale_softmax = scale_softmax if scale_softmax is not None else 1.0 / math.sqrt(HEAD_DIM)
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self.scale_softmax_log2 = self.scale_softmax * math.log2(math.e)
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def _setup(self, qk_mma, pv_mma):
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qk_ik = cute.size(qk_mma.shape_mnk, mode=[2])
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@@ -88,35 +45,36 @@ class FmhaV3StageCMulti:
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pv_thr = pv_mma.get_slice(0); pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2])
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tOtO = pv_thr.make_fragment_C(pv_as)
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self.tmem_s0_offset = 0; self.tmem_p0_offset = 32
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# P occupies [tmem_p0_offset, tmem_p0_offset + p_cols_fp32)
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# S occupies [0, qk_mma_tiler[1]) = [0, 128)
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# O must NOT overlap P. Place O after max(S end, P end), aligned to 32.
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p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width
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p_end = self.tmem_p0_offset + p_cols_fp32
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s_cols = self.qk_mma_tiler[1]
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o_after = max(s_cols, p_end)
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self.tmem_o0_offset = ((o_after + 31) // 32) * 32
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o_cols = find_tmem_tensor_col_offset(tOtO)
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p_end = self.tmem_p0_offset + p_cols_fp32 # 32 + 64 = 96
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s_cols = self.qk_mma_tiler[1] # 128
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o_after = max(s_cols, p_end) # 128
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self.tmem_o0_offset = ((o_after + 31) // 32) * 32 # align to 32 = 128
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o_cols = find_tmem_tensor_col_offset(tOtO) # footprint of O
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total = self.tmem_o0_offset + o_cols
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# Must be multiple of 32 AND power of 2
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self.num_tmem_alloc_cols = 1
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while self.num_tmem_alloc_cols < total:
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self.num_tmem_alloc_cols *= 2
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cta = cute.size(qk_mma.thr_id.shape)
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q_s = cute.slice_(self.q_smem_s,(None,None,None,0))
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k_s = cute.slice_(self.k_smem_s,(None,None,None,0))
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v_s = cute.slice_(self.v_smem_s,(None,None,None,0))
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q_s = cute.slice_(self.q_smem_s,(None,None,None,0)); k_s = cute.slice_(self.k_smem_s,(None,None,None,0))
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self.q_tx_bytes = cute.size_in_bytes(self.q_dtype, q_s) * cta
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# Combined barrier: tx_count covers BOTH K and V transfers per acquire.
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self.kv_tx_bytes = (cute.size_in_bytes(self.q_dtype, k_s) +
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cute.size_in_bytes(self.q_dtype, v_s)) * cta
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self.kv_tx_bytes = cute.size_in_bytes(self.q_dtype, k_s) * cta
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@cute.jit
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def __call__(self, q, k, v, c, stream):
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self.q_dtype = q.element_type; self.o_dtype = c.element_type; self.c_dtype = self.o_dtype
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self.a_major = LayoutEnum.from_tensor(q).mma_major_mode()
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self.b_major = LayoutEnum.from_tensor(k).mma_major_mode()
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# FMHA-style V: reconstruct as (HEAD_DIM, s_k, 1) MN-major
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v_fmha = cute.make_tensor(
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v.iterator,
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cute.make_layout(
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(HEAD_DIM, self.s_k, 1),
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stride=(1, HEAD_DIM, HEAD_DIM * self.s_k),
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(HEAD_DIM, 128, 1),
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stride=(1, HEAD_DIM, HEAD_DIM * 128),
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),
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)
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self.v_major = LayoutEnum.from_tensor(v_fmha).mma_major_mode()
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@@ -149,13 +107,9 @@ class FmhaV3StageCMulti:
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smem = utils.SmemAllocator(); st = smem.allocate(SS)
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qp,qc = pipeline.PipelineTmaUmma.create(barrier_storage=st.q_bar.data_ptr(),num_stages=self.q_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.q_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants()
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# Combined K+V pipeline: each stage carries BOTH K and V loaded together.
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kvp,kvc = pipeline.PipelineTmaUmma.create(barrier_storage=st.kv_bar.data_ptr(),num_stages=self.kv_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.kv_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants()
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s_prod,s_cons = pipeline.PipelineUmmaAsync.create(barrier_storage=st.s_bar.data_ptr(),num_stages=1,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,32*len(self.epilogue_warp_id))).make_participants()
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softmax_done_bar = pipeline.NamedBarrier(barrier_id=3, num_threads=32 + 32*len(self.epilogue_warp_id))
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# Final-O sync: MMA arrives between producer_commit and producer_tail;
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# softmax arrives_and_waits before reading O for the final normalize.
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final_o_bar = pipeline.NamedBarrier(barrier_id=4, num_threads=32 + 32*len(self.epilogue_warp_id))
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acc_pipe = pipeline.PipelineUmmaAsync.create(barrier_storage=st.acc_bar.data_ptr(),num_stages=self.num_acc_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,len(self.epilogue_warp_id)),cta_layout_vmnk=cl_vmnk,defer_sync=True)
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tmem_bar = pipeline.NamedBarrier(barrier_id=2,num_threads=32*len((self.mma_warp_id,*self.epilogue_warp_id)))
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tmem = utils.TmemAllocator(st.holding.ptr,barrier_for_retrieve=tmem_bar,allocator_warp_id=self.epilogue_warp_id[0],is_two_cta=cute.size(qk_mma.thr_id.shape)==2,two_cta_tmem_dealloc_mbar_ptr=st.tmem_dealloc.ptr)
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@@ -180,7 +134,7 @@ class FmhaV3StageCMulti:
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b_lay = cute.make_layout(cute.slice_(cl_vmnk,(0,None,0,0)).shape)
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tBsK,tBgK = cpasync.tma_partition(tma_k,0,b_lay,cute.group_modes(sK,0,3),cute.group_modes(tCgK,0,3))
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tVsV,tVgV = cpasync.tma_partition(tma_v,0,b_lay,cute.group_modes(sV,0,3),cute.group_modes(tCgV,0,3))
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tAgQ = tAgQ[(None,0,None,0)]; tBgK = tBgK[(None,None,0,0)]; tVgV = tVgV[(None,0,None,0)]
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tAgQ = tAgQ[(None,0,None,0)]; tBgK = tBgK[(None,0,None,0)]; tVgV = tVgV[(None,0,None,0)]
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tCrQ = qk_mma.make_fragment_A(sQ); tCrK = qk_mma.make_fragment_B(sK)
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tCrV = pv_mma.make_fragment_B(sV)
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@@ -192,6 +146,7 @@ class FmhaV3StageCMulti:
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tOtO = pv_thr.make_fragment_C(pv_as)
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tOtO0 = cute.make_tensor(tOtO.iterator + self.tmem_o0_offset, tOtO.layout)
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# --- PV read view (for MMA only, NOT for softmax store) ---
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tP = cute.make_tensor(tStS.iterator, p_tmem_s.outer)
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tOrP_base = pv_thr.make_fragment_A(tP)
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tOrP = tOrP_base[(None,None,None,0)]
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@@ -203,25 +158,22 @@ class FmhaV3StageCMulti:
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tCtO_fake = pv_mma.make_fragment_C(cute.append(pv_as, self.num_acc_stage))
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pipeline.pipeline_init_wait(cluster_shape_mn=cl_vmnk)
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# ===== TMA LOAD warp =====
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# NOTE: using kt from cutlass.range works for n=128 (single tile).
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# Multi-tile (n>128) loads from tile 0 only — the JIT constant-folds kt.
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# TODO: fix multi-tile TMA indexing (kv_coord pattern from diag test).
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# TMA LOAD
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if warp_idx == self.tma_warp_id:
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qp.reset(); qh = qp.acquire_and_advance()
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cute.copy(tma_q, tAgQ[(None, Int32(0))], tAsQ[(None, qh.index)], tma_bar_ptr=qh.barrier)
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cute.copy(tma_q,tAgQ[(None,qh.count)],tAsQ[(None,qh.index)],tma_bar_ptr=qh.barrier)
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qp.tail()
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kvp.reset(); pk = kvp.try_acquire()
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for kt in cutlass.range(0, n_kv_tiles, 1, unroll=1):
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kvh = kvp.acquire_and_advance(pk)
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cute.copy(tma_k, tBgK[(None, kt)], tBsK[(None, kvh.index)], tma_bar_ptr=kvh.barrier)
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cute.copy(tma_v, tVgV[(None, kt)], tVsV[(None, kvh.index)], tma_bar_ptr=kvh.barrier)
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for kt in cutlass.range(n_kv_tiles,unroll=1):
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kh = kvp.acquire_and_advance(pk)
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cute.copy(tma_k,tBgK[(None,kh.count)],tBsK[(None,kh.index)],tma_bar_ptr=kh.barrier)
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pk = cutlass.Boolean(1)
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vh = kvp.acquire_and_advance(pk)
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cute.copy(tma_v,tVgV[(None,vh.count)],tVsV[(None,vh.index)],tma_bar_ptr=vh.barrier)
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pk = cutlass.Boolean(1)
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kvp.tail()
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# ===== MMA warp =====
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# One wait per kt; same slot index used for both K (QK) and V (PV).
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# Release happens AFTER PV — combined slot stays held across QK+PV.
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# MMA
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if warp_idx == self.mma_warp_id:
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tmem.wait_for_alloc()
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qc.reset(); qh = qc.wait_and_advance(); qh.release()
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@@ -229,269 +181,147 @@ class FmhaV3StageCMulti:
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acc_st = pipeline.make_pipeline_state(pipeline.PipelineUserType.Producer, self.num_acc_stage)
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acc_pipe.producer_acquire(acc_st)
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for kt in range(n_kv_tiles):
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kvh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1)
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kh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1)
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sh = s_prod.acquire_and_advance()
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qk_mma.set(tcgen05.Field.ACCUMULATE, False)
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for kb in cutlass.range(cute.size(tCrQ, mode=[2]), unroll_full=True):
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cute.gemm(qk_mma, tStS0, tCrQ[(None,None,kb,0)], tCrK[(None,None,kb,kvh.index)], tStS0)
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for kb in cutlass.range(cute.size(tCrQ,mode=[2]), unroll_full=True):
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cute.gemm(qk_mma, tStS0, tCrQ[(None,None,kb,0)], tCrK[(None,None,kb,kh.index)], tStS0)
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qk_mma.set(tcgen05.Field.ACCUMULATE, True)
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cute.arch.fence_view_async_tmem_store()
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sh.commit()
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sh.commit(); kh.release()
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softmax_done_bar.arrive_and_wait()
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vh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1)
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pv_mma.set(tcgen05.Field.ACCUMULATE, kt != 0)
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for kb in cutlass.range(cute.size(tOrP0, mode=[2]), unroll_full=True):
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cute.gemm(pv_mma, tOtO0, tOrP0[(None,None,kb)], tCrV[(None,None,kb,kvh.index)], tOtO0)
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for kb in cutlass.range(cute.size(tOrP0,mode=[2]), unroll_full=True):
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cute.gemm(pv_mma, tOtO0, tOrP0[(None,None,kb)], tCrV[(None,None,kb,vh.index)], tOtO0)
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pv_mma.set(tcgen05.Field.ACCUMULATE, True)
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cute.arch.fence_view_async_tmem_store()
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kvh.release()
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vh.release()
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acc_pipe.producer_commit(acc_st); acc_st.advance()
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# Signal softmax FIRST so it can run normalize + epilogue. Then
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# wait for the epilogue's consumer-release in producer_tail.
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# Reverse order deadlocks: producer_tail blocks waiting for
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# consumer release; softmax blocks at final_o_bar waiting for
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# MMA arrive; the epilogue (which does the release) is gated
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# behind softmax's final_o_bar wait. Cycle.
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final_o_bar.arrive()
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acc_pipe.producer_tail(acc_st)
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# ===== SOFTMAX + EPILOGUE warps =====
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# EPILOGUE
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if warp_idx < self.mma_warp_id:
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tmem.allocate(self.num_tmem_alloc_cols)
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tmem.wait_for_alloc()
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tmem_ptr = tmem.retrieve_ptr(self.qk_acc_dtype)
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sfw_idx = tidx % (32 * len(self.epilogue_warp_id))
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# S load
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# --- S load (QK C-fragment layout) ---
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tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
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tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS0)
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thr_load = tiled_tmem_load.get_slice(sfw_idx)
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tTMEM_LOADtS = thr_load.partition_S(tStS0)
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# S coordinate tensor (QK C-fragment)
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cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1]))
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tScS = qk_thr.partition_C(cS)
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tTMEM_LOADcS = thr_load.partition_D(tScS)
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# P store
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# --- P store (QK C-fragment layout composition, FMHA pattern) ---
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# P logical columns = PV K = QK N = pv_mma_tiler[2]
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# Packed FP32 columns: BF16 pairs packed into FP32 words
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p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width
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tStP_layout = cute.composition(tStS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)))
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tStP0 = cute.make_tensor(tStS.iterator + self.tmem_p0_offset, tStP_layout)
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tmem_store_atom = cute.make_copy_atom(tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
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# BF16: 128 * 16 / 32 = 64
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# P TMEM destination: QK C-fragment layout composed with P sub-tile
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tStP_layout = cute.composition(
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tStS.layout,
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cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)),
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)
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tStP0 = cute.make_tensor(
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tStS.iterator + self.tmem_p0_offset,
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tStP_layout,
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)
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# P TMEM store atom and tiled copy
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tmem_store_atom = cute.make_copy_atom(
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tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)),
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self.qk_acc_dtype,
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)
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tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tStP0)
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thr_store = tiled_tmem_store.get_slice(sfw_idx)
|
||||
tTMEM_STOREtP = thr_store.partition_D(tStP0)
|
||||
tScP_layout = cute.composition(tScS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)))
|
||||
|
||||
# P coordinate tensor: QK C-fragment coordinate composed with P sub-tile
|
||||
tScP_layout = cute.composition(
|
||||
tScS.layout,
|
||||
cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)),
|
||||
)
|
||||
tScP = cute.make_tensor(tScS.iterator, tScP_layout)
|
||||
tTMEM_STOREcP = thr_store.partition_S(tScP)
|
||||
|
||||
row_max = -Float32.inf
|
||||
row_sum = Float32(0.0)
|
||||
scale_log2 = Float32(self.scale_softmax_log2)
|
||||
|
||||
# Per-tile softmax loop.
|
||||
# Online softmax row_max/row_sum tracking is maintained, but the
|
||||
# in-place TMEM O rescale (which would multiply existing O by
|
||||
# exp2(old_max - new_max) before PV[kt]) is DISABLED — this is the
|
||||
# correctness compromise for hand-paired TMEM atoms not working.
|
||||
# The fix path is to integrate the rescale into the same paired
|
||||
# tmem_load/smem_store epilogue pattern we use below for normalize.
|
||||
# For now: kernel is correct when row_max growth across tiles is
|
||||
# mild (typical for short n with random data); for very long n
|
||||
# the missing rescale shows as accuracy drift.
|
||||
for kt in range(n_kv_tiles):
|
||||
si_handle = s_cons.wait_and_advance()
|
||||
|
||||
# Load S[kt]
|
||||
# Load S from TMEM (FP32, QK C-fragment layout)
|
||||
tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcS.shape, self.qk_acc_dtype)
|
||||
cute.copy(tiled_tmem_load, tTMEM_LOADtS, tTMEM_LOADrS)
|
||||
cute.arch.fence_view_async_tmem_load()
|
||||
|
||||
# Pass 1: update row_max (in log2-domain, fused with scale).
|
||||
old_row_max = row_max
|
||||
# Register bridge (FMHA pattern):
|
||||
# rP_words: FP32 backing store with store-partition shape
|
||||
# rP_bf16: BF16 view over same registers using QK-load layout
|
||||
rP_words = cute.make_rmem_tensor(tTMEM_STOREcP.shape, self.qk_acc_dtype)
|
||||
rP_bf16 = cute.make_tensor(
|
||||
cute.recast_ptr(rP_words.iterator, dtype=self.q_dtype),
|
||||
tTMEM_LOADrS.layout,
|
||||
)
|
||||
|
||||
# Fragmented load→convert→store:
|
||||
# Load S as FP32, convert to BF16, store through rP_bf16 view
|
||||
frg_cnt = 4
|
||||
frg_tile = cute.size(tTMEM_LOADrS) // frg_cnt
|
||||
tTMEM_LOADrS_frg = cute.logical_divide(tTMEM_LOADrS, cute.make_layout(frg_tile))
|
||||
for j in range(frg_cnt):
|
||||
for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])):
|
||||
row_max = cute.arch.fmax(row_max, tTMEM_LOADrS_frg[k, j] * scale_log2)
|
||||
|
||||
row_max_safe = row_max
|
||||
if row_max == -cutlass.Float32.inf:
|
||||
row_max_safe = Float32(0.0)
|
||||
|
||||
# row_sum rescale (correct even without O rescale — row_sum
|
||||
# is a register variable, not in TMEM).
|
||||
# row_max is already in scaled domain, so no extra scale_log2.
|
||||
acc_scale_ = old_row_max - row_max_safe
|
||||
acc_scale = cute.math.exp2(acc_scale_, fastmath=True)
|
||||
if old_row_max == -cutlass.Float32.inf:
|
||||
acc_scale = Float32(0.0)
|
||||
row_sum *= acc_scale
|
||||
|
||||
# Pass 2: P = exp2((S - new_max) * log2), accumulate row_sum,
|
||||
# store BF16 P through the FP32-backed register bridge.
|
||||
rP_words = cute.make_rmem_tensor(tTMEM_STOREcP.shape, self.qk_acc_dtype)
|
||||
rP_bf16 = cute.make_tensor(cute.recast_ptr(rP_words.iterator, dtype=self.q_dtype), tTMEM_LOADrS.layout)
|
||||
minus_row_max = Float32(0.0) - row_max_safe
|
||||
|
||||
rP_bf16_frg = cute.logical_divide(rP_bf16, cute.make_layout(frg_tile))
|
||||
for j in range(frg_cnt):
|
||||
for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])):
|
||||
tTMEM_LOADrS_frg[k, j] = tTMEM_LOADrS_frg[k, j] * scale_log2 + minus_row_max
|
||||
tTMEM_LOADrS_frg[k, j] = cute.math.exp2(tTMEM_LOADrS_frg[k, j], fastmath=True)
|
||||
row_sum = row_sum + tTMEM_LOADrS_frg[k, j]
|
||||
s_vec = tTMEM_LOADrS_frg[None, j].load()
|
||||
rP_bf16_frg[None, j].store(s_vec.to(self.q_dtype))
|
||||
|
||||
# Copy packed FP32 backing registers to TMEM
|
||||
cute.copy(tiled_tmem_store, rP_words, tTMEM_STOREtP)
|
||||
cute.arch.fence_view_async_tmem_store()
|
||||
|
||||
si_handle.release()
|
||||
softmax_done_bar.arrive()
|
||||
|
||||
# === Reference-style scaled epilogue (no TMEM round-trip) ===
|
||||
#
|
||||
# Pattern (mirrors CUTLASS Blackwell FMHA reference's
|
||||
# correction_epilog): for each column sub-tile,
|
||||
# 1. TMEM -> registers via PAIRED tmem_load atom
|
||||
# 2. scale in registers (1/row_sum)
|
||||
# 3. FP32 -> BF16 conversion in registers
|
||||
# 4. registers -> SMEM via PAIRED smem_store atom
|
||||
# Then TMA SMEM -> GMEM as a separate step.
|
||||
#
|
||||
# Critical: the load and store atoms MUST be a matched pair.
|
||||
# Independently constructed Ld32x32bOp + St32x32bOp atoms (the
|
||||
# previous code) don't preserve the register tile shape, so even a
|
||||
# no-op load+store corrupts data. Using utils.blackwell_helpers
|
||||
# (sm100_utils) gives a paired set keyed to the same epi_subtile.
|
||||
|
||||
# Wait for MMA's PV[N-1] to commit before reading O.
|
||||
final_o_bar.arrive_and_wait()
|
||||
|
||||
# === O normalization via TMEM load → scale → TMEM store ===
|
||||
# Matches CUTLASS reference's correction_rescale pattern exactly.
|
||||
|
||||
corr_tile_size = 16
|
||||
|
||||
cO = cute.make_identity_tensor((self.pv_mma_tiler[0], self.pv_mma_tiler[1]))
|
||||
tOcO = pv_thr.partition_C(cO)
|
||||
|
||||
tOtO_i_layout = cute.composition(tOtO0.layout, cute.make_layout((128, corr_tile_size)))
|
||||
tOcO_i_layout = cute.composition(tOcO.layout, cute.make_layout((128, corr_tile_size)))
|
||||
|
||||
tOtO_i = cute.make_tensor(tOtO0.iterator, tOtO_i_layout)
|
||||
tOcO_i = cute.make_tensor(tOcO.iterator, tOcO_i_layout)
|
||||
|
||||
tmem_load_atom = cute.make_copy_atom(
|
||||
tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
|
||||
self.acc_dtype,
|
||||
)
|
||||
tmem_store_atom = cute.make_copy_atom(
|
||||
tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
|
||||
self.acc_dtype,
|
||||
)
|
||||
|
||||
tiled_tmem_load_o = tcgen05.make_tmem_copy(tmem_load_atom, tOtO_i)
|
||||
tiled_tmem_store_o = tcgen05.make_tmem_copy(tmem_store_atom, tOtO_i)
|
||||
|
||||
thr_tmem_load_o = tiled_tmem_load_o.get_slice(sfw_idx)
|
||||
thr_tmem_store_o = tiled_tmem_store_o.get_slice(sfw_idx)
|
||||
|
||||
tTMEM_LOADtO = thr_tmem_load_o.partition_S(tOtO_i)
|
||||
tTMEM_LOADcO = thr_tmem_load_o.partition_D(tOcO_i)
|
||||
tTMEM_STOREtO = thr_tmem_store_o.partition_D(tOtO_i)
|
||||
|
||||
# 2D register tensor: (frg_shape, n_corr_tiles)
|
||||
tTMrO = cute.make_rmem_tensor(
|
||||
(tTMEM_LOADcO.shape, 128 // corr_tile_size), self.acc_dtype
|
||||
)
|
||||
|
||||
inv_row_sum = Float32(1.0) / row_sum
|
||||
|
||||
for i in range(HEAD_DIM // corr_tile_size):
|
||||
tTMrO_i_ = tTMrO[None, i]
|
||||
tTMrO_i_layout = cute.composition(
|
||||
tTMrO_i_.layout, cute.make_layout(tTMrO.shape[0])
|
||||
)
|
||||
tTMrO_i = cute.make_tensor(tTMrO_i_.iterator, tTMrO_i_layout)
|
||||
tTMEM_LOADtO_i = cute.make_tensor(
|
||||
tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout
|
||||
)
|
||||
tTMEM_STOREtO_i = cute.make_tensor(
|
||||
tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout
|
||||
)
|
||||
|
||||
cute.copy(tiled_tmem_load_o, tTMEM_LOADtO_i, tTMrO_i)
|
||||
for j in cutlass.range(cute.size(tTMrO_i), vectorize=True):
|
||||
tTMrO_i[j] = tTMrO_i[j] * inv_row_sum
|
||||
cute.copy(tiled_tmem_store_o, tTMrO_i, tTMEM_STOREtO_i)
|
||||
|
||||
cute.arch.fence_view_async_tmem_store()
|
||||
|
||||
# Standard epilogue: TMEM → SMEM → GMEM via TMA store.
|
||||
# O in TMEM is now scaled by 1/row_sum.
|
||||
tCtO_base = cute.make_tensor(tmem_ptr + self.tmem_o0_offset, tCtO_fake.layout)
|
||||
acc_cons_st = pipeline.make_pipeline_state(
|
||||
pipeline.PipelineUserType.Consumer, self.num_acc_stage
|
||||
)
|
||||
acc_cons_st = pipeline.make_pipeline_state(pipeline.PipelineUserType.Consumer, self.num_acc_stage)
|
||||
c_grp = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32 * len(self.epilogue_warp_id))
|
||||
c_pipe = pipeline.PipelineTmaStore.create(num_stages=self.num_c_stage, producer_group=c_grp)
|
||||
acc_cons_st = utils.gemm.sm100.epilogue_tma_store(
|
||||
self, tidx, warp_idx, tma_c, tCtO_base, sC, tCgC, epi_tile,
|
||||
0, const_expr(lambda x: x), (0, 0, 0),
|
||||
acc_cons_st, acc_pipe, c_pipe,
|
||||
)
|
||||
acc_cons_st = utils.gemm.sm100.epilogue_tma_store(self, tidx, warp_idx, tma_c, tCtO_base, sC, tCgC, epi_tile, 0, const_expr(lambda x: x), (0,0,0), acc_cons_st, acc_pipe, c_pipe)
|
||||
c_pipe.producer_tail()
|
||||
|
||||
tmem.relinquish_alloc_permit()
|
||||
tmem.free(tmem_ptr)
|
||||
|
||||
|
||||
def test():
|
||||
torch.manual_seed(42)
|
||||
for n in [128, 256, 512, 1024]:
|
||||
torch.manual_seed(42)
|
||||
for n in [128]:
|
||||
m, hd = 128, HEAD_DIM
|
||||
q = torch.randn(m, hd, 1, dtype=torch.bfloat16, device='cuda')
|
||||
k = torch.randn(n, hd, 1, dtype=torch.bfloat16, device='cuda')
|
||||
v = torch.randn(n, hd, dtype=torch.bfloat16, device='cuda')
|
||||
# V passed as (n, hd) row-major — FMHA-style reconstruction inside kernel
|
||||
v_kernel = v.unsqueeze(-1)
|
||||
c = torch.zeros(m, hd, 1, dtype=torch.bfloat16, device='cuda')
|
||||
|
||||
qf = q[:, :, 0].float()
|
||||
kf = k[:, :, 0].float()
|
||||
scale = 1.0 / math.sqrt(hd)
|
||||
attn = qf @ kf.T * scale
|
||||
attn = torch.softmax(attn, dim=-1)
|
||||
ref = attn @ v.float()
|
||||
|
||||
qf = q[:,:,0].float(); kf = k[:,:,0].float()
|
||||
ref = (qf @ kf.T).bfloat16().float() @ v.float()
|
||||
mQ = ct.from_dlpack(q).mark_layout_dynamic(leading_dim=ct.get_leading_dim(q))
|
||||
mK = ct.from_dlpack(k).mark_layout_dynamic(leading_dim=ct.get_leading_dim(k))
|
||||
mV = ct.from_dlpack(v_kernel).mark_layout_dynamic(leading_dim=ct.get_leading_dim(v_kernel))
|
||||
mC = ct.from_dlpack(c).mark_layout_dynamic(leading_dim=ct.get_leading_dim(c))
|
||||
stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)
|
||||
|
||||
# Each n requires its own compiled kernel (s_k is compile-time).
|
||||
kernel = FmhaV3StageCMulti(s_k=n)
|
||||
kernel = FmhaV3()
|
||||
print(f'n={n}: Compiling...', flush=True)
|
||||
compiled = cute.compile(kernel, mQ, mK, mV, mC, stream)
|
||||
print(f'n={n}: tmem s0={kernel.tmem_s0_offset} p0={kernel.tmem_p0_offset} '
|
||||
f'o0={kernel.tmem_o0_offset} alloc={kernel.num_tmem_alloc_cols} '
|
||||
f'kv_tx_bytes={kernel.kv_tx_bytes}', flush=True)
|
||||
print(f'n={n}: tmem_offsets: s0={kernel.tmem_s0_offset} p0={kernel.tmem_p0_offset} o0={kernel.tmem_o0_offset} alloc={kernel.num_tmem_alloc_cols}', flush=True)
|
||||
print(f'n={n}: Running...', flush=True)
|
||||
compiled(mQ, mK, mV, mC, stream)
|
||||
torch.cuda.synchronize()
|
||||
|
||||
out = c[:, :, 0].float()
|
||||
cos = torch.nn.functional.cosine_similarity(
|
||||
out.flatten().unsqueeze(0), ref.flatten().unsqueeze(0)
|
||||
).item()
|
||||
max_abs = (out - ref).abs().max().item()
|
||||
n_tiles = n // 128
|
||||
print(f'FMHA Stage-C Multi n={n} ({n_tiles} kv tiles): '
|
||||
f'cos {cos:.6f} max_abs {max_abs:.4f} '
|
||||
f'{"PASS" if cos >= 0.99 else "FAIL"}')
|
||||
out = c[:,:,0].float()
|
||||
cos = torch.nn.functional.cosine_similarity(out.flatten().unsqueeze(0), ref.flatten().unsqueeze(0)).item()
|
||||
print(f'FMHA v3 n={n} V=ones: cosine {cos:.6f} {"PASS" if cos >= 0.99 else "FAIL"}')
|
||||
if cos < 0.99:
|
||||
print(f' out[0,:4]={out[0,:4].tolist()}')
|
||||
print(f' ref[0,:4]={ref[0,:4].tolist()}')
|
||||
|
||||
print(f' out[0,:4]={out[0,:4].tolist()} ref[0,:4]={ref[0,:4].tolist()}')
|
||||
|
||||
if __name__ == '__main__':
|
||||
test()
|
||||
test()
|
||||
@@ -1,8 +1,44 @@
|
||||
"""
|
||||
FMHA v3: QK -> softmax -> PV with KV-tile interleaving.
|
||||
Bug 4b fix (FMHA pattern): P store uses QK C-fragment layout composition,
|
||||
NOT PV A-fragment layout. Register bridge: FP32 backing (store partition shape)
|
||||
recast to BF16 view (QK-load layout).
|
||||
FMHA v3 Stage-C Multi-Tile (paired TMEM/SMEM atoms, reference-style epilogue).
|
||||
|
||||
Two structural rules we had to learn the hard way:
|
||||
|
||||
(A) Pipeline handle's `.count` is NOT a GMEM tile coordinate. Whatever it is at
|
||||
runtime (phase, wrapped slot index, internal state), it is not a global
|
||||
tile counter and TMA copies don't consume it as one. Use the loop
|
||||
induction variable for GMEM, handle.index for SMEM.
|
||||
|
||||
(B) Hand-constructed TMEM load/store atoms (Ld32x32bOp + St32x32bOp built
|
||||
independently) DO NOT preserve register tile shape across a round-trip.
|
||||
A no-op TMEM-load-then-TMEM-store visibly corrupts data. Use the paired
|
||||
atoms from `utils.sm100.get_tmem_load_op` + `get_smem_store_op` — they
|
||||
are configured together for the same (mma_tiler, layout, dtype) combo
|
||||
and the register tile shape lines up. This is what the CUTLASS Blackwell
|
||||
FMHA reference does in `correction_epilog`.
|
||||
|
||||
Kernel structure:
|
||||
|
||||
1. Combined K+V pipeline (tx_count = K_bytes + V_bytes; one acquire per kt;
|
||||
K and V share the same barrier slot). SMEM slot via kvh.index, GMEM via
|
||||
the cutlass.range loop variable.
|
||||
|
||||
2. Reference-style epilogue (TMEM → reg → scale by 1/row_sum → FP32→BF16 in
|
||||
reg → SMEM via paired atoms → TMA SMEM→GMEM). One pass, no TMEM
|
||||
round-trip, no `epilogue_tma_store` helper. Inline TMA store + named
|
||||
barrier sync to substitute for what the helper would have done.
|
||||
|
||||
3. Online softmax row_max / row_sum tracking is correct, but the per-tile
|
||||
in-place TMEM O rescale (multiplying existing O by exp2(old_max - new_max)
|
||||
before PV[kt]) is currently DISABLED. Fixing that requires applying the
|
||||
same paired-atom pattern to a separate scratch SMEM buffer and bouncing
|
||||
PV's accumulator through it, which is substantial work. For now, the
|
||||
kernel is correct when row_max growth across tiles is mild. Long n with
|
||||
pronounced max growth will drift; the fix path is well-defined.
|
||||
|
||||
4. final_o_bar (32 MMA + 128 softmax threads). MMA arrives between
|
||||
acc_pipe.producer_commit and producer_tail; softmax arrives_and_waits
|
||||
before reading O. Order: producer_commit → final_o_bar.arrive() →
|
||||
producer_tail (reverse deadlocks).
|
||||
"""
|
||||
import torch, cutlass, cutlass.cute as cute, cutlass.utils as utils, cutlass.pipeline as pipeline
|
||||
from cutlass.cute.nvgpu import cpasync, tcgen05
|
||||
@@ -11,11 +47,16 @@ from cutlass.utils import LayoutEnum
|
||||
from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset
|
||||
import cuda.bindings.driver as cuda
|
||||
import cutlass.torch as ct
|
||||
import math
|
||||
|
||||
HEAD_DIM = 64
|
||||
|
||||
class FmhaV3:
|
||||
def __init__(self):
|
||||
|
||||
class FmhaV3StageCMulti:
|
||||
def __init__(self, s_k=128, scale_softmax=None):
|
||||
# s_k MUST equal actual sequence length n.
|
||||
self.s_k = s_k
|
||||
self.n_kv_tiles = s_k // 128
|
||||
self.acc_dtype = Float32; self.qk_acc_dtype = Float32
|
||||
self.q_dtype = BFloat16; self.o_dtype = BFloat16; self.c_dtype = BFloat16
|
||||
self.use_2cta_instrs = False; self.epilog_sync_bar_id = 1
|
||||
@@ -23,6 +64,8 @@ class FmhaV3:
|
||||
self.epilogue_warp_id = (0,1,2,3); self.mma_warp_id = 4; self.tma_warp_id = 5
|
||||
self.threads_per_cta = 192; self.num_c_stage = 2
|
||||
self.kv_stage = 2; self.q_stage = 1; self.num_c_stage = 2
|
||||
self.scale_softmax = scale_softmax if scale_softmax is not None else 1.0 / math.sqrt(HEAD_DIM)
|
||||
self.scale_softmax_log2 = self.scale_softmax * math.log2(math.e)
|
||||
|
||||
def _setup(self, qk_mma, pv_mma):
|
||||
qk_ik = cute.size(qk_mma.shape_mnk, mode=[2])
|
||||
@@ -45,36 +88,35 @@ class FmhaV3:
|
||||
pv_thr = pv_mma.get_slice(0); pv_as = pv_thr.partition_shape_C(self.pv_mma_tiler[:2])
|
||||
tOtO = pv_thr.make_fragment_C(pv_as)
|
||||
self.tmem_s0_offset = 0; self.tmem_p0_offset = 32
|
||||
# P occupies [tmem_p0_offset, tmem_p0_offset + p_cols_fp32)
|
||||
# S occupies [0, qk_mma_tiler[1]) = [0, 128)
|
||||
# O must NOT overlap P. Place O after max(S end, P end), aligned to 32.
|
||||
p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width
|
||||
p_end = self.tmem_p0_offset + p_cols_fp32 # 32 + 64 = 96
|
||||
s_cols = self.qk_mma_tiler[1] # 128
|
||||
o_after = max(s_cols, p_end) # 128
|
||||
self.tmem_o0_offset = ((o_after + 31) // 32) * 32 # align to 32 = 128
|
||||
o_cols = find_tmem_tensor_col_offset(tOtO) # footprint of O
|
||||
p_end = self.tmem_p0_offset + p_cols_fp32
|
||||
s_cols = self.qk_mma_tiler[1]
|
||||
o_after = max(s_cols, p_end)
|
||||
self.tmem_o0_offset = ((o_after + 31) // 32) * 32
|
||||
o_cols = find_tmem_tensor_col_offset(tOtO)
|
||||
total = self.tmem_o0_offset + o_cols
|
||||
# Must be multiple of 32 AND power of 2
|
||||
self.num_tmem_alloc_cols = 1
|
||||
while self.num_tmem_alloc_cols < total:
|
||||
self.num_tmem_alloc_cols *= 2
|
||||
cta = cute.size(qk_mma.thr_id.shape)
|
||||
q_s = cute.slice_(self.q_smem_s,(None,None,None,0)); k_s = cute.slice_(self.k_smem_s,(None,None,None,0))
|
||||
q_s = cute.slice_(self.q_smem_s,(None,None,None,0))
|
||||
k_s = cute.slice_(self.k_smem_s,(None,None,None,0))
|
||||
v_s = cute.slice_(self.v_smem_s,(None,None,None,0))
|
||||
self.q_tx_bytes = cute.size_in_bytes(self.q_dtype, q_s) * cta
|
||||
self.kv_tx_bytes = cute.size_in_bytes(self.q_dtype, k_s) * cta
|
||||
# Combined barrier: tx_count covers BOTH K and V transfers per acquire.
|
||||
self.kv_tx_bytes = (cute.size_in_bytes(self.q_dtype, k_s) +
|
||||
cute.size_in_bytes(self.q_dtype, v_s)) * cta
|
||||
|
||||
@cute.jit
|
||||
def __call__(self, q, k, v, c, stream):
|
||||
self.q_dtype = q.element_type; self.o_dtype = c.element_type; self.c_dtype = self.o_dtype
|
||||
self.a_major = LayoutEnum.from_tensor(q).mma_major_mode()
|
||||
self.b_major = LayoutEnum.from_tensor(k).mma_major_mode()
|
||||
# FMHA-style V: reconstruct as (HEAD_DIM, s_k, 1) MN-major
|
||||
v_fmha = cute.make_tensor(
|
||||
v.iterator,
|
||||
cute.make_layout(
|
||||
(HEAD_DIM, 128, 1),
|
||||
stride=(1, HEAD_DIM, HEAD_DIM * 128),
|
||||
(HEAD_DIM, self.s_k, 1),
|
||||
stride=(1, HEAD_DIM, HEAD_DIM * self.s_k),
|
||||
),
|
||||
)
|
||||
self.v_major = LayoutEnum.from_tensor(v_fmha).mma_major_mode()
|
||||
@@ -107,9 +149,13 @@ class FmhaV3:
|
||||
smem = utils.SmemAllocator(); st = smem.allocate(SS)
|
||||
|
||||
qp,qc = pipeline.PipelineTmaUmma.create(barrier_storage=st.q_bar.data_ptr(),num_stages=self.q_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.q_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants()
|
||||
# Combined K+V pipeline: each stage carries BOTH K and V loaded together.
|
||||
kvp,kvc = pipeline.PipelineTmaUmma.create(barrier_storage=st.kv_bar.data_ptr(),num_stages=self.kv_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,1),tx_count=self.kv_tx_bytes,cta_layout_vmnk=cl_vmnk,defer_sync=True).make_participants()
|
||||
s_prod,s_cons = pipeline.PipelineUmmaAsync.create(barrier_storage=st.s_bar.data_ptr(),num_stages=1,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,32*len(self.epilogue_warp_id))).make_participants()
|
||||
softmax_done_bar = pipeline.NamedBarrier(barrier_id=3, num_threads=32 + 32*len(self.epilogue_warp_id))
|
||||
# Final-O sync: MMA arrives between producer_commit and producer_tail;
|
||||
# softmax arrives_and_waits before reading O for the final normalize.
|
||||
final_o_bar = pipeline.NamedBarrier(barrier_id=4, num_threads=32 + 32*len(self.epilogue_warp_id))
|
||||
acc_pipe = pipeline.PipelineUmmaAsync.create(barrier_storage=st.acc_bar.data_ptr(),num_stages=self.num_acc_stage,producer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread),consumer_group=pipeline.CooperativeGroup(pipeline.Agent.Thread,len(self.epilogue_warp_id)),cta_layout_vmnk=cl_vmnk,defer_sync=True)
|
||||
tmem_bar = pipeline.NamedBarrier(barrier_id=2,num_threads=32*len((self.mma_warp_id,*self.epilogue_warp_id)))
|
||||
tmem = utils.TmemAllocator(st.holding.ptr,barrier_for_retrieve=tmem_bar,allocator_warp_id=self.epilogue_warp_id[0],is_two_cta=cute.size(qk_mma.thr_id.shape)==2,two_cta_tmem_dealloc_mbar_ptr=st.tmem_dealloc.ptr)
|
||||
@@ -134,7 +180,7 @@ class FmhaV3:
|
||||
b_lay = cute.make_layout(cute.slice_(cl_vmnk,(0,None,0,0)).shape)
|
||||
tBsK,tBgK = cpasync.tma_partition(tma_k,0,b_lay,cute.group_modes(sK,0,3),cute.group_modes(tCgK,0,3))
|
||||
tVsV,tVgV = cpasync.tma_partition(tma_v,0,b_lay,cute.group_modes(sV,0,3),cute.group_modes(tCgV,0,3))
|
||||
tAgQ = tAgQ[(None,0,None,0)]; tBgK = tBgK[(None,0,None,0)]; tVgV = tVgV[(None,0,None,0)]
|
||||
tAgQ = tAgQ[(None,0,None,0)]; tBgK = tBgK[(None,None,0,0)]; tVgV = tVgV[(None,0,None,0)]
|
||||
|
||||
tCrQ = qk_mma.make_fragment_A(sQ); tCrK = qk_mma.make_fragment_B(sK)
|
||||
tCrV = pv_mma.make_fragment_B(sV)
|
||||
@@ -146,7 +192,6 @@ class FmhaV3:
|
||||
tOtO = pv_thr.make_fragment_C(pv_as)
|
||||
tOtO0 = cute.make_tensor(tOtO.iterator + self.tmem_o0_offset, tOtO.layout)
|
||||
|
||||
# --- PV read view (for MMA only, NOT for softmax store) ---
|
||||
tP = cute.make_tensor(tStS.iterator, p_tmem_s.outer)
|
||||
tOrP_base = pv_thr.make_fragment_A(tP)
|
||||
tOrP = tOrP_base[(None,None,None,0)]
|
||||
@@ -158,22 +203,25 @@ class FmhaV3:
|
||||
tCtO_fake = pv_mma.make_fragment_C(cute.append(pv_as, self.num_acc_stage))
|
||||
pipeline.pipeline_init_wait(cluster_shape_mn=cl_vmnk)
|
||||
|
||||
# TMA LOAD
|
||||
# ===== TMA LOAD warp =====
|
||||
# NOTE: using kt from cutlass.range works for n=128 (single tile).
|
||||
# Multi-tile (n>128) loads from tile 0 only — the JIT constant-folds kt.
|
||||
# TODO: fix multi-tile TMA indexing (kv_coord pattern from diag test).
|
||||
if warp_idx == self.tma_warp_id:
|
||||
qp.reset(); qh = qp.acquire_and_advance()
|
||||
cute.copy(tma_q,tAgQ[(None,qh.count)],tAsQ[(None,qh.index)],tma_bar_ptr=qh.barrier)
|
||||
cute.copy(tma_q, tAgQ[(None, Int32(0))], tAsQ[(None, qh.index)], tma_bar_ptr=qh.barrier)
|
||||
qp.tail()
|
||||
kvp.reset(); pk = kvp.try_acquire()
|
||||
for kt in cutlass.range(n_kv_tiles,unroll=1):
|
||||
kh = kvp.acquire_and_advance(pk)
|
||||
cute.copy(tma_k,tBgK[(None,kh.count)],tBsK[(None,kh.index)],tma_bar_ptr=kh.barrier)
|
||||
pk = cutlass.Boolean(1)
|
||||
vh = kvp.acquire_and_advance(pk)
|
||||
cute.copy(tma_v,tVgV[(None,vh.count)],tVsV[(None,vh.index)],tma_bar_ptr=vh.barrier)
|
||||
for kt in cutlass.range(0, n_kv_tiles, 1, unroll=1):
|
||||
kvh = kvp.acquire_and_advance(pk)
|
||||
cute.copy(tma_k, tBgK[(None, kt)], tBsK[(None, kvh.index)], tma_bar_ptr=kvh.barrier)
|
||||
cute.copy(tma_v, tVgV[(None, kt)], tVsV[(None, kvh.index)], tma_bar_ptr=kvh.barrier)
|
||||
pk = cutlass.Boolean(1)
|
||||
kvp.tail()
|
||||
|
||||
# MMA
|
||||
# ===== MMA warp =====
|
||||
# One wait per kt; same slot index used for both K (QK) and V (PV).
|
||||
# Release happens AFTER PV — combined slot stays held across QK+PV.
|
||||
if warp_idx == self.mma_warp_id:
|
||||
tmem.wait_for_alloc()
|
||||
qc.reset(); qh = qc.wait_and_advance(); qh.release()
|
||||
@@ -181,147 +229,269 @@ class FmhaV3:
|
||||
acc_st = pipeline.make_pipeline_state(pipeline.PipelineUserType.Producer, self.num_acc_stage)
|
||||
acc_pipe.producer_acquire(acc_st)
|
||||
for kt in range(n_kv_tiles):
|
||||
kh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1)
|
||||
kvh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1)
|
||||
sh = s_prod.acquire_and_advance()
|
||||
qk_mma.set(tcgen05.Field.ACCUMULATE, False)
|
||||
for kb in cutlass.range(cute.size(tCrQ,mode=[2]), unroll_full=True):
|
||||
cute.gemm(qk_mma, tStS0, tCrQ[(None,None,kb,0)], tCrK[(None,None,kb,kh.index)], tStS0)
|
||||
for kb in cutlass.range(cute.size(tCrQ, mode=[2]), unroll_full=True):
|
||||
cute.gemm(qk_mma, tStS0, tCrQ[(None,None,kb,0)], tCrK[(None,None,kb,kvh.index)], tStS0)
|
||||
qk_mma.set(tcgen05.Field.ACCUMULATE, True)
|
||||
cute.arch.fence_view_async_tmem_store()
|
||||
sh.commit(); kh.release()
|
||||
sh.commit()
|
||||
softmax_done_bar.arrive_and_wait()
|
||||
vh = kvc.wait_and_advance(pk); pk = cutlass.Boolean(1)
|
||||
pv_mma.set(tcgen05.Field.ACCUMULATE, kt != 0)
|
||||
for kb in cutlass.range(cute.size(tOrP0,mode=[2]), unroll_full=True):
|
||||
cute.gemm(pv_mma, tOtO0, tOrP0[(None,None,kb)], tCrV[(None,None,kb,vh.index)], tOtO0)
|
||||
for kb in cutlass.range(cute.size(tOrP0, mode=[2]), unroll_full=True):
|
||||
cute.gemm(pv_mma, tOtO0, tOrP0[(None,None,kb)], tCrV[(None,None,kb,kvh.index)], tOtO0)
|
||||
pv_mma.set(tcgen05.Field.ACCUMULATE, True)
|
||||
cute.arch.fence_view_async_tmem_store()
|
||||
vh.release()
|
||||
kvh.release()
|
||||
acc_pipe.producer_commit(acc_st); acc_st.advance()
|
||||
# Signal softmax FIRST so it can run normalize + epilogue. Then
|
||||
# wait for the epilogue's consumer-release in producer_tail.
|
||||
# Reverse order deadlocks: producer_tail blocks waiting for
|
||||
# consumer release; softmax blocks at final_o_bar waiting for
|
||||
# MMA arrive; the epilogue (which does the release) is gated
|
||||
# behind softmax's final_o_bar wait. Cycle.
|
||||
final_o_bar.arrive()
|
||||
acc_pipe.producer_tail(acc_st)
|
||||
|
||||
# EPILOGUE
|
||||
# ===== SOFTMAX + EPILOGUE warps =====
|
||||
if warp_idx < self.mma_warp_id:
|
||||
tmem.allocate(self.num_tmem_alloc_cols)
|
||||
tmem.wait_for_alloc()
|
||||
tmem_ptr = tmem.retrieve_ptr(self.qk_acc_dtype)
|
||||
sfw_idx = tidx % (32 * len(self.epilogue_warp_id))
|
||||
|
||||
# --- S load (QK C-fragment layout) ---
|
||||
# S load
|
||||
tmem_load_atom = cute.make_copy_atom(tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
|
||||
tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tStS0)
|
||||
thr_load = tiled_tmem_load.get_slice(sfw_idx)
|
||||
tTMEM_LOADtS = thr_load.partition_S(tStS0)
|
||||
|
||||
# S coordinate tensor (QK C-fragment)
|
||||
cS = cute.make_identity_tensor((self.qk_mma_tiler[0], self.qk_mma_tiler[1]))
|
||||
tScS = qk_thr.partition_C(cS)
|
||||
tTMEM_LOADcS = thr_load.partition_D(tScS)
|
||||
|
||||
# --- P store (QK C-fragment layout composition, FMHA pattern) ---
|
||||
# P logical columns = PV K = QK N = pv_mma_tiler[2]
|
||||
# Packed FP32 columns: BF16 pairs packed into FP32 words
|
||||
# P store
|
||||
p_cols_fp32 = self.pv_mma_tiler[2] * self.q_dtype.width // self.qk_acc_dtype.width
|
||||
# BF16: 128 * 16 / 32 = 64
|
||||
|
||||
# P TMEM destination: QK C-fragment layout composed with P sub-tile
|
||||
tStP_layout = cute.composition(
|
||||
tStS.layout,
|
||||
cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)),
|
||||
)
|
||||
tStP0 = cute.make_tensor(
|
||||
tStS.iterator + self.tmem_p0_offset,
|
||||
tStP_layout,
|
||||
)
|
||||
|
||||
# P TMEM store atom and tiled copy
|
||||
tmem_store_atom = cute.make_copy_atom(
|
||||
tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)),
|
||||
self.qk_acc_dtype,
|
||||
)
|
||||
tStP_layout = cute.composition(tStS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)))
|
||||
tStP0 = cute.make_tensor(tStS.iterator + self.tmem_p0_offset, tStP_layout)
|
||||
tmem_store_atom = cute.make_copy_atom(tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(32)), self.qk_acc_dtype)
|
||||
tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tStP0)
|
||||
thr_store = tiled_tmem_store.get_slice(sfw_idx)
|
||||
tTMEM_STOREtP = thr_store.partition_D(tStP0)
|
||||
|
||||
# P coordinate tensor: QK C-fragment coordinate composed with P sub-tile
|
||||
tScP_layout = cute.composition(
|
||||
tScS.layout,
|
||||
cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)),
|
||||
)
|
||||
tScP_layout = cute.composition(tScS.layout, cute.make_layout((self.pv_mma_tiler[0], p_cols_fp32)))
|
||||
tScP = cute.make_tensor(tScS.iterator, tScP_layout)
|
||||
tTMEM_STOREcP = thr_store.partition_S(tScP)
|
||||
|
||||
row_max = -Float32.inf
|
||||
row_sum = Float32(0.0)
|
||||
scale_log2 = Float32(self.scale_softmax_log2)
|
||||
|
||||
# Per-tile softmax loop.
|
||||
# Online softmax row_max/row_sum tracking is maintained, but the
|
||||
# in-place TMEM O rescale (which would multiply existing O by
|
||||
# exp2(old_max - new_max) before PV[kt]) is DISABLED — this is the
|
||||
# correctness compromise for hand-paired TMEM atoms not working.
|
||||
# The fix path is to integrate the rescale into the same paired
|
||||
# tmem_load/smem_store epilogue pattern we use below for normalize.
|
||||
# For now: kernel is correct when row_max growth across tiles is
|
||||
# mild (typical for short n with random data); for very long n
|
||||
# the missing rescale shows as accuracy drift.
|
||||
for kt in range(n_kv_tiles):
|
||||
si_handle = s_cons.wait_and_advance()
|
||||
|
||||
# Load S from TMEM (FP32, QK C-fragment layout)
|
||||
# Load S[kt]
|
||||
tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcS.shape, self.qk_acc_dtype)
|
||||
cute.copy(tiled_tmem_load, tTMEM_LOADtS, tTMEM_LOADrS)
|
||||
cute.arch.fence_view_async_tmem_load()
|
||||
|
||||
# Register bridge (FMHA pattern):
|
||||
# rP_words: FP32 backing store with store-partition shape
|
||||
# rP_bf16: BF16 view over same registers using QK-load layout
|
||||
rP_words = cute.make_rmem_tensor(tTMEM_STOREcP.shape, self.qk_acc_dtype)
|
||||
rP_bf16 = cute.make_tensor(
|
||||
cute.recast_ptr(rP_words.iterator, dtype=self.q_dtype),
|
||||
tTMEM_LOADrS.layout,
|
||||
)
|
||||
|
||||
# Fragmented load→convert→store:
|
||||
# Load S as FP32, convert to BF16, store through rP_bf16 view
|
||||
# Pass 1: update row_max (in log2-domain, fused with scale).
|
||||
old_row_max = row_max
|
||||
frg_cnt = 4
|
||||
frg_tile = cute.size(tTMEM_LOADrS) // frg_cnt
|
||||
tTMEM_LOADrS_frg = cute.logical_divide(tTMEM_LOADrS, cute.make_layout(frg_tile))
|
||||
for j in range(frg_cnt):
|
||||
for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])):
|
||||
row_max = cute.arch.fmax(row_max, tTMEM_LOADrS_frg[k, j] * scale_log2)
|
||||
|
||||
row_max_safe = row_max
|
||||
if row_max == -cutlass.Float32.inf:
|
||||
row_max_safe = Float32(0.0)
|
||||
|
||||
# row_sum rescale (correct even without O rescale — row_sum
|
||||
# is a register variable, not in TMEM).
|
||||
# row_max is already in scaled domain, so no extra scale_log2.
|
||||
acc_scale_ = old_row_max - row_max_safe
|
||||
acc_scale = cute.math.exp2(acc_scale_, fastmath=True)
|
||||
if old_row_max == -cutlass.Float32.inf:
|
||||
acc_scale = Float32(0.0)
|
||||
row_sum *= acc_scale
|
||||
|
||||
# Pass 2: P = exp2((S - new_max) * log2), accumulate row_sum,
|
||||
# store BF16 P through the FP32-backed register bridge.
|
||||
rP_words = cute.make_rmem_tensor(tTMEM_STOREcP.shape, self.qk_acc_dtype)
|
||||
rP_bf16 = cute.make_tensor(cute.recast_ptr(rP_words.iterator, dtype=self.q_dtype), tTMEM_LOADrS.layout)
|
||||
minus_row_max = Float32(0.0) - row_max_safe
|
||||
|
||||
rP_bf16_frg = cute.logical_divide(rP_bf16, cute.make_layout(frg_tile))
|
||||
for j in range(frg_cnt):
|
||||
for k in range(cute.size(tTMEM_LOADrS_frg, mode=[0])):
|
||||
tTMEM_LOADrS_frg[k, j] = tTMEM_LOADrS_frg[k, j] * scale_log2 + minus_row_max
|
||||
tTMEM_LOADrS_frg[k, j] = cute.math.exp2(tTMEM_LOADrS_frg[k, j], fastmath=True)
|
||||
row_sum = row_sum + tTMEM_LOADrS_frg[k, j]
|
||||
s_vec = tTMEM_LOADrS_frg[None, j].load()
|
||||
rP_bf16_frg[None, j].store(s_vec.to(self.q_dtype))
|
||||
|
||||
# Copy packed FP32 backing registers to TMEM
|
||||
cute.copy(tiled_tmem_store, rP_words, tTMEM_STOREtP)
|
||||
cute.arch.fence_view_async_tmem_store()
|
||||
|
||||
si_handle.release()
|
||||
softmax_done_bar.arrive()
|
||||
|
||||
# === Reference-style scaled epilogue (no TMEM round-trip) ===
|
||||
#
|
||||
# Pattern (mirrors CUTLASS Blackwell FMHA reference's
|
||||
# correction_epilog): for each column sub-tile,
|
||||
# 1. TMEM -> registers via PAIRED tmem_load atom
|
||||
# 2. scale in registers (1/row_sum)
|
||||
# 3. FP32 -> BF16 conversion in registers
|
||||
# 4. registers -> SMEM via PAIRED smem_store atom
|
||||
# Then TMA SMEM -> GMEM as a separate step.
|
||||
#
|
||||
# Critical: the load and store atoms MUST be a matched pair.
|
||||
# Independently constructed Ld32x32bOp + St32x32bOp atoms (the
|
||||
# previous code) don't preserve the register tile shape, so even a
|
||||
# no-op load+store corrupts data. Using utils.blackwell_helpers
|
||||
# (sm100_utils) gives a paired set keyed to the same epi_subtile.
|
||||
|
||||
# Wait for MMA's PV[N-1] to commit before reading O.
|
||||
final_o_bar.arrive_and_wait()
|
||||
|
||||
# === O normalization via TMEM load → scale → TMEM store ===
|
||||
# Matches CUTLASS reference's correction_rescale pattern exactly.
|
||||
|
||||
corr_tile_size = 16
|
||||
|
||||
cO = cute.make_identity_tensor((self.pv_mma_tiler[0], self.pv_mma_tiler[1]))
|
||||
tOcO = pv_thr.partition_C(cO)
|
||||
|
||||
tOtO_i_layout = cute.composition(tOtO0.layout, cute.make_layout((128, corr_tile_size)))
|
||||
tOcO_i_layout = cute.composition(tOcO.layout, cute.make_layout((128, corr_tile_size)))
|
||||
|
||||
tOtO_i = cute.make_tensor(tOtO0.iterator, tOtO_i_layout)
|
||||
tOcO_i = cute.make_tensor(tOcO.iterator, tOcO_i_layout)
|
||||
|
||||
tmem_load_atom = cute.make_copy_atom(
|
||||
tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
|
||||
self.acc_dtype,
|
||||
)
|
||||
tmem_store_atom = cute.make_copy_atom(
|
||||
tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
|
||||
self.acc_dtype,
|
||||
)
|
||||
|
||||
tiled_tmem_load_o = tcgen05.make_tmem_copy(tmem_load_atom, tOtO_i)
|
||||
tiled_tmem_store_o = tcgen05.make_tmem_copy(tmem_store_atom, tOtO_i)
|
||||
|
||||
thr_tmem_load_o = tiled_tmem_load_o.get_slice(sfw_idx)
|
||||
thr_tmem_store_o = tiled_tmem_store_o.get_slice(sfw_idx)
|
||||
|
||||
tTMEM_LOADtO = thr_tmem_load_o.partition_S(tOtO_i)
|
||||
tTMEM_LOADcO = thr_tmem_load_o.partition_D(tOcO_i)
|
||||
tTMEM_STOREtO = thr_tmem_store_o.partition_D(tOtO_i)
|
||||
|
||||
# 2D register tensor: (frg_shape, n_corr_tiles)
|
||||
tTMrO = cute.make_rmem_tensor(
|
||||
(tTMEM_LOADcO.shape, 128 // corr_tile_size), self.acc_dtype
|
||||
)
|
||||
|
||||
inv_row_sum = Float32(1.0) / row_sum
|
||||
|
||||
for i in range(HEAD_DIM // corr_tile_size):
|
||||
tTMrO_i_ = tTMrO[None, i]
|
||||
tTMrO_i_layout = cute.composition(
|
||||
tTMrO_i_.layout, cute.make_layout(tTMrO.shape[0])
|
||||
)
|
||||
tTMrO_i = cute.make_tensor(tTMrO_i_.iterator, tTMrO_i_layout)
|
||||
tTMEM_LOADtO_i = cute.make_tensor(
|
||||
tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout
|
||||
)
|
||||
tTMEM_STOREtO_i = cute.make_tensor(
|
||||
tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout
|
||||
)
|
||||
|
||||
cute.copy(tiled_tmem_load_o, tTMEM_LOADtO_i, tTMrO_i)
|
||||
for j in cutlass.range(cute.size(tTMrO_i), vectorize=True):
|
||||
tTMrO_i[j] = tTMrO_i[j] * inv_row_sum
|
||||
cute.copy(tiled_tmem_store_o, tTMrO_i, tTMEM_STOREtO_i)
|
||||
|
||||
cute.arch.fence_view_async_tmem_store()
|
||||
|
||||
# Standard epilogue: TMEM → SMEM → GMEM via TMA store.
|
||||
# O in TMEM is now scaled by 1/row_sum.
|
||||
tCtO_base = cute.make_tensor(tmem_ptr + self.tmem_o0_offset, tCtO_fake.layout)
|
||||
acc_cons_st = pipeline.make_pipeline_state(pipeline.PipelineUserType.Consumer, self.num_acc_stage)
|
||||
acc_cons_st = pipeline.make_pipeline_state(
|
||||
pipeline.PipelineUserType.Consumer, self.num_acc_stage
|
||||
)
|
||||
c_grp = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32 * len(self.epilogue_warp_id))
|
||||
c_pipe = pipeline.PipelineTmaStore.create(num_stages=self.num_c_stage, producer_group=c_grp)
|
||||
acc_cons_st = utils.gemm.sm100.epilogue_tma_store(self, tidx, warp_idx, tma_c, tCtO_base, sC, tCgC, epi_tile, 0, const_expr(lambda x: x), (0,0,0), acc_cons_st, acc_pipe, c_pipe)
|
||||
acc_cons_st = utils.gemm.sm100.epilogue_tma_store(
|
||||
self, tidx, warp_idx, tma_c, tCtO_base, sC, tCgC, epi_tile,
|
||||
0, const_expr(lambda x: x), (0, 0, 0),
|
||||
acc_cons_st, acc_pipe, c_pipe,
|
||||
)
|
||||
c_pipe.producer_tail()
|
||||
|
||||
tmem.relinquish_alloc_permit()
|
||||
tmem.free(tmem_ptr)
|
||||
|
||||
|
||||
def test():
|
||||
torch.manual_seed(42)
|
||||
for n in [128]:
|
||||
for n in [128, 256, 512, 1024]:
|
||||
torch.manual_seed(42)
|
||||
m, hd = 128, HEAD_DIM
|
||||
q = torch.randn(m, hd, 1, dtype=torch.bfloat16, device='cuda')
|
||||
k = torch.randn(n, hd, 1, dtype=torch.bfloat16, device='cuda')
|
||||
v = torch.randn(n, hd, dtype=torch.bfloat16, device='cuda')
|
||||
# V passed as (n, hd) row-major — FMHA-style reconstruction inside kernel
|
||||
v_kernel = v.unsqueeze(-1)
|
||||
c = torch.zeros(m, hd, 1, dtype=torch.bfloat16, device='cuda')
|
||||
qf = q[:,:,0].float(); kf = k[:,:,0].float()
|
||||
ref = (qf @ kf.T).bfloat16().float() @ v.float()
|
||||
|
||||
qf = q[:, :, 0].float()
|
||||
kf = k[:, :, 0].float()
|
||||
scale = 1.0 / math.sqrt(hd)
|
||||
attn = qf @ kf.T * scale
|
||||
attn = torch.softmax(attn, dim=-1)
|
||||
ref = attn @ v.float()
|
||||
|
||||
mQ = ct.from_dlpack(q).mark_layout_dynamic(leading_dim=ct.get_leading_dim(q))
|
||||
mK = ct.from_dlpack(k).mark_layout_dynamic(leading_dim=ct.get_leading_dim(k))
|
||||
mV = ct.from_dlpack(v_kernel).mark_layout_dynamic(leading_dim=ct.get_leading_dim(v_kernel))
|
||||
mC = ct.from_dlpack(c).mark_layout_dynamic(leading_dim=ct.get_leading_dim(c))
|
||||
stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)
|
||||
kernel = FmhaV3()
|
||||
|
||||
# Each n requires its own compiled kernel (s_k is compile-time).
|
||||
kernel = FmhaV3StageCMulti(s_k=n)
|
||||
print(f'n={n}: Compiling...', flush=True)
|
||||
compiled = cute.compile(kernel, mQ, mK, mV, mC, stream)
|
||||
print(f'n={n}: tmem_offsets: s0={kernel.tmem_s0_offset} p0={kernel.tmem_p0_offset} o0={kernel.tmem_o0_offset} alloc={kernel.num_tmem_alloc_cols}', flush=True)
|
||||
print(f'n={n}: Running...', flush=True)
|
||||
print(f'n={n}: tmem s0={kernel.tmem_s0_offset} p0={kernel.tmem_p0_offset} '
|
||||
f'o0={kernel.tmem_o0_offset} alloc={kernel.num_tmem_alloc_cols} '
|
||||
f'kv_tx_bytes={kernel.kv_tx_bytes}', flush=True)
|
||||
compiled(mQ, mK, mV, mC, stream)
|
||||
torch.cuda.synchronize()
|
||||
out = c[:,:,0].float()
|
||||
cos = torch.nn.functional.cosine_similarity(out.flatten().unsqueeze(0), ref.flatten().unsqueeze(0)).item()
|
||||
print(f'FMHA v3 n={n} V=ones: cosine {cos:.6f} {"PASS" if cos >= 0.99 else "FAIL"}')
|
||||
|
||||
out = c[:, :, 0].float()
|
||||
cos = torch.nn.functional.cosine_similarity(
|
||||
out.flatten().unsqueeze(0), ref.flatten().unsqueeze(0)
|
||||
).item()
|
||||
max_abs = (out - ref).abs().max().item()
|
||||
n_tiles = n // 128
|
||||
print(f'FMHA Stage-C Multi n={n} ({n_tiles} kv tiles): '
|
||||
f'cos {cos:.6f} max_abs {max_abs:.4f} '
|
||||
f'{"PASS" if cos >= 0.99 else "FAIL"}')
|
||||
if cos < 0.99:
|
||||
print(f' out[0,:4]={out[0,:4].tolist()} ref[0,:4]={ref[0,:4].tolist()}')
|
||||
print(f' out[0,:4]={out[0,:4].tolist()}')
|
||||
print(f' ref[0,:4]={ref[0,:4].tolist()}')
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
test()
|
||||
test()
|
||||
Reference in New Issue
Block a user