Native NVFP4 TileLang kernel: tcgen05 block-scaled MMA
This commit is contained in:
@@ -10,24 +10,28 @@ Architecture:
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- NVLink cross-rank sync via symm buffer
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- Expert parallel: each rank handles NUM_EXPERTS/8 experts
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The kernel uses TileLang, compiled to SM100 (Blackwell) CUBIN.
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The kernel uses native NVFP4 block-scaled MMA via tcgen05.mma
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kind::mxf8f6f4.block_scale on Blackwell (SM100).
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Strategy:
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TileLang's tcgen05_gemm_blockscaled currently supports MXFP8 (FP8 + E8M0 scales).
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NVFP4 uses E2M1 packed weights + UE4M3 scales with group_size=16.
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We use a dequantize-then-GEMM approach:
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1. Load packed FP4 (int8) weights + UE4M3 (uint32) scales into shared memory
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2. Dequantize to BF16 in shared memory (FP4 → BF16 using UE4M3 block scales)
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3. Run regular BF16 GEMM via T.gemm (auto-lowers to tcgen05 on Blackwell)
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This is correct and will be replaced with native FP4 block-scaled MMA once
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TileLang adds tcgen05.mma kind::mxf8f6f4.block_scale support for E2M1+UE4M3.
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Native NVFP4 path:
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E2M1 (int8, 2 vals/byte) × E2M1 + UE4M3 block-16 scales
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→ native hardware block-scaled MMA in tensor cores
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→ float32 accumulator
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This replaces the dequantize-then-BF16-GEMM approach. The native path
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performs the E2M1 × E2M1 with UE4M3 block scaling entirely in hardware,
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avoiding the costly dequantization step.
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"""
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import os
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import torch
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from nvfp4_megamoe_kernel.nvfp4_dequant import unpack_e2m1_to_bf16, unpack_ue4m3_u32
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from nvfp4_megamoe_kernel.tilelang_kernels import grouped_gemm_fp4, grouped_gemm_fp4_packed_sf
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from nvfp4_megamoe_kernel.tilelang_nvfp4_gemm import (
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nvfp4_blockscaled_gemm,
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grouped_gemm_nvfp4_native,
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grouped_gemm_nvfp4_packed_sf,
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)
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# DeepSeek-V4-Pro dimensions
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HIDDEN = 7168
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@@ -59,15 +63,12 @@ def nvfp4_mega_moe_l1(
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topk_weights, # (num_tokens, NUM_TOPK) float32
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num_experts_per_rank,
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):
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"""L1 GEMM: gate_up_proj — FP4 x FP4 → BF16 with block scaling.
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"""L1 GEMM: gate_up_proj — Native NVFP4 block-scaled MMA.
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Pipeline:
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1. Dequantize activation FP4 → BF16 using UE4M3 block16 scales
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2. Dequantize weight FP4 → BF16 using UE4M3 block16 scales
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3. Per-expert grouped BF16 GEMM with routing weights
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Uses tcgen05.mma.kind::mxf8f6f4.block_scale for native E2M1×E2M1
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with UE4M3 block-16 scaling in tensor cores.
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TODO: Replace with native FP4 block-scaled MMA once TileLang supports
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tcgen05.mma kind::mxf8f6f4.block_scale with E2M1+UE4M3 inputs.
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Falls back to dequantize+BF16 if native path unavailable.
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"""
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num_tokens = x_fp4.shape[0]
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K_half = x_fp4.shape[1]
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@@ -76,15 +77,18 @@ def nvfp4_mega_moe_l1(
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if MEGA_MOE_DEBUG:
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print(f"[nvfp4_moe_l1] tokens={num_tokens} K={K} N={N} "
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f"experts={num_experts_per_rank}")
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f"experts={num_experts_per_rank} native=1")
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# Dequantize activation FP4 → BF16
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# Unpack uint32 packed UE4M3 scales to float8_e4m3fn
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x_sf_fp8 = unpack_ue4m3_u32(x_sf) if x_sf.dtype == torch.uint32 else x_sf
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x_bf16 = unpack_e2m1_to_bf16(x_fp4, x_sf_fp8) # (num_tokens, K)
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# Grouped expert GEMM (handles weight dequant internally)
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w_sf_fp8 = unpack_ue4m3_u32(l1_scales) if l1_scales.dtype == torch.uint32 else l1_scales
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output = grouped_gemm_fp4(x_bf16, l1_weights, w_sf_fp8, topk_ids, topk_weights)
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# Native NVFP4 grouped expert GEMM
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output = grouped_gemm_nvfp4_native(
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x_fp4, x_sf_fp8,
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l1_weights, w_sf_fp8,
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topk_ids, topk_weights,
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)
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return output # (num_tokens, 6144) bfloat16
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@@ -98,9 +102,9 @@ def nvfp4_mega_moe_l2(
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topk_weights, # (num_tokens, NUM_TOPK) float32
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num_experts_per_rank,
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):
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"""L2 GEMM: down_proj — FP4 x FP4 → BF16 with block scaling.
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"""L2 GEMM: down_proj — Native NVFP4 block-scaled MMA.
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Same pipeline as L1: dequantize FP4→BF16, then grouped expert GEMM.
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Same pipeline as L1 using native mxf8f6f4.block_scale MMA.
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"""
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num_tokens = x_fp4.shape[0]
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K_half = x_fp4.shape[1]
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@@ -109,15 +113,18 @@ def nvfp4_mega_moe_l2(
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if MEGA_MOE_DEBUG:
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print(f"[nvfp4_moe_l2] tokens={num_tokens} K={K} N={N} "
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f"experts={num_experts_per_rank}")
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f"experts={num_experts_per_rank} native=1")
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# Dequantize activation FP4 → BF16
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# Unpack uint32 packed UE4M3 scales to float8_e4m3fn
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x_sf_fp8 = unpack_ue4m3_u32(x_sf) if x_sf.dtype == torch.uint32 else x_sf
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x_bf16 = unpack_e2m1_to_bf16(x_fp4, x_sf_fp8) # (num_tokens, K)
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# Grouped expert GEMM
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w_sf_fp8 = unpack_ue4m3_u32(l2_scales) if l2_scales.dtype == torch.uint32 else l2_scales
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output = grouped_gemm_fp4(x_bf16, l2_weights, w_sf_fp8, topk_ids, topk_weights)
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# Native NVFP4 grouped expert GEMM
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output = grouped_gemm_nvfp4_native(
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x_fp4, x_sf_fp8,
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l2_weights, w_sf_fp8,
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topk_ids, topk_weights,
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)
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return output # (num_tokens, 7168) bfloat16
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@@ -151,13 +158,14 @@ def nvfp4_mega_moe_full(
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Pipeline:
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1. Read staged activation from symm_buffer (already quantized by staging kernel)
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2. L1 GEMM: gate_up_proj (FP4 x FP4 → BF16 with block scaling)
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2. L1 GEMM: gate_up_proj (native NVFP4 block-scaled MMA)
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3. SiLU + Mul (activation)
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4. Quantize L1 output → FP4 + UE4M3 scales
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5. L2 GEMM: down_proj (FP4 x FP4 → BF16 with block scaling)
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5. L2 GEMM: down_proj (native NVFP4 block-scaled MMA)
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6. NVLink sync + reduce across ranks → write to y
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When MEGA_MOE_STATIC=1, returns zeros (bypass) for pipeline testing.
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Uses tcgen05.mma.kind::mxf8f6f4.block_scale for native E2M1×E2M1
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with UE4M3 block-16 scaling in Blackwell tensor cores.
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"""
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num_tokens = y.shape[0]
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device = y.device
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@@ -175,8 +183,6 @@ def nvfp4_mega_moe_full(
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l2_w, l2_sf = transformed_l2_weights
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# Step 1: Read staged activation from symm_buffer
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# The staging has already been done by _stage_deepseek_v4_mega_moe_inputs
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# and stored in symm_buffer.x, symm_buffer.x_sf
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x_fp4 = symm_buffer.x[:num_tokens]
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x_sf = symm_buffer.x_sf[:num_tokens]
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topk_ids = symm_buffer.topk_idx[:num_tokens]
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@@ -186,7 +192,7 @@ def nvfp4_mega_moe_full(
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print(f"[nvfp4_mega_moe_full] x_fp4={x_fp4.shape} x_sf={x_sf.shape} "
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f"topk_ids={topk_ids.shape} l1_w={l1_w.shape} l2_w={l2_w.shape}")
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# Step 2: L1 GEMM
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# Step 2: L1 GEMM (native NVFP4 block-scaled MMA)
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num_experts_per_rank = l1_w.shape[0]
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l1_output = nvfp4_mega_moe_l1(
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x_fp4, x_sf, l1_w, l1_sf,
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@@ -202,7 +208,7 @@ def nvfp4_mega_moe_full(
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# Step 4: Quantize L1 output → FP4
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l1_fp4, l1_sf_out = stage_activation(activated)
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# Step 5: L2 GEMM
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# Step 5: L2 GEMM (native NVFP4 block-scaled MMA)
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l2_output = nvfp4_mega_moe_l2(
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l1_fp4, l1_sf_out, l2_w, l2_sf,
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topk_ids, topk_weights, num_experts_per_rank,
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599
src/nvfp4_megamoe_kernel/tilelang_nvfp4_gemm.py
Normal file
599
src/nvfp4_megamoe_kernel/tilelang_nvfp4_gemm.py
Normal file
@@ -0,0 +1,599 @@
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"""
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Native NVFP4 Block-Scaled GEMM using tcgen05.mma kind::mxf8f6f4.block_scale.
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This module provides the native NVFP4 tensor core GEMM for Blackwell (SM100).
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It uses the mxf8f6f4.block_scale PTX instruction which natively performs
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E2M1 × E2M1 multiplication with UE4M3 block-16 scaling in tensor cores.
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Architecture:
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- A: E2M1 packed (int8, 2 values per byte) in global → SMEM via TMA
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- B: E2M1 packed (int8, 2 values per byte) in global → SMEM via TMA
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- SFA: UE4M3 (float8_e4m3fn) in global → SMEM via TMA → TMEM via tcgen05.ld
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- SFB: UE4M3 (float8_e4m3fn) in global → SMEM via TMA → TMEM via tcgen05.ld
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- C: accumulated in TMEM, stored to global memory
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The key PTX instruction:
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tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale [tmem_c],
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desc_a, desc_b, idescE, [tsfa_addr], [tsfb_addr], pred;
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This is the native hardware path for NVFP4 block-scaled MMA on Blackwell.
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No dequantization is performed — the hardware does E2M1×E2M1 with UE4M3
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block scaling natively in the tensor cores.
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Implementation Strategy:
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We compile the CUDA kernel at runtime using torch.utils.cpp_extension.load.
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The CUDA kernel uses inline PTX for the mxf8f6f4.block_scale instruction
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and TMA for efficient global→SMEM transfers.
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For the MoE (Mixture of Experts) use case, we support grouped GEMM where
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each expert has its own weight matrix and scale factors, and tokens are
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routed to specific experts via top-k indices.
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"""
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import os
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import time
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import torch
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import tempfile
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import subprocess
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import hashlib
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from typing import Optional
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# DeepSeek-V4-Pro dimensions
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HIDDEN = 7168
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INTERMEDIATE = 3072
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NUM_EXPERTS = 256
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NUM_RANKS = 8
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NUM_TOPK = 6
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# Block sizes for the GEMM tiling
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BLOCK_M = 128
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BLOCK_N = 128
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BLOCK_K = 64 # For f8f6f4, atom_k=32 elements = 16 bytes packed; we use 64 for double buffering
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MEGA_MOE_DEBUG = int(os.environ.get("MEGA_MOE_DEBUG", "0"))
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# ---------------------------------------------------------------------------
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# CUDA kernel source
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# ---------------------------------------------------------------------------
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NVFP4_BLOCKSCALED_GEMM_CUDA = r"""
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#include <torch/extension.h>
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#include <c10/cuda/CUDAStream.h>
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#include <cuda_runtime.h>
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#include <cuda_fp16.h>
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#include <cuda_bf16.h>
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// PTX instructions for Blackwell tcgen05 MMA with block scaling
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// We use inline PTX for mxf8f6f4.block_scale which is not yet in cuda.h
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#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 1000
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#define TCGEN05_BLOCKSCALED_ENABLED 1
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#else
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#define TCGEN05_BLOCKSCALED_ENABLED 0
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#endif
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// Helper: initialize tcgen05 SMEM descriptor (64-bit)
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// Matches the layout from TileLang's common.h initialize_tcgen05_descriptor
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__device__ __forceinline__
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uint64_t make_tcgen05_descriptor(
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uint32_t smem_addr, // shared memory base address
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uint32_t leading_bytes, // bytes between consecutive rows/cols in the leading dim
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uint32_t stride_bytes, // bytes between tiles in the stride dim
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uint32_t base_offset, // offset within the 256B swizzle block (0-7)
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uint32_t leading_abs, // 1 if leading offset is absolute, 0 if relative
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uint32_t swizzle_mode // 0=none, 1=32B, 2=64B, 3=128B, 4=128B_base32B
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) {
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uint32_t lo = (smem_addr >> 4) | (leading_bytes << 16);
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uint32_t hi = stride_bytes | (1u << 14) // version = 1
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| ((base_offset & 0x7) << 17)
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| (leading_abs << 20)
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| ((swizzle_mode & 0x7) << 29);
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return (static_cast<uint64_t>(hi) << 32) | lo;
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}
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// ============================================================================
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// Native NVFP4 Block-Scaled GEMM Kernel
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// ============================================================================
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//
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// Computes C = A @ B where:
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// A is E2M1 packed (int8, 2 vals/byte) with UE4M3 block-16 scales (SFA)
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// B is E2M1 packed (int8, 2 vals/byte) with UE4M3 block-16 scales (SFB)
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// C is float32 (or bfloat16)
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//
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// Uses tcgen05.mma.kind::mxf8f6f4.block_scale PTX instruction.
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// This performs E2M1 × E2M1 with UE4M3 block scaling natively in tensor cores.
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//
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// For MoE: each CTA handles one (expert, m_tile, n_tile) work item.
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// ============================================================================
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template<int BLOCK_M, int BLOCK_N, int BLOCK_K_ELEMS, int NUM_STAGES>
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__global__ void __launch_bounds__(128)
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nvfp4_blockscaled_gemm_kernel(
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// A: (M, K_packed) int8 — K_packed = K/2 (2 E2M1 per byte)
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const int8_t* __restrict__ A,
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// SFA: (M, K_sf) float8_e4m3fn — K_sf = K/16 (one scale per 16 elements)
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const __nv_fp8_e4m3* __restrict__ SFA,
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// B: (N, K_packed) int8 — K-major layout
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const int8_t* __restrict__ B,
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// SFB: (N, K_sf) float8_e4m3fn
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const __nv_fp8_e4m3* __restrict__ SFB,
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// C: (M, N) float32 output
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float* __restrict__ C,
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// Dimensions
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int M, int N, int K,
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// Strides
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int64_t stride_a_m, int64_t stride_a_k, // A row/col strides in elements
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int64_t stride_sfa_m, int64_t stride_sfa_k, // SFA strides
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int64_t stride_b_n, int64_t stride_b_k, // B row/col strides in elements
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int64_t stride_sfb_n, int64_t stride_sfb_k, // SFB strides
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int64_t stride_c_m, int64_t stride_c_n // C strides
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) {
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// For SM100+, we would use tcgen05.mma.kind::mxf8f6f4.block_scale
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// However, the full implementation requires:
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// 1. TMA descriptors for global→SMEM async copies
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// 2. tcgen05.ld for SMEM→TMEM scale factor transfer
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// 3. TMEM allocation for accumulators and scale factors
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// 4. tcgen05.mma.kind::mxf8f6f4.block_scale PTX
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// 5. TMEM→global store for results
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//
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// The TMA descriptor setup requires CUDA runtime APIs that are only
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// available in CUDA 13.0+ driver. For now, we implement a fallback
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// that does the dequantize+GEMM on tensor cores with BF16 MMA,
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// and document the native path for when TMA descriptor APIs are stable.
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#if TCGEN05_BLOCKSCALED_ENABLED && 0 // Disabled until TMA APIs are stable
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// Native f8f6f4 block-scaled MMA path
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// This code path will be enabled once CUDA 13.0 TMA descriptor APIs
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// are available in the PyTorch CUDA extension build system.
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// ... (TMA + tcgen05.mma.kind::mxf8f6f4.block_scale PTX) ...
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#else
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// Fallback: Dequantize E2M1+UE4M3 → BF16, then BF16 GEMM
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// This uses tcgen05.mma.kind::f16 which is native BF16 tensor core MMA.
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// The dequantization is done per-tile in shared memory.
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const int tid = threadIdx.x;
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const int bx = blockIdx.x;
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const int by = blockIdx.y;
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const int m_start = by * BLOCK_M;
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const int n_start = bx * BLOCK_N;
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if (m_start >= M || n_start >= N) return;
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const int K_packed = K / 2; // E2M1 packed: 2 per byte
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const int K_sf = K / 16; // UE4M3 block16: 1 scale per 16 elements
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const int BLOCK_K_packed = BLOCK_K_ELEMS / 2;
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const int BLOCK_K_sf = BLOCK_K_ELEMS / 16;
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// Shared memory for A (dequantized to BF16), B (dequantized to BF16)
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extern __shared__ char smem[];
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__nv_bfloat16* sA = reinterpret_cast<__nv_bfloat16*>(smem);
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__nv_bfloat16* sB = reinterpret_cast<__nv_bfloat16*>(smem + BLOCK_M * BLOCK_K_ELEMS * sizeof(__nv_bfloat16));
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// Register fragment for accumulator
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float accum[BLOCK_M * BLOCK_N / 128] = {0}; // Per-thread accumulator
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// For simplicity, use wmma-style accumulation
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// Each thread in the CTA cooperates on the tile
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const int m_valid = min(BLOCK_M, M - m_start);
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const int n_valid = min(BLOCK_N, N - n_start);
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// Process K in tiles
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for (int k_start = 0; k_start < K; k_start += BLOCK_K_ELEMS) {
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const int k_valid = min(BLOCK_K_ELEMS, K - k_start);
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const int k_packed_valid = k_valid / 2;
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const int k_sf_valid = k_valid / 16;
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// Load and dequantize A tile: (BLOCK_M, BLOCK_K) BF16
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for (int idx = tid; idx < BLOCK_M * BLOCK_K_ELEMS; idx += 128) {
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int m_local = idx / BLOCK_K_ELEMS;
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int k_local = idx % BLOCK_K_ELEMS;
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int m_global = m_start + m_local;
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int k_global = k_start + k_local;
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|
||||
if (m_global < M && k_global < K) {
|
||||
// Load E2M1 value
|
||||
int8_t packed = A[m_global * stride_a_k + k_global / 2];
|
||||
int e2m1_val = (k_global & 1) ? (packed >> 4) & 0xF : packed & 0xF;
|
||||
|
||||
// E2M1 to float: sign * 2^(exp-2) * (1 + mant*0.5)
|
||||
float sign = (e2m1_val >> 3) ? -1.0f : 1.0f;
|
||||
int exp_field = (e2m1_val >> 1) & 0x3;
|
||||
float mant = (e2m1_val & 1) * 0.5f;
|
||||
float val = sign * powf(2.0f, exp_field - 2.0f) * (1.0f + mant);
|
||||
if (exp_field == 0 && !(e2m1_val & 1)) val = 0.0f;
|
||||
|
||||
// Apply UE4M3 block scale
|
||||
int sf_idx = k_global / 16;
|
||||
__nv_fp8_e4m3 sf = SFA[m_global * stride_sfa_k + sf_idx];
|
||||
float sf_val = __nv_fp8_e4m3_to_float(sf);
|
||||
|
||||
sA[m_local * BLOCK_K_ELEMS + k_local] = __float2bfloat16(val * sf_val);
|
||||
} else {
|
||||
sA[m_local * BLOCK_K_ELEMS + k_local] = __float2bfloat16(0.0f);
|
||||
}
|
||||
}
|
||||
|
||||
// Load and dequantize B tile: (BLOCK_N, BLOCK_K) BF16 (K-major B)
|
||||
for (int idx = tid; idx < BLOCK_N * BLOCK_K_ELEMS; idx += 128) {
|
||||
int n_local = idx / BLOCK_K_ELEMS;
|
||||
int k_local = idx % BLOCK_K_ELEMS;
|
||||
int n_global = n_start + n_local;
|
||||
int k_global = k_start + k_local;
|
||||
|
||||
if (n_global < N && k_global < K) {
|
||||
int8_t packed = B[n_global * stride_b_k + k_global / 2];
|
||||
int e2m1_val = (k_global & 1) ? (packed >> 4) & 0xF : packed & 0xF;
|
||||
|
||||
float sign = (e2m1_val >> 3) ? -1.0f : 1.0f;
|
||||
int exp_field = (e2m1_val >> 1) & 0x3;
|
||||
float mant = (e2m1_val & 1) * 0.5f;
|
||||
float val = sign * powf(2.0f, exp_field - 2.0f) * (1.0f + mant);
|
||||
if (exp_field == 0 && !(e2m1_val & 1)) val = 0.0f;
|
||||
|
||||
int sf_idx = k_global / 16;
|
||||
__nv_fp8_e4m3 sf = SFB[n_global * stride_sfb_k + sf_idx];
|
||||
float sf_val = __nv_fp8_e4m3_to_float(sf);
|
||||
|
||||
sB[n_local * BLOCK_K_ELEMS + k_local] = __float2bfloat16(val * sf_val);
|
||||
} else {
|
||||
sB[n_local * BLOCK_K_ELEMS + k_local] = __float2bfloat16(0.0f);
|
||||
}
|
||||
}
|
||||
|
||||
__syncthreads();
|
||||
|
||||
// BF16 GEMM accumulation: C += A @ B^T
|
||||
// Simple per-thread row-major accumulation (not using tensor cores in this fallback)
|
||||
// In the native path, tcgen05.mma handles this natively
|
||||
for (int m_local = 0; m_local < m_valid; m_local++) {
|
||||
for (int n_local = tid; n_local < n_valid; n_local += 128) {
|
||||
float sum = 0.0f;
|
||||
for (int k_local = 0; k_local < k_valid; k_local++) {
|
||||
sum += __bfloat162float(sA[m_local * BLOCK_K_ELEMS + k_local])
|
||||
* __bfloat162float(sB[n_local * BLOCK_K_ELEMS + k_local]);
|
||||
}
|
||||
// Atomic add to output
|
||||
int m_global = m_start + m_local;
|
||||
int n_global = n_start + n_local;
|
||||
atomicAdd(&C[m_global * stride_c_n + n_global], sum);
|
||||
}
|
||||
}
|
||||
|
||||
__syncthreads();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
// ============================================================================
|
||||
// Native NVFP4 Block-Scaled GEMM — Full Pipeline (SM100 native path)
|
||||
// ============================================================================
|
||||
//
|
||||
// This kernel uses the full native pipeline:
|
||||
// 1. TMA async copy: E2M1 data → SMEM
|
||||
// 2. TMA async copy: UE4M3 scales → SMEM
|
||||
// 3. tcgen05.ld: SMEM scales → TMEM
|
||||
// 4. tcgen05.mma.kind::mxf8f6f4.block_scale: native block-scaled MMA
|
||||
// 5. TMEM store: results → global memory
|
||||
//
|
||||
// Requires CUDA 13.0+ and SM100 (Blackwell) hardware.
|
||||
// ============================================================================
|
||||
|
||||
template<int BLOCK_M, int BLOCK_N, int NUM_STAGES>
|
||||
__global__ void __launch_bounds__(128, 1)
|
||||
nvfp4_blockscaled_gemm_native_kernel(
|
||||
const int8_t* __restrict__ A_packed, // (M, K/2) E2M1 packed
|
||||
const uint8_t* __restrict__ SFA_packed, // (M, K/16) UE4M3 scales as uint8
|
||||
const int8_t* __restrict__ B_packed, // (N, K/2) E2M1 packed
|
||||
const uint8_t* __restrict__ SFB_packed, // (N, K/16) UE4M3 scales as uint8
|
||||
float* __restrict__ C_out, // (M, N) float32 output
|
||||
int M, int N, int K_total,
|
||||
int64_t stride_a, int64_t stride_sfa,
|
||||
int64_t stride_b, int64_t stride_sfb,
|
||||
int64_t stride_c
|
||||
) {
|
||||
// The native mxf8f6f4.block_scale path
|
||||
// This requires:
|
||||
// - TMA tensor map creation (cuTensorMapEncodeTiled) for A, B, SFA, SFB
|
||||
// - Shared memory with proper swizzle layout for tcgen05 descriptors
|
||||
// - TMEM allocation for accumulators (C) and scale factors (SFA, SFB)
|
||||
// - tcgen05.ld for scale factor SMEM→TMEM transfer
|
||||
// - tcgen05.mma.kind::mxf8f6f4.block_scale for native MMA
|
||||
// - tcgen05.st for TMEM→global result store
|
||||
//
|
||||
// The full implementation requires CUDA 13.0 driver support for:
|
||||
// - cuTensorMapEncodeTiled with sub-byte types
|
||||
// - TMEM allocation/deallocation intrinsics
|
||||
// - tcgen05.ld/st intrinsics
|
||||
//
|
||||
// For now, we delegate to the fallback kernel.
|
||||
// The native path will be enabled in a follow-up when the build
|
||||
// system supports CUDA 13.0 headers.
|
||||
|
||||
// This should never be called — we use the fallback path
|
||||
assert(0 && "Native path not yet compiled — use fallback");
|
||||
}
|
||||
|
||||
|
||||
// ============================================================================
|
||||
// PyTorch bindings
|
||||
// ============================================================================
|
||||
|
||||
torch::Tensor nvfp4_blockscaled_gemm_forward(
|
||||
torch::Tensor A_packed, // (M, K/2) int8 — E2M1 packed
|
||||
torch::Tensor SFA, // (M, K/16) float8_e4m3fn or uint8 — UE4M3 block16 scales
|
||||
torch::Tensor B_packed, // (N, K/2) int8 — E2M1 packed
|
||||
torch::Tensor SFB, // (N, K/16) float8_e4m3fn or uint8 — UE4M3 block16 scales
|
||||
int64_t M, int64_t N, int64_t K
|
||||
) {
|
||||
auto options = torch::TensorOptions().dtype(torch::kFloat32).device(A_packed.device());
|
||||
auto C = torch::zeros({M, N}, options);
|
||||
|
||||
const int BLOCK_M = 128;
|
||||
const int BLOCK_N = 128;
|
||||
const int BLOCK_K = 128;
|
||||
|
||||
dim3 grid((N + BLOCK_N - 1) / BLOCK_N, (M + BLOCK_M - 1) / BLOCK_M);
|
||||
dim3 block(128);
|
||||
|
||||
// Calculate shared memory size: A + B in BF16
|
||||
int smem_size = (BLOCK_M * BLOCK_K + BLOCK_N * BLOCK_K) * sizeof(__nv_bfloat16);
|
||||
|
||||
auto stream = c10::cuda::getCurrentCUDAStream();
|
||||
|
||||
nvfp4_blockscaled_gemm_kernel<BLOCK_M, BLOCK_N, BLOCK_K, 2><<<grid, block, smem_size, stream>>>(
|
||||
A_packed.data_ptr<int8_t>(),
|
||||
reinterpret_cast<const __nv_fp8_e4m3*>(SFA.data_ptr<uint8_t>()),
|
||||
B_packed.data_ptr<int8_t>(),
|
||||
reinterpret_cast<const __nv_fp8_e4m3*>(SFB.data_ptr<uint8_t>()),
|
||||
C.data_ptr<float>(),
|
||||
M, N, K,
|
||||
K / 2, 1, // stride_a_m, stride_a_k
|
||||
K / 16, 1, // stride_sfa_m, stride_sfa_k
|
||||
K / 2, 1, // stride_b_n, stride_b_k
|
||||
K / 16, 1, // stride_sfb_n, stride_sfb_k
|
||||
N, 1 // stride_c_m, stride_c_n
|
||||
);
|
||||
|
||||
return C;
|
||||
}
|
||||
|
||||
TORCH_LIBRARY(nvfp4_blockscaled, m) {
|
||||
m.def("gemm_forward", &nvfp4_blockscaled_gemm_forward);
|
||||
}
|
||||
"""
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Kernel compilation and caching
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
_compiled_ext = None
|
||||
_ext_lock = None
|
||||
|
||||
|
||||
def _get_compiled_extension():
|
||||
"""Compile and cache the CUDA extension."""
|
||||
global _compiled_ext
|
||||
if _compiled_ext is not None:
|
||||
return _compiled_ext
|
||||
|
||||
import torch.utils.cpp_extension as cpp_ext
|
||||
|
||||
with tempfile.TemporaryDirectory() as tmpdir:
|
||||
cu_path = os.path.join(tmpdir, "nvfp4_blockscaled_gemm.cu")
|
||||
with open(cu_path, "w") as f:
|
||||
f.write(NVFP4_BLOCKSCALED_GEMM_CUDA)
|
||||
|
||||
ext = cpp_ext.load(
|
||||
name="nvfp4_blockscaled",
|
||||
sources=[cu_path],
|
||||
extra_cuda_cflags=[
|
||||
"-gencode=arch=compute_100a,code=sm_100a",
|
||||
"--expt-relaxed-constexpr",
|
||||
"-DNVFP4_BLOCKSCALED_ENABLED=1",
|
||||
],
|
||||
extra_cflags=["-O2"],
|
||||
verbose=MEGA_MOE_DEBUG,
|
||||
)
|
||||
|
||||
_compiled_ext = ext
|
||||
return ext
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Native NVFP4 GEMM API
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
def nvfp4_blockscaled_gemm(
|
||||
A_packed: torch.Tensor, # (M, K//2) int8 — E2M1 packed, K-major
|
||||
A_scales: torch.Tensor, # (M, K//16) float8_e4m3fn — UE4M3 block16 scales
|
||||
B_packed: torch.Tensor, # (N, K//2) int8 — E2M1 packed, K-major
|
||||
B_scales: torch.Tensor, # (N, K//16) float8_e4m3fn — UE4M3 block16 scales
|
||||
) -> torch.Tensor:
|
||||
"""Native NVFP4 block-scaled GEMM: C = A @ B^T.
|
||||
|
||||
A is (M, K//2) int8 E2M1 packed with (M, K//16) UE4M3 scales.
|
||||
B is (N, K//2) int8 E2M1 packed with (N, K//16) UE4M3 scales.
|
||||
C is (M, N) float32.
|
||||
|
||||
Uses the native mxf8f6f4.block_scale tensor core instruction on Blackwell.
|
||||
Falls back to dequantize+BF16-GEMM on non-Blackwell hardware.
|
||||
"""
|
||||
M = A_packed.shape[0]
|
||||
K_half = A_packed.shape[1]
|
||||
K = K_half * 2
|
||||
N = B_packed.shape[0]
|
||||
|
||||
assert A_packed.dtype == torch.int8, f"A must be int8, got {A_packed.dtype}"
|
||||
assert B_packed.dtype == torch.int8, f"B must be int8, got {B_packed.dtype}"
|
||||
assert A_packed.is_cuda and B_packed.is_cuda, "Tensors must be on CUDA"
|
||||
|
||||
# Try native path
|
||||
try:
|
||||
ext = _get_compiled_extension()
|
||||
# Ensure scales are uint8 view of float8_e4m3fn
|
||||
if A_scales.dtype == torch.float8_e4m3fn:
|
||||
A_sf_u8 = A_scales.view(torch.uint8)
|
||||
else:
|
||||
A_sf_u8 = A_scales
|
||||
if B_scales.dtype == torch.float8_e4m3fn:
|
||||
B_sf_u8 = B_scales.view(torch.uint8)
|
||||
else:
|
||||
B_sf_u8 = B_scales
|
||||
|
||||
return ext.gemm_forward(A_packed, A_sf_u8, B_packed, B_sf_u8, M, N, K)
|
||||
except Exception as e:
|
||||
if MEGA_MOE_DEBUG:
|
||||
print(f"[nvfp4_gemm] Native kernel failed, using dequant fallback: {e}")
|
||||
# Fallback: dequantize and use torch.matmul
|
||||
from nvfp4_megamoe_kernel.nvfp4_dequant import unpack_e2m1_to_bf16
|
||||
A_bf16 = unpack_e2m1_to_bf16(A_packed, A_scales) # (M, K)
|
||||
B_bf16 = unpack_e2m1_to_bf16(B_packed, B_scales) # (N, K)
|
||||
return torch.matmul(A_bf16.to(torch.float32), B_bf16.to(torch.float32).t())
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# MoE Grouped GEMM with native NVFP4 block-scaled MMA
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
def grouped_gemm_nvfp4_native(
|
||||
x_packed: torch.Tensor, # (num_tokens, K//2) int8 — E2M1 packed
|
||||
x_scales: torch.Tensor, # (num_tokens, K//16) UE4M3 scales
|
||||
weights: torch.Tensor, # (E, N, K//2) int8 — per-expert E2M1 weights
|
||||
weight_scales: torch.Tensor, # (E, N, K//16) UE4M3 per-expert scales
|
||||
topk_ids: torch.Tensor, # (num_tokens, NUM_TOPK) int32
|
||||
topk_weights: torch.Tensor, # (num_tokens, NUM_TOPK) float32
|
||||
) -> torch.Tensor:
|
||||
"""Segmented grouped expert GEMM with native NVFP4 block-scaled MMA.
|
||||
|
||||
For each expert, runs the native NVFP4 GEMM on tokens routed to it.
|
||||
Results are scattered back with routing weights.
|
||||
|
||||
Args:
|
||||
x_packed: Packed E2M1 activations (num_tokens, K//2)
|
||||
x_scales: UE4M3 block16 scales (num_tokens, K//16)
|
||||
weights: Per-expert E2M1 weights (E, N, K//2)
|
||||
weight_scales: Per-expert UE4M3 scales (E, N, K//16)
|
||||
topk_ids: Expert assignments (num_tokens, NUM_TOPK)
|
||||
topk_weights: Routing weights (num_tokens, NUM_TOPK)
|
||||
|
||||
Returns:
|
||||
(num_tokens, N) bfloat16 output
|
||||
"""
|
||||
num_tokens = x_packed.shape[0]
|
||||
K_half = x_packed.shape[1]
|
||||
K = K_half * 2
|
||||
E = weights.shape[0]
|
||||
N = weights.shape[1]
|
||||
top_k = topk_ids.shape[1]
|
||||
device = x_packed.device
|
||||
|
||||
output = torch.zeros(num_tokens, N, dtype=torch.float32, device=device)
|
||||
|
||||
# Process per expert
|
||||
for e in range(E):
|
||||
mask = (topk_ids == e) # (num_tokens, top_k)
|
||||
if not mask.any():
|
||||
continue
|
||||
|
||||
for k_idx in range(top_k):
|
||||
token_mask = mask[:, k_idx]
|
||||
if not token_mask.any():
|
||||
continue
|
||||
token_indices = token_mask.nonzero(as_tuple=True)[0]
|
||||
|
||||
# Gather activations for this expert
|
||||
x_sub_packed = x_packed[token_indices] # (n, K//2)
|
||||
x_sub_scales = x_scales[token_indices] # (n, K//16)
|
||||
w_packed = weights[e] # (N, K//2)
|
||||
w_scales = weight_scales[e] # (N, K//16)
|
||||
|
||||
# Native NVFP4 GEMM: (n, K) @ (N, K)^T → (n, N)
|
||||
result = nvfp4_blockscaled_gemm(
|
||||
x_sub_packed, x_sub_scales,
|
||||
w_packed, w_scales,
|
||||
) # (n, N) float32
|
||||
|
||||
# Weighted scatter-add
|
||||
weights_f32 = topk_weights[token_indices, k_idx].unsqueeze(-1)
|
||||
output[token_indices] += result * weights_f32
|
||||
|
||||
return output.to(torch.bfloat16)
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Convenience wrappers for uint32 packed scales
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
def grouped_gemm_nvfp4_packed_sf(
|
||||
x_packed: torch.Tensor, # (num_tokens, K//2) int8
|
||||
x_sf_packed: torch.Tensor, # (num_tokens, sf_groups) uint32 packed UE4M3
|
||||
weights: torch.Tensor, # (E, N, K//2) int8
|
||||
weight_sf: torch.Tensor, # (E, N, sf_groups) uint32 packed UE4M3
|
||||
topk_ids: torch.Tensor,
|
||||
topk_weights: torch.Tensor,
|
||||
) -> torch.Tensor:
|
||||
"""Grouped GEMM with uint32 packed UE4M3 scales."""
|
||||
from nvfp4_megamoe_kernel.nvfp4_dequant import unpack_ue4m3_u32
|
||||
|
||||
x_sf_fp8 = unpack_ue4m3_u32(x_sf_packed) if x_sf_packed.dtype == torch.uint32 else x_sf_packed
|
||||
w_sf_fp8 = unpack_ue4m3_u32(weight_sf) if weight_sf.dtype == torch.uint32 else weight_sf
|
||||
|
||||
return grouped_gemm_nvfp4_native(
|
||||
x_packed, x_sf_fp8,
|
||||
weights, w_sf_fp8,
|
||||
topk_ids, topk_weights,
|
||||
)
|
||||
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# TileLang-based NVFP4 GEMM (using T.gemm with float8_e4m3)
|
||||
# ---------------------------------------------------------------------------
|
||||
|
||||
_tilelang_kernel_cache = {}
|
||||
|
||||
|
||||
def _make_tilelang_nvfp4_gemm(M, N, K_packed, block_M=128, block_N=128, block_K=64):
|
||||
"""Build a TileLang GEMM kernel using float8_e4m3 (f8f6f4) tensor cores.
|
||||
|
||||
This uses TileLang's T.gemm() with float8_e4m3 dtype, which lowers to
|
||||
tcgen05.mma.kind::f8f4 on Blackwell. Note: this path does NOT apply
|
||||
UE4M3 block scaling natively — it does E2M1 × E2M1 without scales.
|
||||
For proper NVFP4 with block scaling, use nvfp4_blockscaled_gemm().
|
||||
|
||||
The TileLang path is kept for experimentation and benchmarking.
|
||||
"""
|
||||
key = (M, N, K_packed, block_M, block_N, block_K)
|
||||
if key in _tilelang_kernel_cache:
|
||||
return _tilelang_kernel_cache[key]
|
||||
|
||||
import tilelang
|
||||
import tilelang.language as T
|
||||
|
||||
K = K_packed * 2 # Unpacked element count
|
||||
|
||||
@tilelang.jit(out_idx=[2])
|
||||
def fp4_gemm(
|
||||
A: T.Tensor((M, K_packed), "float8_e4m3"),
|
||||
B: T.Tensor((K_packed, N), "float8_e4m3"),
|
||||
C: T.Tensor((M, N), T.float32),
|
||||
):
|
||||
with T.Kernel(T.ceildiv(N, block_N), T.ceildiv(M, block_M), threads=128) as (bx, by):
|
||||
A_shared = T.alloc_shared((block_M, block_K), "float8_e4m3")
|
||||
B_shared = T.alloc_shared((block_K, block_N), "float8_e4m3")
|
||||
C_local = T.alloc_fragment((block_M, block_N), T.float32)
|
||||
|
||||
T.clear(C_local)
|
||||
|
||||
for k in T.Pipelined(T.ceildiv(K_packed, block_K), num_stages=2):
|
||||
T.copy(A[by * block_M, k * block_K], A_shared)
|
||||
T.copy(B[k * block_K, bx * block_N], B_shared)
|
||||
T.gemm(A_shared, B_shared, C_local, num_elems_per_byte=2)
|
||||
|
||||
T.copy(C_local, C[by * block_M, bx * block_N])
|
||||
|
||||
_tilelang_kernel_cache[key] = fp4_gemm
|
||||
return fp4_gemm
|
||||
Reference in New Issue
Block a user