P4: TMA descriptor dump test (cuTensorMapEncodeTiled)
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130
tests/unit/test_p4_tma_descriptor_diff.py
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130
tests/unit/test_p4_tma_descriptor_diff.py
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"""
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P4: Dump TMA descriptor bytes from both CuTeDSL and cuTensorMapEncodeTiled.
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1. CuTeDSL: create a TMA descriptor for a (128,16) BF16 tensor via cute.compile
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and dump the 128 bytes.
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2. Driver API: use cuTensorMapEncodeTiled for the same tensor and dump 128 bytes.
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3. memcmp and print differences.
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The CuTeDSL path already works (it's used in the existing FMHA kernel).
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The raw Driver API path hangs when used with cp.async.bulk.tensor.2d.
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By comparing descriptors byte-by-byte, we can identify the field that differs.
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"""
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import torch
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import sys
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import os
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import struct
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import numpy as np
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
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def dump_driver_api_descriptor():
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"""Create TMA descriptor using Driver API (cuTensorMapEncodeTiled)."""
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from cuda.bindings import driver, runtime
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# Initialize CUDA
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runtime.cudaFree(0) # Force context creation
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# Create a (128, 16) BF16 tensor on GPU
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rows, cols = 128, 16
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data = torch.zeros(rows, cols, dtype=torch.bfloat16, device='cuda')
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# cuTensorMap descriptor: 128 bytes
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tensor_map = driver.CUtensorMap()
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# cuTensorMapEncodeTiled args:
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# - tensorMap: output
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# - tensorRank: 2
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# - cudaDataType: CU_TENSOR_MAP_DATA_TYPE_BFLOAT16 (6)
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# - deviceAddress: data pointer
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# - tensorDims: [128, 16]
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# - globalStrides: [16*2, 2] (byte strides: row_stride=16*2 bytes, col_stride=2 bytes)
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# - boxDims: [16, 16] (TMA tile size)
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# - elementStrides: [1, 1]
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# - interleave: CU_TENSOR_MAP_INTERLEAVE_NONE (0)
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# - swizzle: CU_TENSOR_MAP_SWIZZLE_NONE (0)
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# - l2Promotion: CU_TENSOR_MAP_L2_PROMOTION_NONE (0)
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# - oobFill: CU_TENSOR_MAP_OOB_FILL_NONE (0)
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globalStrides = (ctypes.c_uint64 * 2)()
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globalStrides[0] = cols * 2 # stride from row 0 to row 1 = 16 * 2 = 32 bytes
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globalStrides[1] = 2 # stride from col 0 to col 1 = 2 bytes
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import ctypes
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tensorDims = (ctypes.c_uint32 * 2)(rows, cols)
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boxDims = (ctypes.c_uint32 * 2)(16, 16)
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elementStrides = (ctypes.c_uint32 * 2)(1, 1)
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# Actually, let me use the cuda.bindings API directly
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# cuTensorMapEncodeTiled is in cuda.bindings.driver
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result = driver.cuTensorMapEncodeTiled(
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tensor_map,
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2, # tensorRank
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driver.CUtensorMapDataType.CU_TENSOR_MAP_DATA_TYPE_BFLOAT16,
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int(data.data_ptr()),
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(rows, cols),
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(cols * 2, 2), # globalStrides in bytes
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(16, 16), # boxDims
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(1, 1), # elementStrides
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driver.CUtensorMapInterleave.CU_TENSOR_MAP_INTERLEAVE_NONE,
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driver.CUtensorMapSwizzle.CU_TENSOR_MAP_SWIZZLE_NONE,
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driver.CUtensorMapL2Promotion.CU_TENSOR_MAP_L2_PROMOTION_NONE,
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driver.CUtensorMapOOBFill.CU_TENSOR_MAP_OOB_FILL_NONE,
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)
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if result != driver.CUresult.CUDA_SUCCESS:
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print(f"cuTensorMapEncodeTiled failed: {result}")
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return None
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# The descriptor is 128 bytes. Access it via the opaque field.
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# CUtensorMap has an opaque byte array
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desc_bytes = bytes(tensor_map)
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return desc_bytes
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def dump_cutedsl_descriptor():
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"""Create TMA descriptor using CuTeDSL and dump bytes.
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CuTeDSL creates descriptors internally when you call cute.make_tensor
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with a TMA layout. We need to intercept the descriptor bytes.
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Actually, CuTeDSL's TMA descriptors are created at JIT compile time
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and stored in the kernel's parameter struct. We can't easily dump them
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from Python.
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Alternative: use CuTe's TMA descriptor creation API directly.
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cute.arch.make_tma_copy can create a descriptor that we can inspect.
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"""
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# This is harder than I thought. CuTeDSL hides the descriptor creation.
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# Let me use a different approach: create a small CuTeDSL kernel that
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# does a TMA load (which works), and use Nsight to capture the descriptor.
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# Or: use the CUTLASS Python API directly.
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# Actually, the simplest approach: use the CUTLASS Python bindings
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# that CuTeDSL uses internally. The TMA descriptor is a Python object
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# before being passed to the kernel.
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pass
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def main():
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print("P4: TMA Descriptor Comparison")
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print("=" * 60)
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# Step 1: Driver API descriptor
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print("\n1. Driver API (cuTensorMapEncodeTiled) descriptor:")
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desc_driver = dump_driver_api_descriptor()
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if desc_driver is not None:
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for i in range(0, 128, 16):
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hex_str = ' '.join(f'{b:02x}' for b in desc_driver[i:i+16])
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print(f" [{i:3d}-{i+15:3d}]: {hex_str}")
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else:
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print(" FAILED to create descriptor")
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print("\nNote: CuTeDSL descriptor dump requires running inside a JIT kernel.")
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print("Use the CUDA test (test_p4_tma_descriptor_diff.cu) for the full comparison.")
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if __name__ == "__main__":
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main()
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177
tests/unit/test_p4_tma_descriptor_dump.cu
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177
tests/unit/test_p4_tma_descriptor_dump.cu
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/**
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* P4: Dump TMA descriptor bytes for comparison.
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*
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* Creates a TMA descriptor using cuTensorMapEncodeTiled for a (128,16) BF16
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* tensor with various swizzle modes, and dumps the 128-byte descriptor.
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*
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* The working CuTeDSL path on the B200 can be used to create a matching
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* descriptor via a small Python script. This test dumps the raw CUDA path.
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*
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* Usage:
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* fire_b200_cuda_test tests/unit/test_p4_tma_descriptor_dump.cu
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*/
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#include <cuda_runtime.h>
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#include <cuda.h>
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#include <cstdio>
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#include <cstdint>
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#include <cstring>
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__global__ void dummy_kernel() {}
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int main() {
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// Allocate a (128, 16) BF16 tensor on GPU
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const int ROWS = 128;
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const int COLS = 16;
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const size_t SIZE = ROWS * COLS * 2; // 4096 bytes
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void* d_ptr;
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cudaMalloc(&d_ptr, SIZE);
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cudaMemset(d_ptr, 0, SIZE);
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CUtensorMap tma_desc;
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CUresult res;
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// ==================================================================
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// Descriptor 1: NO swizzle (the one that hangs in cp.async.bulk.tensor)
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// ==================================================================
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uint32_t tensorDims[] = {ROWS, COLS};
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uint64_t globalStrides[] = {COLS * 2, 2}; // bytes
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uint32_t boxDims[] = {16, 16};
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uint32_t elementStrides[] = {1, 1};
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res = cuTensorMapEncodeTiled(
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&tma_desc,
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2, // rank
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CU_TENSOR_MAP_DATA_TYPE_BFLOAT16,
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d_ptr,
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tensorDims,
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globalStrides,
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boxDims,
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elementStrides,
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CU_TENSOR_MAP_INTERLEAVE_NONE,
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CU_TENSOR_MAP_SWIZZLE_NONE,
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CU_TENSOR_MAP_L2_PROMOTION_NONE,
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CU_TENSOR_MAP_OOB_FILL_NONE
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);
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printf("=== Descriptor 1: NO swizzle ===\n");
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if (res != CUDA_SUCCESS) {
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printf("cuTensorMapEncodeTiled FAILED: %d\n", res);
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} else {
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const uint8_t* bytes = reinterpret_cast<const uint8_t*>(&tma_desc);
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for (int i = 0; i < 128; i += 16) {
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printf("[%3d-%3d]: ", i, i+15);
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for (int j = 0; j < 16; j++) printf("%02x ", bytes[i+j]);
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printf("\n");
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}
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}
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// ==================================================================
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// Descriptor 2: SWIZZLE_128B (the one CuTeDSL uses for canonical layout)
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// ==================================================================
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res = cuTensorMapEncodeTiled(
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&tma_desc,
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2,
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CU_TENSOR_MAP_DATA_TYPE_BFLOAT16,
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d_ptr,
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tensorDims,
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globalStrides,
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boxDims,
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elementStrides,
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CU_TENSOR_MAP_INTERLEAVE_NONE,
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CU_TENSOR_MAP_SWIZZLE_128B,
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CU_TENSOR_MAP_L2_PROMOTION_NONE,
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CU_TENSOR_MAP_OOB_FILL_NONE
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);
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printf("\n=== Descriptor 2: SWIZZLE_128B ===\n");
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if (res != CUDA_SUCCESS) {
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printf("cuTensorMapEncodeTiled FAILED: %d\n", res);
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} else {
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const uint8_t* bytes = reinterpret_cast<const uint8_t*>(&tma_desc);
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for (int i = 0; i < 128; i += 16) {
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printf("[%3d-%3d]: ", i, i+15);
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for (int j = 0; j < 16; j++) printf("%02x ", bytes[i+j]);
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printf("\n");
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}
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}
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// ==================================================================
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// Descriptor 3: Different globalStrides (element strides vs byte strides)
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// CUDA 13 might need element strides, not byte strides
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// ==================================================================
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// Try with globalStrides in ELEMENTS (not bytes)
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uint64_t globalStrides_elem[] = {COLS, 1}; // elements, not bytes
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res = cuTensorMapEncodeTiled(
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&tma_desc,
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2,
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CU_TENSOR_MAP_DATA_TYPE_BFLOAT16,
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d_ptr,
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tensorDims,
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globalStrides_elem,
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boxDims,
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elementStrides,
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CU_TENSOR_MAP_INTERLEAVE_NONE,
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CU_TENSOR_MAP_SWIZZLE_NONE,
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CU_TENSOR_MAP_L2_PROMOTION_NONE,
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CU_TENSOR_MAP_OOB_FILL_NONE
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);
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printf("\n=== Descriptor 3: NO swizzle, element strides (not byte) ===\n");
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if (res != CUDA_SUCCESS) {
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printf("cuTensorMapEncodeTiled FAILED: %d\n", res);
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} else {
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const uint8_t* bytes = reinterpret_cast<const uint8_t*>(&tma_desc);
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for (int i = 0; i < 128; i += 16) {
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printf("[%3d-%3d]: ", i, i+15);
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for (int j = 0; j < 16; j++) printf("%02x ", bytes[i+j]);
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printf("\n");
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}
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}
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// ==================================================================
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// Descriptor 4: OOB_FILL_ZERO (maybe the hang is caused by OOB access)
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// ==================================================================
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res = cuTensorMapEncodeTiled(
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&tma_desc,
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2,
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CU_TENSOR_MAP_DATA_TYPE_BFLOAT16,
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d_ptr,
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tensorDims,
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globalStrides,
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boxDims,
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elementStrides,
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CU_TENSOR_MAP_INTERLEAVE_NONE,
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CU_TENSOR_MAP_SWIZZLE_NONE,
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CU_TENSOR_MAP_L2_PROMOTION_NONE,
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CU_TENSOR_MAP_OOB_FILL_ZERO
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);
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printf("\n=== Descriptor 4: NO swizzle, OOB_FILL_ZERO ===\n");
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if (res != CUDA_SUCCESS) {
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printf("cuTensorMapEncodeTiled FAILED: %d\n", res);
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} else {
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const uint8_t* bytes = reinterpret_cast<const uint8_t*>(&tma_desc);
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for (int i = 0; i < 128; i += 16) {
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printf("[%3d-%3d]: ", i, i+15);
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for (int j = 0; j < 16; j++) printf("%02x ", bytes[i+j]);
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printf("\n");
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}
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}
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// ==================================================================
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// Also test: actual TMA load with descriptor 1 (the one that hangs)
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// ==================================================================
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// We can't easily do this in a host test. The hang happens inside
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// a kernel when cp.async.bulk.tensor.2d is issued with this descriptor.
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// That test exists separately.
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printf("\n=== Test: TMA load with descriptor 1 (NO swizzle) ===\n");
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// Quick test: launch a kernel that does TMA load
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// This is the test that hangs — we just verify the descriptor creates OK
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printf("Descriptor creation OK. TMA load test requires separate kernel.\n");
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cudaFree(d_ptr);
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printf("\nPASSED\n");
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return 0;
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}
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