D1.5: Replace broken TMEM round-trip with correction epilogue (paired atoms)
Replace hand-constructed Ld32x32bOp/St32x32bOp TMEM round-trip with the proven correction epilogue pattern from fused_swiglu.py: 1. O rescale (kt>0): TMEM→REGS (paired load), multiply by acc_scale, REGS→TMEM (paired store via retile_to_S). No layout mismatch. 2. Final O output: One-way TMEM→REGS→SMEM→GMEM using epilogue_tmem_copy_and_partition + epilogue_smem_copy_and_partition + TMA partition. Register-level normalization (divide by row_sum) or raw BF16 cast for D5a path. This fixes both D1.5 issues: - Issue 1: TMEM round-trip corruption (hand-constructed atoms) - Issue 2: O rescale for multi-KV-tile (kt>0) Supports normalize=True (in-kernel) and normalize=False (D5a external). Uses epilog_sync_bar + c_pipe for SMEM→GMEM, replacing epilogue_tma_store.
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MAY_26_2026_PLAN.md
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# Progress check: you're moving fast and in the right direction
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Two days ago you had stages A, B, partial C, an unresolved TMEM round-trip blocker, and SWA/sink merge unstarted. Today you have **D5 complete** (single-tile and multi-tile via Python KV merge, cos 0.999996), **SwiGLU clamping landed in the fused kernel** (paper §4.2.3 clamps are in lines 2192-2201), **D3/D4 masks in-kernel**, **D5c sink-bias-as-logit insight that obsoleted D5d**, and a thoughtful workaround for the TMEM corruption that lets you ship correct multi-tile attention right now via per-segment LSE merge. The Python KV merge cos at 0.999998 says the math is airtight.
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Three things genuinely impress me:
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The **"sink merge is a single softmax over [S_comp, S_swa + attn_sink]"** realization in D5c is the right insight and saves you the entire D5d fused-merge epilogue. That you discovered it through implementation rather than reading the FlashMLA formula and porting it literally is a sign of real understanding.
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You **clearly distinguished the two TMEM blockers** — Issue 1 (round-trip corruption from hand-built atoms) vs Issue 2 (rescale for kt>0) — and the "external normalization is exact" framing in the doc shows you understand that emitting unnormalized O + LSE is not a workaround, it's a *better* design for FlashAttention-style attention because it composes (which is exactly what enabled D5c to be one kernel instead of two).
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You **scrupulously protected the proven path** — the const_expr guards around `n_kv_tiles > 1` for the rescale code, the const_expr guards around `not self.normalize` for LSE, the hd=64 regression test invariant. The fact that hd=64/128/256 all hold at cos 0.999998 after all this churn is unusual in low-level kernel work.
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The few things that did regress or get tangled, you correctly identified: hd=512 MLIR hang, multi-CTA flat_divide layout mismatch. Both are toolchain/refactor problems, not architectural mistakes.
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---
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# About the blocker — you already have the fix in your codebase
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I want to point this out before suggesting anything new, because it changes the framing: **you've been doing the correct correction_epilog pattern in `fused_swiglu.py` for months.** Look at lines 2021, 2064-2078:
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```python
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tCtAcc_transformed = transform_partitioned_tensor_layout(tCtAcc_base)
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# ...
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tiled_copy_t2r, tTR_tAcc_base_epi, tTR_rAcc = epilogue_tmem_copy_and_partition(
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self, tidx, tCtAcc_transformed, tCgC_transformed,
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epi_tile, use_2cta_instrs,
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)
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tTR_rC = cute.make_rmem_tensor(tTR_rAcc.shape, self.c_dtype)
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tiled_copy_r2s, tRS_rC, tRS_sC = epilogue_smem_copy_and_partition(
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self, tiled_copy_t2r, tTR_rC, tidx, sC
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)
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```
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Then in the subtile loop you do exactly what FMHA needs:
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```python
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cute.copy(tiled_copy_t2r, tTR_tAcc_mn, tTR_rAcc) # TMEM → REGS via paired atom
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acc_vec = tiled_copy_r2s.retile(tTR_rAcc).load() # registers in flight
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# ... SwiGLU + clamp here ... # modify in registers
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tRS_rC.store(acc_vec_bf16)
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cute.copy(tiled_copy_r2s, tRS_rC, tRS_sC[(None, None, None, c_buffer)]) # REGS → SMEM
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# ... TMA store SMEM → GMEM ...
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```
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**One-way trip. No TMEM round-trip. Library-paired atoms.** Exactly what your STAGE_D.md identifies as the proper fix. You've literally been using this in the MoE epilogue every time the kernel runs SwiGLU. The reason it works in MoE and not in your FMHA isn't a fundamental impossibility — it's that the FMHA epilogue currently uses `epilogue_tma_store` (which reads from TMEM directly with its own internal atoms) instead of the `epilogue_tmem_copy_and_partition` + `epilogue_smem_copy_and_partition` pair.
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The README note about "tma_partition can't be called inside if warp_idx blocks" was the blocker that pushed you toward `epilogue_tma_store` originally — but the MoE kernel calls `cpasync.tma_partition` for `bSG_sC, bSG_gC_partitioned` from inside the `if warp_idx < self.mma_warp_id:` block (line 2082). So either that constraint has been worked around, or it was never actually a constraint — possibly an issue with where the call sat in the control flow.
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# Sketch of the FMHA correction epilogue
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Here's the structure to replace lines 549-597 of `fmha.py`. I'm writing this against your existing kernel's conventions (your variable names, your barrier IDs, your `sfw_idx`):
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```python
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# === FMHA EPILOGUE — one-way TMEM → REGS → SMEM → GMEM ===
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# Replaces the current 'epilogue_tma_store' + TMEM round-trip normalize.
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# Pattern proven in dsv4/kernels/gemm/fused_swiglu.py (lines 2021, 2064-2229).
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# ---- Setup (run once per kernel, not per kt) ----
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# Move this block ABOVE the kt loop so partitioning happens once.
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# Put it AFTER tmem.allocate but BEFORE the kt loop, alongside the
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# existing tStS/tOtO0 setup.
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# Transform the partitioned O tensor (TMEM acc) into the epilogue's expected layout.
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# tOtO0 is the TMEM tensor for O; we need to transform it the way MoE does for tCtAcc.
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tCtO_transformed = utils.gemm.sm100.transform_partitioned_tensor_layout(tOtO0)
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# Same for the GMEM tensor — use the existing tCgC (your pv_thr.partition_C(gC)).
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tCgC_transformed = utils.gemm.sm100.transform_partitioned_tensor_layout(tCgC)
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# Create the paired atoms — this is the magic. tiled_copy_t2r and tiled_copy_r2s
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# share addressing so the round trip is lossless.
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tiled_copy_t2r, tTR_tO_base, tTR_rO = (
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utils.gemm.sm100.epilogue_tmem_copy_and_partition(
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self, sfw_idx, tCtO_transformed, tCgC_transformed,
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epi_tile, self.use_2cta_instrs,
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)
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)
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# Register tile for the to-be-written output (BF16).
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tTR_rC = cute.make_rmem_tensor(tTR_rO.shape, self.c_dtype)
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tiled_copy_r2s, tRS_rC, tRS_sC = (
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utils.gemm.sm100.epilogue_smem_copy_and_partition(
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self, tiled_copy_t2r, tTR_rC, sfw_idx, sC,
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)
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)
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# TMA partition for SMEM → GMEM store, matching the MoE pattern.
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tCgC_epi = cute.flat_divide(tCgC_transformed, epi_tile)
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bSG_sC, bSG_gC_partitioned = cpasync.tma_partition(
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tma_c, 0, cute.make_layout(1),
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cute.group_modes(sC, 0, 2),
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cute.group_modes(tCgC_epi, 0, 2),
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)
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# For single-CTA grid (your current case) the coordinates are all 0.
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# For multi-CTA later, this is where (m_tile, head, batch) lands.
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bSG_gC = bSG_gC_partitioned[(None, None, None, 0, 0, 0)]
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# Epilogue sync barrier — separate from softmax_done_bar to avoid double-wait
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epi_sync_bar = pipeline.NamedBarrier(
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barrier_id=self.epilog_sync_bar_id,
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num_threads=32 * len(self.epilogue_warp_id),
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)
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# C-store pipeline (same as MoE)
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c_grp = pipeline.CooperativeGroup(
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pipeline.Agent.Thread, 32 * len(self.epilogue_warp_id),
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)
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c_pipeline = pipeline.PipelineTmaStore.create(
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num_stages=self.num_c_stage, producer_group=c_grp,
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)
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# ---- After the kt loop, after final_o_bar.arrive_and_wait() ----
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# Compute 1/row_sum once per row, in registers. No TMEM round-trip.
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# row_sum was tracked across all kt; it's per-row in each thread.
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row_max_safe = row_max
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if row_max == -Float32.inf:
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row_max_safe = Float32(0.0)
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inv_row_sum = Float32(1.0) / row_sum
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# tTR_tO has shape (..., subtile_cnt). Iterate subtiles.
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subtile_cnt = cute.size(tTR_tO_base.shape, mode=[3])
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for subtile_idx in cutlass.range(subtile_cnt):
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# TMEM → REGS using the paired atom (the lossless path).
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tTR_tO_mn = tTR_tO_base[(None, None, None, subtile_idx)]
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cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)
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# Normalize and convert in registers. This is where the fix lives.
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# When normalize=True: divide by row_sum, cast to BF16.
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# When normalize=False (D5a): cast raw O to BF16, skip the divide.
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acc_vec = tiled_copy_r2s.retile(tTR_rO).load()
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if const_expr(self.normalize):
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acc_vec = acc_vec * inv_row_sum
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tRS_rC.store(acc_vec.to(self.c_dtype))
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# REGS → SMEM
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c_buffer = subtile_idx % self.num_c_stage
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cute.copy(tiled_copy_r2s, tRS_rC, tRS_sC[(None, None, None, c_buffer)])
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cute.arch.fence_proxy("async.shared", space="cta")
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epi_sync_bar.arrive_and_wait()
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# SMEM → GMEM (one warp does the TMA)
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if warp_idx == self.epilogue_warp_id[0]:
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cute.copy(
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tma_c,
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bSG_sC[(None, c_buffer)],
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bSG_gC[(None, subtile_idx)],
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)
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c_pipeline.producer_commit()
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c_pipeline.producer_acquire()
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epi_sync_bar.arrive_and_wait()
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c_pipeline.producer_tail()
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# LSE still emitted for callers that want it (composes with D5 / external merge)
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if const_expr(not self.normalize):
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_row_max_safe = row_max
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if row_max == -Float32.inf:
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_row_max_safe = Float32(0.0)
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_ln2 = Float32(0.6931471805599453)
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lse_val = cute.math.log(row_sum, fastmath=True) + _row_max_safe * _ln2
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mLSE[sfw_idx, Int32(0), Int32(0)] = lse_val
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mRowSums[sfw_idx, Int32(0), Int32(0)] = row_sum
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tmem.relinquish_alloc_permit()
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tmem.free(tmem_ptr)
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```
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This same pattern also gives you **D1.5 issue 2 (per-kt O rescale)** essentially for free. The rescale logic currently inside `if kt > 0:` (lines 524-544) becomes:
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```python
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# Per-kt O rescale (TMEM → REGS → multiply by acc_scale → REGS → TMEM)
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if const_expr(self.n_kv_tiles > 1):
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if kt > 0:
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for subtile_idx in cutlass.range(subtile_cnt):
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tTR_tO_mn = tTR_tO_base[(None, None, None, subtile_idx)]
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cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)
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# Modify in registers (this is what the hand-built atoms got wrong)
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for k in cutlass.range(cute.size(tTR_rO), vectorize=True):
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tTR_rO[k] = tTR_rO[k] * acc_scale
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# Same paired atom for the way back — addressing matches.
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cute.copy(tiled_copy_t2r.retile_to_S(), tTR_rO, tTR_tO_mn)
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cute.arch.fence_view_async_tmem_store()
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```
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The key claim: `tiled_copy_t2r` carries an internal addressing scheme that's consistent for both the load and (when you use its `retile_to_S`-built store) the store. That's the whole reason the MoE epilogue works — paired atoms from the same partitioning, not two independently-constructed atoms whose addressings happen to mismatch.
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**Three caveats** before you run this:
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The exact CUTLASS helper API for the "store back to TMEM" direction varies between CuTeDSL versions — `tiled_copy_t2r.retile_to_S()` is one form, some versions expose a separate `epilogue_tmem_store_and_partition` helper, and some require you to compose `make_tmem_copy(tcgen05.copy.St32x32bOp(...), tTR_tO_base)` from the same `tTR_tO_base` you built the load from. Print `dir(utils.gemm.sm100)` on B200 to see what's available in your version. The principle is the same: derive the store atom from the same partition object as the load.
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The `transform_partitioned_tensor_layout` call may need different handling for `tOtO0` (TMEM iterator with offset) vs the MoE's `tCtAcc_base` (fresh TMEM pointer). If it errors, build `tCtO_transformed` by constructing a fresh tensor at `tmem_ptr + self.tmem_o0_offset` with `tCtO_fake.layout`, the way `tCtO_base` is built at line 566.
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The CuTeDSL region-isolation issue from the README — if `tma_partition` inside the `if warp_idx < self.mma_warp_id:` block still throws "weakly congruent," move the `cpasync.tma_partition(tma_c, ...)` call to before the `if warp_idx` branches. It's pure layout construction and doesn't depend on per-warp state. The MoE kernel gets away with it inside the block because of where in the IR-region tree the call sits; if your FMHA hits the issue, the partition can hoist to anywhere after `pipeline_init_wait`.
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# What unblocks the moment this lands
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**D1.5 issue 1** (TMEM round-trip corruption): gone. The paired-atom load/store doesn't round-trip in the sense that caused the 3% error — the same addressing covers both directions, no transcoding.
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**D1.5 issue 2** (per-kt rescale): gone. Same atoms used for rescale produce correct data.
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**Multi-tile attention without Python merge**: enabled. You can run s_k=1152 in a single kernel launch instead of 9. That's a real perf win at decode where launch overhead matters.
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**NVFP4-1.2** (fuse FP4 quant into the FMHA output → wo_a path): unblocked. The register-level modification slot (`acc_vec * inv_row_sum` above) is also where amax reduction + FP4 packing happens, exactly the way SwiGLU + clamping sits in the MoE epilogue.
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**Multi-CTA grid (D2 deferred work)**: this is the harder one. Once you're using `flat_divide(tCgC_transformed, epi_tile)` + `tma_partition` for the C store, the flat_divide vs local_tile mismatch you hit in D2.3-2.6 mostly evaporates — the MoE kernel uses exactly `cute.flat_divide(tCgC_transformed, epi_tile)` to do its multi-CTA tile addressing (line 2081), and the runtime block coords land via `bSG_gC_partitioned[(None, None, None, *mma_tile_coord_mnl)]`. The current per-head Python launch becomes the multi-CTA grid as soon as you can index that final coordinate with `(bidx, bidy, bidz)` from `cute.arch.block_idx()`.
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# After the epilogue lands, the next things in order
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I'd sequence these:
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**1. Verify hd=64/128/256 regress at cos 0.999998** with the new epilogue, both `normalize=True` and `normalize=False`. The atom invariant means this should just work, but verify before moving on. Add a multi-tile s_k=256 test that asserts cos > 0.99 with the new fused rescale to confirm Issue 2 is dead.
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**2. Multi-CTA grid (D2.3-2.6 finish)** using the unblocked `flat_divide` + `tma_partition` path. Per-head launch works but is wasteful — at decode T=1, n_h=128, you're paying 128 separate kernel launches. A single grid=(1, 128, batch) launch with proper per-CTA Q indexing collapses this to one launch and lets MQA K/V sharing become possible later via cluster shape.
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**3. NVFP4-1.1 (fuse FP4 quant into SwiGLU epilogue)** — independent of FMHA, biggest bandwidth win in the codebase. The MoE epilogue already has all the structure needed: register-level modification slot, paired atoms, SMEM stage, TMA store. You just replace `tRS_rC.store(acc_vec_bf16)` with per-microblock amax + scale + FP4 pack + write to an FP4 SMEM buffer + TMA store the FP4 + parallel TMA store of the FP8 scales. Same epilogue, different output layout.
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**4. NVFP4-1.2 (fuse FP4 into FMHA's inverse-RoPE → wo_a path)** — directly enabled by step 1. The acc_vec modification slot in the new FMHA epilogue is exactly where the inverse-RoPE rotation + FP4 quantization belongs. Wo_a then reads FP4.
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**5. The hd=512 MLIR hang** — I'd actually push this lower in priority. With multi-CTA grid working and per-head launch as a fallback, you can run hd=512 via the head-packed M-dimension approach (Q reshaped to `(n_h*T, hd, 1)` per your D2 notes), and the multi-tile kernel handles s_k=1152 in one launch. That's a complete decode path. Solving the MLIR backend hang is real work — option 3 (raw CUTLASS C++) is probably the most realistic if NVIDIA can't fix it, and writing one hd=512-specific .cu file is a fraction of the work of fighting MLIR. But it's not the highest-leverage thing right now.
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**6. The indexer kernel rewrite** (paper §5.2.1 — FP4 tensor-core scoring) sits in your speculative bucket but I'd promote it now that D5 is done and you have a clear FP4 pipeline pattern from steps 3-4. It's the single largest remaining perf gap in the inference path, and you have the FP4 patterns established to do it cleanly.
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The arc of this work has been right. Each step removed a real blocker, kept the proven path intact, and the workarounds you chose (Python KV merge, per-head launch) were principled choices that bought you forward progress without committing to wrong abstractions. The epilogue is the next thing that unlocks the production path — and the template for fixing it has been in your repo all along.
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@@ -2,7 +2,8 @@
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Migrated from tests/unit/test_fmha_v3_stage_c.py — Stage C proven path.
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P stored to TMEM via register bridge, PV reads from TMEM.
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O rescale via correction_rescale atoms, O normalization via TMEM round-trip.
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O rescale + normalization via correction epilogue (one-way TMEM→REGS→SMEM→GMEM)
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using paired atoms from epilogue_tmem_copy_and_partition / epilogue_smem_copy_and_partition.
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"""
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import torch, cutlass, cutlass.cute as cute, cutlass.utils as utils, cutlass.pipeline as pipeline
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from cutlass.cute.nvgpu import cpasync, tcgen05
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@@ -10,6 +11,11 @@ from cutlass import Float32, BFloat16, Int32, Boolean, const_expr
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from cutlass.utils import LayoutEnum
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from cutlass.utils.tmem_allocator import find_tmem_tensor_col_offset
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from cutlass.utils.blackwell_helpers import get_smem_store_op
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from cutlass.utils.gemm.sm100 import (
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transform_partitioned_tensor_layout,
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epilogue_tmem_copy_and_partition,
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epilogue_smem_copy_and_partition,
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)
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import cuda.bindings.driver as cuda
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import cutlass.torch as ct
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import math
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@@ -392,36 +398,51 @@ class FmhaKernel:
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row_sum = Float32(0.0)
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scale_log2 = Float32(self.scale_softmax_log2)
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# O rescale atoms (hand-constructed, using composition layout like CUTLASS correction_rescale)
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# Only needed when there are multiple KV tiles (O must be rescaled per-kt).
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# With n_kv_tiles=1, no rescale is needed (kt is always 0).
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corr_tile_size = 16
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n_corr_tiles = self.pv_n_tile // corr_tile_size
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if const_expr(self.n_kv_tiles > 1):
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cO = cute.make_identity_tensor((self.pv_mma_tiler[0], self.pv_mma_tiler[1]))
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tOcO = pv_thr.partition_C(cO)
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tOtO_i_layout = cute.composition(tOtO0.layout, cute.make_layout((128, corr_tile_size)))
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tOcO_i_layout = cute.composition(tOcO.layout, cute.make_layout((128, corr_tile_size)))
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tOtO_i = cute.make_tensor(tOtO0.iterator, tOtO_i_layout)
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tOcO_i = cute.make_tensor(tOcO.iterator, tOcO_i_layout)
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tmem_load_o_atom = cute.make_copy_atom(
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tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
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self.acc_dtype,
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)
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tmem_store_o_atom = cute.make_copy_atom(
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tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),
|
||||
self.acc_dtype,
|
||||
)
|
||||
tiled_tmem_load_o = tcgen05.make_tmem_copy(tmem_load_o_atom, tOtO_i)
|
||||
tiled_tmem_store_o = tcgen05.make_tmem_copy(tmem_store_o_atom, tOtO_i)
|
||||
thr_tmem_load_o = tiled_tmem_load_o.get_slice(sfw_idx)
|
||||
thr_tmem_store_o = tiled_tmem_store_o.get_slice(sfw_idx)
|
||||
tTMEM_LOADtO = thr_tmem_load_o.partition_S(tOtO_i)
|
||||
tTMEM_LOADcO = thr_tmem_load_o.partition_D(tOcO_i)
|
||||
tTMEM_STOREtO = thr_tmem_store_o.partition_D(tOtO_i)
|
||||
tTMrO = cute.make_rmem_tensor(
|
||||
(tTMEM_LOADcO.shape, 128 // corr_tile_size), self.acc_dtype
|
||||
)
|
||||
# ============================================================
|
||||
# CORRECTION EPILOGUE SETUP (paired atoms, one-way TMEM→REGS→SMEM→GMEM)
|
||||
# Pattern proven in dsv4/kernels/gemm/fused_swiglu.py (lines 2021-2076).
|
||||
# Replaces broken hand-constructed TMEM round-trip (D1.5 fix).
|
||||
# ============================================================
|
||||
# Build the O accumulator tensor at the TMEM pointer + o0_offset.
|
||||
# This is the TMEM source for the correction epilogue.
|
||||
tCtO_base = cute.make_tensor(tmem_ptr + self.tmem_o0_offset, tCtO_fake.layout)
|
||||
tCtO_transformed = transform_partitioned_tensor_layout(tCtO_base)
|
||||
tCgC_transformed = transform_partitioned_tensor_layout(tCgC)
|
||||
|
||||
# Paired atoms: tiled_copy_t2r (TMEM→REGS) and tiled_copy_r2s (REGS→SMEM)
|
||||
# share addressing so the round trip is lossless.
|
||||
tiled_copy_t2r, tTR_tO_base, tTR_rO = epilogue_tmem_copy_and_partition(
|
||||
self, sfw_idx, tCtO_transformed, tCgC_transformed,
|
||||
epi_tile, self.use_2cta_instrs,
|
||||
)
|
||||
# Register tile for BF16 output (after normalization/conversion)
|
||||
tTR_rC = cute.make_rmem_tensor(tTR_rO.shape, self.c_dtype)
|
||||
tiled_copy_r2s, tRS_rC, tRS_sC = epilogue_smem_copy_and_partition(
|
||||
self, tiled_copy_t2r, tTR_rC, sfw_idx, sC,
|
||||
)
|
||||
|
||||
# TMA partition for SMEM → GMEM store (same as MoE pattern)
|
||||
tCgC_epi = cute.flat_divide(tCgC_transformed, epi_tile)
|
||||
bSG_sC, bSG_gC_partitioned = cpasync.tma_partition(
|
||||
tma_c, 0, cute.make_layout(1),
|
||||
cute.group_modes(sC, 0, 2),
|
||||
cute.group_modes(tCgC_epi, 0, 2),
|
||||
)
|
||||
# Single-CTA grid: all block coordinates are 0
|
||||
bSG_gC = bSG_gC_partitioned[(None, None, None, 0, 0, 0)]
|
||||
|
||||
# Epilogue sync barrier + C-store pipeline
|
||||
epilog_sync_bar = pipeline.NamedBarrier(
|
||||
barrier_id=self.epilog_sync_bar_id,
|
||||
num_threads=32 * len(self.epilogue_warp_id),
|
||||
)
|
||||
c_grp = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32 * len(self.epilogue_warp_id))
|
||||
c_pipe = pipeline.PipelineTmaStore.create(num_stages=self.num_c_stage, producer_group=c_grp)
|
||||
|
||||
# Group modes for the subtile iteration (same pattern as fused_swiglu)
|
||||
tTR_tO_grouped = cute.group_modes(tTR_tO_base, 3, cute.rank(tTR_tO_base))
|
||||
bSG_gC_grouped = cute.group_modes(bSG_gC, 1, cute.rank(bSG_gC))
|
||||
subtile_cnt = cute.size(tTR_tO_grouped.shape, mode=[3])
|
||||
|
||||
for kt in range(self.n_kv_tiles):
|
||||
si_handle = s_cons.wait_and_advance()
|
||||
@@ -521,26 +542,23 @@ class FmhaKernel:
|
||||
k2 = k_coord // 64
|
||||
_sP_nostage[(m_coord, k0), 0, (k1, k2)] = rP_bf16[(j0, 0), j1, 0, 0]
|
||||
cute.arch.fence_proxy("async.shared", space="cta")
|
||||
# O rescale for kt > 0 using paired atoms (D1.5 fix).
|
||||
# One-way TMEM→REGS (multiply by acc_scale) → TMEM via paired store atom.
|
||||
# The paired atom's addressing is consistent for both load and store,
|
||||
# so this does NOT suffer from the layout mismatch that broke the
|
||||
# hand-constructed Ld32x32bOp/St32x32bOp round-trip.
|
||||
if const_expr(self.n_kv_tiles > 1):
|
||||
if kt > 0:
|
||||
for i in range(n_corr_tiles):
|
||||
tTMrO_i_ = tTMrO[None, i]
|
||||
tTMrO_i_layout = cute.composition(
|
||||
tTMrO_i_.layout, cute.make_layout(tTMrO.shape[0])
|
||||
)
|
||||
tTMrO_i = cute.make_tensor(tTMrO_i_.iterator, tTMrO_i_layout)
|
||||
tTMEM_LOADtO_i = cute.make_tensor(
|
||||
tTMEM_LOADtO.iterator + i * corr_tile_size,
|
||||
tTMEM_LOADtO.layout,
|
||||
)
|
||||
tTMEM_STOREtO_i = cute.make_tensor(
|
||||
tTMEM_STOREtO.iterator + i * corr_tile_size,
|
||||
tTMEM_STOREtO.layout,
|
||||
)
|
||||
cute.copy(tiled_tmem_load_o, tTMEM_LOADtO_i, tTMrO_i)
|
||||
for k in cutlass.range(cute.size(tTMrO_i), vectorize=True):
|
||||
tTMrO_i[k] = tTMrO_i[k] * acc_scale
|
||||
cute.copy(tiled_tmem_store_o, tTMrO_i, tTMEM_STOREtO_i)
|
||||
for subtile_idx in cutlass.range(subtile_cnt, unroll=1):
|
||||
tTR_tO_mn = tTR_tO_grouped[(None, None, None, subtile_idx)]
|
||||
cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)
|
||||
# Modify in registers — acc_scale is per-row, same for all elements
|
||||
# in this thread's fragment. (Each thread handles one row.)
|
||||
for k in cutlass.range(cute.size(tTR_rO), vectorize=True):
|
||||
tTR_rO[k] = tTR_rO[k] * acc_scale
|
||||
# Store back to TMEM via the paired atom's store direction.
|
||||
# Use retile_to_S() to get the store-compatible layout.
|
||||
cute.copy(tiled_copy_t2r.retile_to_S(), tTR_rO, tTR_tO_mn)
|
||||
cute.arch.fence_view_async_tmem_store()
|
||||
|
||||
si_handle.release()
|
||||
@@ -550,30 +568,52 @@ class FmhaKernel:
|
||||
final_o_bar.arrive_and_wait()
|
||||
|
||||
# ============================================================
|
||||
# EPILOGUE: TMA store O to GMEM + compute LSE
|
||||
# CORRECTION EPILOGUE: one-way TMEM → REGS → SMEM → GMEM
|
||||
# ============================================================
|
||||
# The raw un-normalized O in TMEM is perfect (cos 0.999998).
|
||||
# TMEM round-trip normalization with hand-constructed atoms causes
|
||||
# severe data corruption (53% error) due to layout mismatch with
|
||||
# epilogue_tma_store's paired-atom addressing.
|
||||
# Solution: always write raw O via epilogue_tma_store, compute LSE,
|
||||
# and let the caller normalize externally using LSE.
|
||||
# This is the D5a path — production-quality with zero precision loss.
|
||||
# The TMEM round-trip normalization (normalize=True) is tracked as D1.5.
|
||||
# Uses paired atoms from epilogue_tmem_copy_and_partition /
|
||||
# epilogue_smem_copy_and_partition (same pattern as fused_swiglu.py).
|
||||
# This is the D1.5 fix: no TMEM round-trip corruption because we
|
||||
# use library-paired atoms for the one-way trip through registers.
|
||||
# ============================================================
|
||||
|
||||
# TMA store via CUTLASS epilogue_tma_store (reads raw O from TMEM)
|
||||
tCtO_base = cute.make_tensor(tmem_ptr + self.tmem_o0_offset, tCtO_fake.layout)
|
||||
c_grp = pipeline.CooperativeGroup(pipeline.Agent.Thread, 32 * len(self.epilogue_warp_id))
|
||||
c_pipe = pipeline.PipelineTmaStore.create(num_stages=self.num_c_stage, producer_group=c_grp)
|
||||
acc_cons_st = pipeline.make_pipeline_state(
|
||||
pipeline.PipelineUserType.Consumer, self.num_acc_stage
|
||||
)
|
||||
acc_cons_st = utils.gemm.sm100.epilogue_tma_store(
|
||||
self, sfw_idx, warp_idx, tma_c, tCtO_base, sC, tCgC, epi_tile,
|
||||
0, const_expr(lambda x: x), (0, 0, 0),
|
||||
acc_cons_st, acc_pipe, c_pipe,
|
||||
)
|
||||
# Compute inv_row_sum for normalization (in registers, no TMEM round-trip)
|
||||
_row_max_safe = row_max
|
||||
if row_max == -cutlass.Float32.inf:
|
||||
_row_max_safe = Float32(0.0)
|
||||
if const_expr(self.normalize):
|
||||
inv_row_sum = Float32(1.0) / row_sum
|
||||
|
||||
# Iterate over output subtiles: TMEM → REGS → (normalize/convert) → SMEM → GMEM
|
||||
for subtile_idx in cutlass.range(subtile_cnt, unroll=1):
|
||||
# TMEM → REGS using the paired atom (lossless)
|
||||
tTR_tO_mn = tTR_tO_grouped[(None, None, None, subtile_idx)]
|
||||
cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)
|
||||
|
||||
# Register-level modification:
|
||||
# - normalize=True: divide by row_sum, cast to BF16
|
||||
# - normalize=False: just cast to BF16 (un-normalized O for D5a)
|
||||
acc_vec = tiled_copy_r2s.retile(tTR_rO).load()
|
||||
if const_expr(self.normalize):
|
||||
acc_vec = acc_vec * inv_row_sum
|
||||
tRS_rC.store(acc_vec.to(self.c_dtype))
|
||||
|
||||
# REGS → SMEM
|
||||
c_buffer = subtile_idx % self.num_c_stage
|
||||
cute.copy(tiled_copy_r2s, tRS_rC, tRS_sC[(None, None, None, c_buffer)])
|
||||
cute.arch.fence_proxy("async.shared", space="cta")
|
||||
epilog_sync_bar.arrive_and_wait()
|
||||
|
||||
# SMEM → GMEM (one warp does the TMA store)
|
||||
if warp_idx == self.epilogue_warp_id[0]:
|
||||
cute.copy(
|
||||
tma_c,
|
||||
bSG_sC[(None, c_buffer)],
|
||||
bSG_gC_grouped[(None, subtile_idx)],
|
||||
)
|
||||
c_pipe.producer_commit()
|
||||
c_pipe.producer_acquire()
|
||||
epilog_sync_bar.arrive_and_wait()
|
||||
|
||||
c_pipe.producer_tail()
|
||||
|
||||
# Compute LSE: lse = ln(row_sum) + row_max * ln(2)
|
||||
@@ -584,9 +624,6 @@ class FmhaKernel:
|
||||
# sfw_idx maps directly to the row index in the attention matrix.
|
||||
# All 128 threads write independently to mLSE[sfw_idx] — no sync needed.
|
||||
if const_expr(not self.normalize):
|
||||
_row_max_safe = row_max
|
||||
if row_max == -cutlass.Float32.inf:
|
||||
_row_max_safe = Float32(0.0)
|
||||
_ln2 = Float32(0.6931471805599453) # ln(2)
|
||||
lse_val = cute.math.log(row_sum, fastmath=True) + _row_max_safe * _ln2
|
||||
mLSE[sfw_idx, Int32(0), Int32(0)] = lse_val
|
||||
|
||||
Reference in New Issue
Block a user