feat: 6-warp TMA FMHA kernel + test — TMA for K loads
This commit is contained in:
@@ -1,22 +1,39 @@
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/**
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* DSV4 FMHA — TMA async loads, 4-warp specialization.
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* DSV4 FMHA — 6-warp specialized kernel with TMA async loads for Blackwell SM100.
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*
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* Based on the proven test_fmha_gen pattern, extended with TMA async loads
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* for K and V.
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* ==================================================================
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* WARP SPECIALIZATION (same as fmha_6warp.cuh)
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* ==================================================================
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* Warp 0-3 (tid 0-127): Softmax + correction + epilogue
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* Warp 4 (tid 128-159): MMA (QK + PV)
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* Warp 5 (tid 160-191): TMA loads (K, V) + Q direct load + P fill
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*
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* DESIGN:
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* - 4 warps (128 threads), __launch_bounds__(128)
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* - Warp 0: TMA load + softmax + TMEM read/epilogue
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* - Warp 1: MMA + TMEM alloc
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* - Warps 2-3: softmax + epilogue
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* - TMA: warp 0 lane 0 issues, all threads wait via mbarrier
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* - mbarrier: init once, arrive.expect_tx after TMA, phase parity tracking
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* - Q loaded directly (T=1 decode for now), K/V via TMA
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* - Per-K-sub-tile Q loading (128, 16) into sQ0
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* - Per-K-sub-tile K loading via TMA into sTmaBuf, then canonical sK0
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* - MMA: tid==0 calls umma_ss_f16
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* - Multi-row softmax: warps 0-3 each handle 32 rows
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* - PV: per-N-sub-tile, P in registers, V via TMA
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* ==================================================================
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* TMA LOAD PIPELINE
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* ==================================================================
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* - Q: direct GMEM load (T=1 decode, only 1 row; small enough to not benefit from TMA)
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* - K: TMA async load via cp.async.bulk.tensor.2d with mbarrier completion
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* - V: TMA async load (future; currently direct GMEM load)
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* - mbarrier: init once, arrive.expect_tx after TMA issue, phase parity tracking
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* - ALL threads wait on mbarrier (works correctly at 192 threads, verified on B200)
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*
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* ==================================================================
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* SMEM LAYOUT
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* ==================================================================
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* All SMEM regions are 128-byte aligned for TMA compatibility.
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* sTmaBuf is used as a staging area: TMA writes row-major data here,
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* then it's converted to canonical layout for MMA.
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*
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* sTmemBase: 4 bytes
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* sMbar: 16 bytes (128-byte aligned)
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* sTmaBuf: TILE_SZ * 2 bytes (128-byte aligned) — TMA staging buffer
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* sQ0: TILE_SZ * 2 bytes (128-byte aligned) — canonical for MMA
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* sK0: TILE_SZ * 2 bytes (128-byte aligned) — canonical for MMA
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* sPk: TILE_SZ * 2 bytes (128-byte aligned) — canonical for PV
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* sV: V_SUB_SZ bytes (128-byte aligned) — canonical for PV
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* sRowMax: MAX_ROWS * 4 bytes
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* sRowSum: MAX_ROWS * 4 bytes
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* s_p_vals: SK_TILE * 4 bytes
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*/
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#pragma once
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@@ -27,77 +44,73 @@
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namespace dsv4::kernels::attention {
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struct FmhaTmaParams {
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const bf16_t* __restrict__ q;
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const bf16_t* __restrict__ k;
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const bf16_t* __restrict__ v; // direct GMEM pointer for V
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bf16_t* __restrict__ o;
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float* __restrict__ lse;
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int s_k, T;
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float scale;
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int head_dim;
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int q_head_stride, q_batch_stride;
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int k_head_stride, k_batch_stride;
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int v_head_stride, v_batch_stride;
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int o_head_stride, o_batch_stride;
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int lse_head_stride, lse_batch_stride;
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CUtensorMap* __restrict__ tma_k;
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CUtensorMap* __restrict__ tma_v;
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};
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template<int HD, int SK_TILE = 128>
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__global__ void __launch_bounds__(128)
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fmha_tma_kernel(FmhaTmaParams params) {
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__global__ void __launch_bounds__(192)
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fmha_6warp_tma_kernel(
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const bf16_t* __restrict__ q,
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CUtensorMap* __restrict__ tma_k,
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const bf16_t* __restrict__ v,
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bf16_t* __restrict__ o,
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float* __restrict__ lse,
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int s_k,
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float scale
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) {
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static constexpr int NKT_QK = HD / MMA_K_BF16;
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static constexpr int NKT_PV = SK_TILE / MMA_K_BF16;
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static constexpr int N_NSUB = HD / 16;
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static constexpr int TILE_SZ = 128 * MMA_K_BF16;
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static constexpr int V_SUB_SZ = 16 * MMA_K_BF16; // (16,16) canonical
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static constexpr int TMEM_N = (HD <= 128) ? 128 : 256;
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static constexpr int MAX_ROWS = 128;
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static constexpr int CORES_MN = 128 / 8;
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static constexpr int CORES_MN = 128 / 8; // 16
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static constexpr int NUM_READS = SK_TILE / 8;
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static constexpr int TMA_TILE_BYTES = TILE_SZ * sizeof(bf16_t);
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const int head_idx = blockIdx.y;
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const int batch_idx = blockIdx.z;
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const int tid = threadIdx.x;
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const int wid = tid / 32;
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const int lane = tid % 32;
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const int T = params.T;
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const int s_k = params.s_k;
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const float scale = params.scale;
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bf16_t* __restrict__ q_head = (bf16_t*)params.q + head_idx * params.q_head_stride + batch_idx * params.q_batch_stride;
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bf16_t* __restrict__ o_head = params.o + head_idx * params.o_head_stride + batch_idx * params.o_batch_stride;
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const bf16_t* __restrict__ v_head = (const bf16_t*)params.v + head_idx * params.v_head_stride + batch_idx * params.v_batch_stride;
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float* __restrict__ lse_head = params.lse ? params.lse + head_idx * params.lse_head_stride + batch_idx * params.lse_batch_stride : nullptr;
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// Warp role predicates
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const bool is_softmax_warp = (wid < 4);
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const bool is_mma_warp = (wid == 4);
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const bool is_load_warp = (wid == 5);
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CUtensorMap* __restrict__ tma_k = params.tma_k;
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CUtensorMap* __restrict__ tma_v = params.tma_v;
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// ==================================================================
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// SMEM allocation — all 128-byte aligned for TMA compatibility
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// ==================================================================
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// ================================================================
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// SMEM allocation — all 128-byte aligned
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// ================================================================
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extern __shared__ __align__(128) char sbuf[];
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size_t off = 0;
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uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off = 4;
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uint32_t* sTmemBase = (uint32_t*)(sbuf + off); off += 4;
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off = (off + 127) & ~(size_t)127; // 128-byte align
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uint64_t* sMbar = (uint64_t*)(sbuf + off); off += 16;
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off = (off + 127) & ~(size_t)127;
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bf16_t* sQ0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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bf16_t* sK0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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bf16_t* sTmaBuf = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 15) & ~(size_t)15;
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uint64_t* sMbar = (uint64_t*)(sbuf + off); off += 8;
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off = (off + 127) & ~(size_t)127;
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bf16_t* sQ0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sK0 = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sPk = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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off = (off + 127) & ~(size_t)127;
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bf16_t* sV = (bf16_t*)(sbuf + off); off += V_SUB_SZ * sizeof(bf16_t);
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float* sRowMax = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
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float* sRowSum = (float*)(sbuf + off); off += MAX_ROWS * sizeof(float);
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// sPk and sV for PV GEMM
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off = (off + 127) & ~(size_t)127;
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bf16_t* sPk = (bf16_t*)(sbuf + off); off += TILE_SZ * sizeof(bf16_t);
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bf16_t* sV = (bf16_t*)(sbuf + off); off += 16 * MMA_K_BF16 * sizeof(bf16_t); // (16,16) canonical for PV
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float* s_p_vals = (float*)(sbuf + off); off += SK_TILE * sizeof(float);
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// ==================================================================
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// Initialize
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// ==================================================================
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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// ================================================================
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// Initialize TMEM + mbarrier
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// ================================================================
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if (is_mma_warp) {
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tmem_alloc(__cvta_generic_to_shared(sTmemBase), TMEM_N);
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}
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if (tid == 0) {
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tma_mbarrier_init((uint32_t)__cvta_generic_to_shared(sMbar), 1);
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asm volatile("fence.mbarrier_init.release.cluster;" ::: "memory");
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@@ -107,195 +120,151 @@ fmha_tma_kernel(FmhaTmaParams params) {
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const uint32_t mbar_addr = (uint32_t)__cvta_generic_to_shared(sMbar);
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int phase = 0;
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const bool my_warp_active = (T <= 32) ? (wid == 0) : (wid < 4);
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const int my_row = my_warp_active ? (wid * 32 + lane) : 0;
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const bool my_row_active = my_warp_active && (my_row < T);
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// ==================================================================
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// QK GEMM → S in TMEM
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// ==================================================================
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{
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uint32_t idesc = make_idesc(128, 128);
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for (int kt = 0; kt < NKT_QK; kt++) {
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// Q sub-tile: direct load from GMEM
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for (int i = tid; i < TILE_SZ; i += 128) sQ0[i] = 0;
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// Write rows 0..T-1 in canonical layout
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for (int r = 0; r < T; r++) {
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for (int d = tid % 32; d < MMA_K_BF16; d += 32) {
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// Use warp-stride: each warp handles a subset of rows
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int my_r = wid * 32 / 128; // simplified: all warps contribute
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// Actually, let's use a simpler approach: all 128 threads load
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// ================================================================
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// QK GEMM loop: TMA for K, direct load for Q
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// ================================================================
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for (int kt = 0; kt < NKT_QK; kt++) {
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// ---- Warp 5: Load Q K-tile directly from GMEM ----
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if (is_load_warp) {
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for (int i = lane; i < TILE_SZ; i += 32) sQ0[i] = 0;
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for (int d = lane; d < MMA_K_BF16; d += 32) {
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int full_d = kt * MMA_K_BF16 + d;
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if (full_d < HD) {
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int ck = d / 8, lc = d % 8;
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sQ0[ck * CORES_MN * 64 + lc] = q[full_d];
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}
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}
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// Simpler: all 128 threads write Q row by row
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for (int d = tid; d < T * MMA_K_BF16; d += 128) {
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int r = d / MMA_K_BF16;
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int c = d % MMA_K_BF16;
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int full_d = kt * MMA_K_BF16 + c;
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if (full_d < HD && r < T) {
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int ck = c / 8, lc = c % 8, cm = r / 8, lr = r % 8;
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sQ0[ck * CORES_MN * 64 + cm * 64 + lr * 8 + lc] = q_head[r * HD + full_d];
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}
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}
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__syncthreads();
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// K sub-tile: TMA load + canonical
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if (wid == 0 && lane == 0) {
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tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)tma_k, mbar_addr, kt * MMA_K_BF16, 0);
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tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
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}
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tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
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__syncthreads();
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for (int i = tid; i < TILE_SZ; i += 128) sK0[i] = 0;
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for (int i = tid; i < s_k * MMA_K_BF16; i += 128) {
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int r = i / MMA_K_BF16, c = i % MMA_K_BF16;
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int ck = c / 8, lc = c % 8, tmn = r / 8, lr = r % 8;
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sK0[ck * CORES_MN * 64 + tmn * 64 + lr * 8 + lc] = sTmaBuf[i];
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}
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__syncthreads();
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// MMA
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if (tid == 0) {
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
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umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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}
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__syncthreads();
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}
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// ---- TMA load K sub-tile ----
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// Only 1 thread issues TMA (warp 5, lane 0)
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if (is_load_warp && lane == 0) {
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tma_load_2d((uint32_t)__cvta_generic_to_shared(sTmaBuf), (uint64_t)tma_k,
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mbar_addr, kt * MMA_K_BF16, 0);
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tma_mbarrier_arrive_expect_tx(mbar_addr, TMA_TILE_BYTES);
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}
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// ALL threads wait for TMA completion
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tma_mbarrier_wait(mbar_addr, phase); phase ^= 1;
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__syncthreads();
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// ---- Convert sTmaBuf (row-major) → sK0 (canonical) ----
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// All threads participate in the conversion
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for (int i = tid; i < TILE_SZ; i += 192) sK0[i] = 0;
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for (int i = tid; i < s_k * MMA_K_BF16; i += 192) {
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int r = i / MMA_K_BF16, c = i % MMA_K_BF16;
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int ck = c / 8, lc = c % 8, tmn = r / 8, lr = r % 8;
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sK0[ck * CORES_MN * 64 + tmn * 64 + lr * 8 + lc] = sTmaBuf[i];
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}
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__syncthreads();
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// ---- Warp 4: QK MMA ----
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if (is_mma_warp) {
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uint32_t idesc = make_idesc(128, 128);
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ0), 128);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK0), 128);
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if (tid == 128) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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}
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__syncthreads();
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}
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asm volatile("fence.sc.gpu;" ::: "memory");
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__syncthreads();
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// ==================================================================
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// SOFTMAX
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// ==================================================================
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float my_row_max = -INFINITY;
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if (my_warp_active) {
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// ================================================================
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// Softmax (warp 0, row 0 only for T=1 decode)
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// ================================================================
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if (wid == 0) {
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float s_vals[SK_TILE], row_max = -INFINITY;
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for (int n = 0; n < NUM_READS; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n * 8));
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: "r"(tb + n*8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (my_row_active) {
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for (int c = 0; c < 8; c++) {
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int col = n * 8 + c;
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if (col < s_k) my_row_max = fmaxf(my_row_max, tmp[c] * scale);
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}
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if (lane == 0) for (int c=0;c<8;c++) {
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s_vals[n*8+c] = tmp[c] * scale;
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row_max = fmaxf(row_max, tmp[c] * scale);
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}
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}
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}
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if (my_row_active) sRowMax[my_row] = my_row_max;
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__syncthreads();
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float my_p_vals[SK_TILE];
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float my_row_sum = 0.0f;
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if (my_warp_active) {
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float rm = my_row_active ? sRowMax[my_row] : 0.0f;
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for (int n = 0; n < NUM_READS; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
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: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
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"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
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: "r"(tb + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (my_row_active) {
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for (int c = 0; c < 8; c++) {
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int col = n * 8 + c;
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if (col < s_k) {
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float p = expf(tmp[c] * scale - rm);
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my_p_vals[col] = p;
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my_row_sum += p;
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}
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}
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}
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row_max = wmax(row_max);
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if (lane == 0) *sRowMax = row_max;
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float row_sum = 0.0f;
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if (lane == 0) for (int j=0;j<SK_TILE;j++) {
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s_vals[j] = expf(s_vals[j] - row_max);
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row_sum += s_vals[j];
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}
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row_sum = wsum(row_sum);
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if (lane == 0) *sRowSum = row_sum;
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if (lane == 0) for (int j=0;j<SK_TILE;j++) s_vals[j] /= row_sum;
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if (lane == 0) for (int j=0;j<SK_TILE;j++) s_p_vals[j] = s_vals[j];
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}
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if (my_row_active) sRowSum[my_row] = my_row_sum;
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__syncthreads();
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// ==================================================================
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// PV GEMM: N=16 sub-tiles
|
||||
// V canonical uses CORES_MN_V = 16/8 = 2 (NOT 16!)
|
||||
// V SMEM size = 16 * 16 BF16 = 256 (not 128*16 = 2048)
|
||||
// ==================================================================
|
||||
static constexpr int V_SUB_SZ = 16 * MMA_K_BF16; // (16, 16) canonical
|
||||
static constexpr int CORES_MN_V = 16 / 8; // 2
|
||||
// ================================================================
|
||||
// PV GEMM loop: N=16 sub-tiles × K-tiles
|
||||
// ================================================================
|
||||
for (int n = 0; n < N_NSUB; n++) {
|
||||
int d_base = n * 16;
|
||||
|
||||
for (int n_sub = 0; n_sub < N_NSUB; n_sub++) {
|
||||
int d_base = n_sub * 16;
|
||||
for (int pv_kt = 0; pv_kt < NKT_PV; pv_kt++) {
|
||||
const int col_start = pv_kt * MMA_K_BF16;
|
||||
|
||||
// Zero sPk
|
||||
for (int i = tid; i < TILE_SZ; i += 128) sPk[i] = 0;
|
||||
__syncthreads();
|
||||
|
||||
// Write P (only row 0 for T=1 decode, 16 elements)
|
||||
for (int c = tid; c < MMA_K_BF16; c += 128) {
|
||||
int ck = c / 8, lc = c % 8;
|
||||
sPk[ck * CORES_MN * 64 + 0 * 64 + 0 * 8 + lc] = f32_to_bf16(my_p_vals[col_start + c]);
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
// V sub-tile: direct load from GMEM (same as working test_fmha_gen)
|
||||
const bf16_t* __restrict__ v_head = (const bf16_t*)params.v;
|
||||
for (int i = tid; i < V_SUB_SZ; i += 128) sV[i] = 0;
|
||||
for (int dd = tid / 32; dd < 16; dd += 4) {
|
||||
for (int lr = lane; lr < MMA_K_BF16; lr += 32) {
|
||||
int r = col_start + lr;
|
||||
if (r < s_k) {
|
||||
int g_mn = dd / 8, g_k = lr / 8, llr = dd % 8, lc = lr % 8;
|
||||
sV[g_k * CORES_MN_V * 64 + g_mn * 64 + llr * 8 + lc] = v_head[(d_base + dd) * s_k + r];
|
||||
for (int kt = 0; kt < NKT_PV; kt++) {
|
||||
// ---- Warp 5: Fill sPk and load V sub-tile ----
|
||||
if (is_load_warp) {
|
||||
// Fill sPk from s_p_vals
|
||||
for (int i = lane; i < TILE_SZ; i += 32) sPk[i] = 0;
|
||||
if (lane < 16) {
|
||||
int c = lane;
|
||||
int ck = c / 8, lc = c % 8;
|
||||
sPk[ck * CORES_MN * 64 + 0 * 64 + 0 * 8 + lc] = f32_to_bf16(s_p_vals[kt * MMA_K_BF16 + c]);
|
||||
}
|
||||
// Load V sub-tile: direct from GMEM (same as working fmha_6warp)
|
||||
for (int i = lane; i < V_SUB_SZ; i += 32) sV[i] = 0;
|
||||
for (int dd = lane; dd < 16; dd += 32) {
|
||||
for (int lr = 0; lr < MMA_K_BF16; lr++) {
|
||||
int r = kt * MMA_K_BF16 + lr;
|
||||
int g_mn = dd / 8, g_k = lr / 8;
|
||||
int llr = dd % 8, lc = lr % 8;
|
||||
sV[g_k * 2 * 64 + g_mn * 64 + llr * 8 + lc] = v[(d_base + dd) * SK_TILE + r];
|
||||
}
|
||||
}
|
||||
}
|
||||
__syncthreads();
|
||||
|
||||
if (tid == 0) {
|
||||
uint32_t idesc_pv = make_idesc(128, 16);
|
||||
// ---- Warp 4: PV MMA ----
|
||||
if (is_mma_warp) {
|
||||
uint32_t idesc_pv16 = make_idesc(128, 16);
|
||||
uint64_t dp = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sPk), 128);
|
||||
uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV), 16);
|
||||
umma_ss_f16(tb + n_sub*16, dp, dv, idesc_pv, pv_kt > 0);
|
||||
if (tid == 128) umma_ss_f16(tb + n * 16, dp, dv, idesc_pv16, kt > 0);
|
||||
asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
|
||||
}
|
||||
__syncthreads();
|
||||
}
|
||||
}
|
||||
|
||||
asm volatile("fence.sc.gpu;" ::: "memory");
|
||||
__syncthreads();
|
||||
|
||||
// ==================================================================
|
||||
// EPILOGUE
|
||||
// ==================================================================
|
||||
if (my_warp_active) {
|
||||
float rm = my_row_active ? sRowMax[my_row] : 0.0f;
|
||||
float rs = my_row_active ? sRowSum[my_row] : 0.0f;
|
||||
float inv_rs = my_row_active ? (1.0f / rs) : 0.0f;
|
||||
|
||||
for (int n = 0; n < N_NSUB * 2; n++) {
|
||||
// ================================================================
|
||||
// Epilogue: TMEM → regs → normalize → BF16 → GMEM (warp 0)
|
||||
// ================================================================
|
||||
if (wid == 0) {
|
||||
float o_vals[HD];
|
||||
for (int n = 0; n < HD / 8; n++) {
|
||||
float tmp[8];
|
||||
asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];"
|
||||
: "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),
|
||||
"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7])
|
||||
: "r"(tb + n * 8));
|
||||
: "r"(tb + n*8));
|
||||
asm volatile("tcgen05.wait::ld.sync.aligned;");
|
||||
if (my_row_active) {
|
||||
for (int c = 0; c < 8; c++) {
|
||||
int d = n * 8 + c;
|
||||
if (d < HD) o_head[my_row * HD + d] = f32_to_bf16(tmp[c] * inv_rs);
|
||||
}
|
||||
}
|
||||
if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c];
|
||||
}
|
||||
if (my_row_active && lse_head) lse_head[my_row] = logf(rs) + rm;
|
||||
float row_sum = *sRowSum;
|
||||
float inv_rs = 1.0f / row_sum;
|
||||
if (lane == 0) for (int d=0;d<HD;d++) o[d] = f32_to_bf16(o_vals[d] * inv_rs);
|
||||
if (lane == 0 && lse) lse[0] = logf(row_sum) + *sRowMax;
|
||||
}
|
||||
__syncthreads();
|
||||
if (wid == 0) tmem_dealloc(tb, TMEM_N);
|
||||
|
||||
// TMEM dealloc (warp 4)
|
||||
if (is_mma_warp) {
|
||||
tmem_dealloc(tb, TMEM_N);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace dsv4::kernels::attention
|
||||
} // namespace
|
||||
|
||||
143
tests/unit/test_fmha_6warp_tma.cu
Normal file
143
tests/unit/test_fmha_6warp_tma.cu
Normal file
@@ -0,0 +1,143 @@
|
||||
/**
|
||||
* Test 6-warp TMA FMHA kernel for HD=64/128/256.
|
||||
* TMA loads K, direct loads Q and V.
|
||||
*/
|
||||
|
||||
#include <cuda_runtime.h>
|
||||
#include <cuda.h>
|
||||
#include <cstdio>
|
||||
#include <cmath>
|
||||
#include <cstdlib>
|
||||
#include <cstring>
|
||||
|
||||
#ifndef HD_VAL
|
||||
#define HD_VAL 64
|
||||
#endif
|
||||
|
||||
#include "dsv4/kernels/attention/fmha_common.cuh"
|
||||
#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
|
||||
#include "dsv4/kernels/attention/fmha_tma.cuh"
|
||||
|
||||
using namespace dsv4::kernels::attention;
|
||||
|
||||
static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
|
||||
static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
|
||||
|
||||
constexpr int HD = HD_VAL;
|
||||
constexpr int SK = 128;
|
||||
constexpr int MMA_K_BF16 = 16;
|
||||
constexpr int TILE_SZ = 128 * MMA_K_BF16;
|
||||
constexpr int V_SUB_SZ = 16 * MMA_K_BF16;
|
||||
constexpr int TMEM_N = (HD <= 128) ? 128 : 256;
|
||||
|
||||
#include "dsv4/kernels/attention/fmha_6warp_tma.cuh"
|
||||
|
||||
static size_t compute_smem() {
|
||||
size_t off = 0;
|
||||
off += 4; // sTmemBase
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += 16; // sMbar
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += TILE_SZ * sizeof(bf16_t); // sTmaBuf
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += TILE_SZ * sizeof(bf16_t); // sQ0
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += TILE_SZ * sizeof(bf16_t); // sK0
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += TILE_SZ * sizeof(bf16_t); // sPk
|
||||
off = (off + 127) & ~(size_t)127;
|
||||
off += V_SUB_SZ * sizeof(bf16_t); // sV
|
||||
off += 128 * sizeof(float); // sRowMax
|
||||
off += 128 * sizeof(float); // sRowSum
|
||||
off += SK * sizeof(float); // s_p_vals
|
||||
return off;
|
||||
}
|
||||
|
||||
int main() {
|
||||
printf("=== 6-warp TMA FMHA HD=%d ===\n", HD);
|
||||
const float SCALE = 1.0f / sqrtf((float)HD);
|
||||
|
||||
bf16_t* h_q = (bf16_t*)malloc(HD*sizeof(bf16_t));
|
||||
bf16_t* h_k = (bf16_t*)malloc(SK*HD*sizeof(bf16_t));
|
||||
bf16_t* h_v = (bf16_t*)malloc(HD*SK*sizeof(bf16_t));
|
||||
bf16_t* h_o = (bf16_t*)calloc(HD, sizeof(bf16_t));
|
||||
float* h_lse = (float*)calloc(1, sizeof(float));
|
||||
|
||||
srand(42);
|
||||
for (int d=0;d<HD;d++) h_q[d] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
|
||||
for (int i=0;i<SK*HD;i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
|
||||
for (int i=0;i<HD*SK;i++) h_v[i] = f32_to_bf16_host((float)(rand()%100)/100.0f-0.5f);
|
||||
|
||||
bf16_t *d_q,*d_k,*d_v,*d_o;
|
||||
float *d_lse;
|
||||
cudaMalloc(&d_q, HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_v, HD*SK*sizeof(bf16_t));
|
||||
cudaMalloc(&d_o, HD*sizeof(bf16_t));
|
||||
cudaMalloc(&d_lse, sizeof(float));
|
||||
cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
cudaMemcpy(d_v, h_v, HD*SK*sizeof(bf16_t), cudaMemcpyHostToDevice);
|
||||
|
||||
// TMA descriptor for K: (SK, HD) with tile (128, 16)
|
||||
CUtensorMap tma_k; CUtensorMap* d_tma_k;
|
||||
if (!create_tma_desc_2d_bf16(&tma_k, d_k, SK, HD, 128, 16)) {
|
||||
printf("TMA desc FAILED\n"); return 1;
|
||||
}
|
||||
cudaMalloc(&d_tma_k, sizeof(CUtensorMap));
|
||||
cudaMemcpy(d_tma_k, &tma_k, sizeof(CUtensorMap), cudaMemcpyHostToDevice);
|
||||
|
||||
// Compute reference
|
||||
float o_ref[HD];
|
||||
{
|
||||
float s[SK];
|
||||
for (int j=0;j<SK;j++) {
|
||||
float dot = 0.0f;
|
||||
for (int d=0;d<HD;d++) dot += bf16_to_f32_host(h_q[d]) * bf16_to_f32_host(h_k[j*HD+d]);
|
||||
s[j] = dot * SCALE;
|
||||
}
|
||||
float mx = -INFINITY;
|
||||
for (int j=0;j<SK;j++) mx = fmaxf(mx, s[j]);
|
||||
float sm = 0.0f;
|
||||
for (int j=0;j<SK;j++) { s[j] = expf(s[j]-mx); sm += s[j]; }
|
||||
for (int j=0;j<SK;j++) s[j] /= sm;
|
||||
for (int d=0;d<HD;d++) {
|
||||
float ov = 0.0f;
|
||||
for (int j=0;j<SK;j++) ov += s[j] * bf16_to_f32_host(h_v[d*SK+j]);
|
||||
o_ref[d] = ov;
|
||||
}
|
||||
}
|
||||
|
||||
size_t smem = compute_smem();
|
||||
printf("SMEM: %zu bytes (%.1f KB), 6 warps (192 threads), TMEM: %d cols\n", smem, smem/1024.0, TMEM_N);
|
||||
|
||||
if (smem > 48 * 1024) {
|
||||
cudaFuncSetAttribute(fmha_6warp_tma_kernel<HD>, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
|
||||
}
|
||||
fmha_6warp_tma_kernel<HD><<<1, 192, smem>>>(d_q, d_tma_k, d_v, d_o, d_lse, SK, SCALE);
|
||||
|
||||
cudaError_t launch_err = cudaGetLastError();
|
||||
if (launch_err != cudaSuccess) { printf("LAUNCH ERROR: %s\n", cudaGetErrorString(launch_err)); return 1; }
|
||||
|
||||
cudaError_t err = cudaDeviceSynchronize();
|
||||
if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
|
||||
|
||||
cudaMemcpy(h_o, d_o, HD*sizeof(bf16_t), cudaMemcpyDeviceToHost);
|
||||
cudaMemcpy(h_lse, d_lse, sizeof(float), cudaMemcpyDeviceToHost);
|
||||
|
||||
printf("O[0..7] MMA: "); for(int d=0;d<min(8,HD);d++) printf("%.6f ",bf16_to_f32_host(h_o[d])); printf("\n");
|
||||
printf("O[0..7] ref: "); for(int d=0;d<min(8,HD);d++) printf("%.6f ",o_ref[d]); printf("\n");
|
||||
|
||||
float cs=0,na=0,nb=0;
|
||||
for (int d=0;d<HD;d++) {
|
||||
float a=bf16_to_f32_host(h_o[d]),b=o_ref[d];
|
||||
if(fabsf(b)>1e-4f) { cs+=a*b; na+=a*a; nb+=b*b; }
|
||||
}
|
||||
cs /= (sqrtf(na)*sqrtf(nb)+1e-10f);
|
||||
printf("Filtered cosine: %.8f\n", cs);
|
||||
printf("Test %s\n", cs > 0.999f ? "PASSED" : "FAILED");
|
||||
|
||||
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v); cudaFree(d_o); cudaFree(d_lse); cudaFree(d_tma_k);
|
||||
free(h_q); free(h_k); free(h_v); free(h_o); free(h_lse);
|
||||
return cs > 0.999f ? 0 : 1;
|
||||
}
|
||||
Reference in New Issue
Block a user