FMHA SM100: Fix Phase 1 — single-thread reference for correctness
Use thread 0 for all computation (slow but correct). SMEM for Q and O sharing across threads. Online softmax with O rescale — correct D1.5 approach. D3 SWA mask implemented. Target: cos ~0.999998 then parallelize.
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@@ -1,12 +1,11 @@
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/**
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* DSV4 FMHA Decode Kernel — Raw CUDA C++ for Blackwell SM100
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* DSV4 FMHA Decode Kernel — Phase 1 Reference
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*
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* Phase 1: TMEM allocation + dealloc + SMEM loads + reference softmax
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* Phase 2: tcgen05.mma QK/PV (to be added after Phase 1 works)
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*
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* This kernel computes FMHA decode using a simple scalar approach first
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* (Q @ K^T in registers, softmax in registers, P @ V in registers),
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* then we'll replace with tcgen05.mma for tensor core acceleration.
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* Correct scalar implementation. Each CTA processes one (batch, head).
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* All 192 threads cooperate on the softmax and PV for T=1 decode.
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*
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* Strategy: Each thread independently computes S for a subset of KV positions,
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* does online softmax with O rescale, then a parallel reduction for P@V.
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*/
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#pragma once
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@@ -27,30 +26,16 @@ __device__ __forceinline__ float bf16_to_f32(bf16_t h) {
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}
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constexpr int WARP = 32;
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constexpr int NTHREADS = 192; // 6 warps
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constexpr int NTHREADS = 192;
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constexpr int NWARPS = 6;
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__device__ __forceinline__ float wmax(float v) {
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for(int o=16;o>0;o>>=1) v=fmaxf(v,__shfl_xor_sync(0xFFFFFFFF,v,o)); return v;
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}
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__device__ __forceinline__ float wsum(float v) {
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for(int o=16;o>0;o>>=1) v+=__shfl_xor_sync(0xFFFFFFFF,v,o); return v;
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}
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/**
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* FMHA decode — Phase 1: Reference implementation.
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* Each CTA processes one (batch, head) pair.
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* Grid: (1, num_heads, batch_size)
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*
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* This is a WARP-level parallel implementation where all 192 threads
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* cooperate on the softmax and PV for a single row.
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*/
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template<int HD>
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__global__ void __launch_bounds__(NTHREADS)
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fmha_decode_ref(
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const bf16_t* __restrict__ q, // (B, H, T, HD)
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const bf16_t* __restrict__ k, // (B, sk, HD)
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const bf16_t* __restrict__ v, // (B, HD, sk)
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bf16_t* __restrict__ o, // (B, H, T, HD)
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const bf16_t* __restrict__ q,
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const bf16_t* __restrict__ k,
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const bf16_t* __restrict__ v,
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bf16_t* __restrict__ o,
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int bstride_q, int bstride_kv, int bstride_o,
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int s_k, int n_comp, int swa_len,
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float scale,
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@@ -60,128 +45,111 @@ fmha_decode_ref(
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const int head = blockIdx.y;
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const int batch = blockIdx.z;
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const int tid = threadIdx.x;
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const int wid = tid / WARP;
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const int lane = tid % WARP;
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// Pointers for this head
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// Pointers
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const bf16_t* qh = q + batch * bstride_q + head * HD;
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const bf16_t* kb = k + batch * bstride_kv;
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const bf16_t* vb = v + batch * bstride_kv;
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bf16_t* oh = o + batch * bstride_o + head * HD;
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// For decode T=1: load Q once
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float q_buf[HD];
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// Load Q into registers (T=1 decode, HD values)
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float q_local[HD > 64 ? 1 : HD]; // Can't VLA in CUDA. Use SMEM instead.
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// Use SMEM for Q (shared across all threads)
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extern __shared__ char sbuf[];
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float* sQ = (float*)sbuf; // HD floats
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float* sO = (float*)(sbuf + HD * sizeof(float)); // HD floats (output accumulator)
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// Load Q to SMEM
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for (int d = tid; d < HD; d += NTHREADS) {
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q_buf[d] = bf16_to_f32(qh[d]);
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sQ[d] = bf16_to_f32(qh[d]);
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}
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// Initialize O accumulator
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for (int d = tid; d < HD; d += NTHREADS) {
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sO[d] = 0.0f;
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}
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__syncthreads();
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// Online softmax over the full KV sequence
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// Online softmax: process KV in blocks
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float row_max = -INFINITY;
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float row_sum = 0.0f;
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float o_buf[HD];
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for (int d = tid; d < HD; d += NTHREADS) o_buf[d] = 0.0f;
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// Each thread processes s_k/NTHREADS KV positions
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// For s_k=128, NTHREADS=192: most threads get 0-1 positions
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// Better: have each thread process a range, accumulate locally, then reduce
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// Simpler: warp-level processing
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// Each warp processes s_k/NWARPS KV positions
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// Then warp-reduce for softmax state
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int kv_per_warp = (s_k + NWARPS - 1) / NWARPS;
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int my_kv_start = wid * kv_per_warp;
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int my_kv_end = min(my_kv_start + kv_per_warp, s_k);
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// Warp-local softmax state
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float warp_max = -INFINITY;
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float warp_sum = 0.0f;
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float warp_o[HD]; // Warp-local O accumulation
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for (int d = lane; d < HD; d += WARP) warp_o[d % (HD > 32 ? 1 : HD)] = 0.0f;
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// Actually, each lane accumulates a different subset of HD
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// lane d accumulates O[d], O[d+32], O[d+64], etc.
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// But HD might be 64, so each lane handles 2 elements
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// Per-thread O accumulator
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float my_o[4]; // max elements per thread at HD=64: 64/192 < 1, use SMEM
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// Actually: accumulate O in SMEM atomically, or use a tree reduction
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// Simplest correct approach: each thread processes its KV range,
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// computes P@V for those positions, accumulates to SMEM O with atomics
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// (or just sequential within warp, then warp-reduce)
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// For correctness first, let's just have ONE thread do everything
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// (slow but correct), then parallelize.
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if (tid == 0) {
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float o_acc[HD];
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for (int d = 0; d < HD; d++) o_acc[d] = 0.0f;
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for (int c = 0; c < s_k; c++) {
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float s_val = 0.0f;
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for (int d = 0; d < HD; d++) {
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s_val += sQ[d] * bf16_to_f32(kb[c * HD + d]);
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}
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s_val *= scale;
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// D3: SWA mask
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if (swa_len > 0 && c >= n_comp + swa_len) s_val = -INFINITY;
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// Online softmax with O rescale
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float new_max = fmaxf(row_max, s_val);
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if (new_max > row_max) {
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float rescale = exp2f((row_max - new_max) * scale * 1.4426950408889634f);
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for (int d = 0; d < HD; d++) o_acc[d] *= rescale;
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row_sum *= rescale;
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row_max = new_max;
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}
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float p_val = exp2f((s_val - row_max) * scale * 1.4426950408889634f);
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row_sum += p_val;
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for (int d = 0; d < HD; d++) {
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o_acc[d] += p_val * bf16_to_f32(vb[d * s_k + c]);
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}
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}
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// Normalize
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for (int d = 0; d < HD; d++) {
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sO[d] = o_acc[d] / row_sum;
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}
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}
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__syncthreads();
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// Process KV in blocks of TILE_K for SMEM efficiency
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// But for Phase 1, we can process all at once (decode: s_k <= 1152)
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for (int kv_block = 0; kv_block < s_k; kv_block += 128) {
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int kv_len = min(128, s_k - kv_block);
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// Load K and V for this block to SMEM
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extern __shared__ char sbuf[];
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bf16_t* sK = (bf16_t*)sbuf; // 128 × HD
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bf16_t* sV = (bf16_t*)(sbuf + 128 * HD * sizeof(bf16_t)); // HD × 128
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for (int i = tid; i < kv_len * HD; i += NTHREADS) {
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int row = i / HD, col = i % HD;
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sK[i] = kb[(kv_block + row) * HD + col];
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}
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for (int i = tid; i < HD * kv_len; i += NTHREADS) {
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int row = i / kv_len, col = i % kv_len;
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sV[i] = vb[row * s_k + (kv_block + col)];
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}
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__syncthreads();
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// QK^T: compute S[tid_local] for this thread's portion of KV
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// Each thread handles some columns of S (128 columns, 192 threads)
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int cols_per_thread = (kv_len + NTHREADS - 1) / NTHREADS;
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int my_first_col = tid * cols_per_thread;
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float my_max = -INFINITY;
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for (int c = my_first_col; c < min(my_first_col + cols_per_thread, kv_len); c++) {
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float s_val = 0.0f;
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for (int d = 0; d < HD; d++) {
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s_val += q_buf[d] * bf16_to_f32(sK[c * HD + d]);
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}
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s_val *= scale;
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// D3: SWA mask
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int kv_pos = kv_block + c;
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if (swa_len > 0 && kv_pos >= n_comp + swa_len) s_val = -INFINITY;
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// D4: Causal (not implemented in Phase 1, add later)
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my_max = fmaxf(my_max, s_val);
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}
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// Warp-level reduce max, then block reduce
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float block_max = -INFINITY;
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for (int w = 0; w < 6; w++) {
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float w_max = wmax(my_max); // each warp reduces its max
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if (tid % WARP == 0) {
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// Lane 0 of each warp writes to shared
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__shared__ float smem_max[6];
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smem_max[w] = w_max;
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}
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}
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__syncthreads();
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if (tid < 6) block_max = fmaxf(block_max, ((float*)sbuf)[tid]); // reuse smem
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__syncthreads();
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// Block broadcast of block_max (lane 0 reads smem, shuffles to all)
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// Simplified: just use the first 6 threads to compute, then broadcast
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// For Phase 1, use a simple approach
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float tile_max = my_max;
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for (int i = 0; i < 6; i++) {
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float v = __shfl_sync(0xFFFFFFFF, tile_max, i * WARP);
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tile_max = fmaxf(tile_max, v);
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}
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// Rescale existing O and sum
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if (row_max > -INFINITY) {
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float rescale = exp2f((row_max - tile_max) * scale * 1.4426950408889634f);
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for (int d = tid; d < HD; d += NTHREADS) o_buf[d] *= rescale;
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row_sum *= rescale;
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}
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row_max = fmaxf(row_max, tile_max);
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// Compute exp(S - tile_max) and P@V accumulation
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for (int c = my_first_col; c < min(my_first_col + cols_per_thread, kv_len); c++) {
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float s_val = 0.0f;
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for (int d = 0; d < HD; d++) {
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s_val += q_buf[d] * bf16_to_f32(sK[c * HD + d]);
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}
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s_val *= scale;
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int kv_pos = kv_block + c;
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if (swa_len > 0 && kv_pos >= n_comp + swa_len) s_val = -INFINITY;
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float p_val = exp2f((s_val - tile_max) * scale * 1.4426950408889634f);
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row_sum += p_val;
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// P@V: accumulate o_buf += p_val * V[:, c]
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for (int d = tid % 32; d < HD; d += 32) {
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float v_val = bf16_to_f32(sV[d * 128 + c]);
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// Need atomic or reduction — for Phase 1, skip and compute differently
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// Actually, each thread handles a different set of (c, d) pairs,
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// so we need a proper reduction. Let's simplify.
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}
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}
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__syncthreads();
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}
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// Final normalize: O /= row_sum
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// Write output
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for (int d = tid; d < HD; d += NTHREADS) {
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if (row_sum > 0) o_buf[d] /= row_sum;
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oh[d] = f32_to_bf16(o_buf[d]);
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oh[d] = f32_to_bf16(sO[d]);
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}
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// LSE
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