test: FMHA softmax (QK→read S→softmax→write P→read P→verify)
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tests/unit/test_fmha_softmax.cu
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214
tests/unit/test_fmha_softmax.cu
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/**
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* UMMA FMHA Softmax Test — HD=64, SK=128
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* Validates: QK GEMM → read S → softmax → write P → read P
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* PV GEMM deferred to next test.
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*/
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#include <cuda_runtime.h>
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#include <cstdio>
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#include <cmath>
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#include <cstdlib>
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#include <cstring>
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#include "dsv4/kernels/attention/fmha_common.cuh"
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#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
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using namespace dsv4::kernels::attention;
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static bf16_t f32_to_bf16_host(float f) { uint32_t u; memcpy(&u,&f,4); return (uint16_t)(u>>16); }
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static float bf16_to_f32_host(bf16_t h) { uint32_t u=(uint32_t)h<<16; float f; memcpy(&f,&u,4); return f; }
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constexpr int HD = 64, SK = 128, NKT = HD / MMA_K_BF16;
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constexpr int BLOCK_MN = 128, TILE_SZ = BLOCK_MN * MMA_K_BF16, CORES_MN = BLOCK_MN / 8;
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__global__ void __launch_bounds__(128)
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test_softmax(const bf16_t* q, const bf16_t* k, bf16_t* p_out, float* p_scalar, float scale)
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{
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const int tid = threadIdx.x, wid = tid / 32, lane = tid % 32;
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extern __shared__ char sbuf[];
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uint32_t* sTmemBase = (uint32_t*)sbuf;
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bf16_t* sQ0 = (bf16_t*)(((uintptr_t)(sbuf + 4) + 15) & ~(uintptr_t)15);
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bf16_t* sK0 = sQ0 + NKT * TILE_SZ;
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// Load Q and K (same as working QK test)
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for (int i = tid; i < NKT * TILE_SZ; i += 128) { sQ0[i] = 0; sK0[i] = 0; }
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for (int kt = 0; kt < NKT; kt++) {
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bf16_t* sq = sQ0 + kt * TILE_SZ;
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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sq[ck * CORES_MN * 64 + lc] = q[kt * MMA_K_BF16 + d];
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}
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bf16_t* sk = sK0 + kt * TILE_SZ;
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for (int r = 0; r < SK; r++) {
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for (int d = tid; d < MMA_K_BF16; d += 128) {
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int ck = d / 8, lc = d % 8;
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int tmn = r / 8, lr = r % 8;
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sk[ck * CORES_MN * 64 + tmn * 64 + lr * 8 + lc] = k[r * HD + kt * MMA_K_BF16 + d];
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}
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}
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}
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__syncthreads();
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// TMEM alloc
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if (wid == 1) tmem_alloc(__cvta_generic_to_shared(sTmemBase), 128);
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__syncthreads();
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uint32_t tb = *sTmemBase;
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// QK GEMM
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bf16_t* sQ_arr[4] = {sQ0, sQ0+TILE_SZ, sQ0+2*TILE_SZ, sQ0+3*TILE_SZ};
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bf16_t* sK_arr[4] = {sK0, sK0+TILE_SZ, sK0+2*TILE_SZ, sK0+3*TILE_SZ};
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uint32_t idesc = make_idesc(BLOCK_MN, BLOCK_MN);
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for (int kt = 0; kt < NKT; kt++) {
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uint64_t dq = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sQ_arr[kt]), BLOCK_MN);
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uint64_t dk = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sK_arr[kt]), BLOCK_MN);
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if (tid == 0) umma_ss_f16(tb, dq, dk, idesc, kt > 0);
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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}
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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// ================================================================
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// SOFTMAX: Read row 0 of S, compute softmax, write P back to TMEM
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// ================================================================
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if (wid == 0) {
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float s_vals[SK];
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float row_max = -INFINITY;
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// Read S row 0 from TMEM using 32x32b.x8
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for (int n = 0; n < SK / 8; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) {
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for (int c = 0; c < 8; c++) {
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// S is UNSCALED raw dot product; apply scale
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s_vals[n * 8 + c] = tmp[c] * scale;
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row_max = fmaxf(row_max, tmp[c] * scale);
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}
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}
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}
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row_max = wmax(row_max);
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// exp(S - max) and sum
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float row_sum = 0.0f;
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if (lane == 0) {
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for (int j = 0; j < SK; j++) {
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s_vals[j] = expf(s_vals[j] - row_max);
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row_sum += s_vals[j];
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}
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}
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row_sum = wsum(row_sum);
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// Normalize
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if (lane == 0) {
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for (int j = 0; j < SK; j++) s_vals[j] /= row_sum;
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}
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// Write P back to TMEM using 32x32b.x8 stores
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// P is (128, 128) with only row 0 non-zero.
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// 32x32b.x8: 32 rows × 8 columns. Lane 0 writes row 0, lanes 1-31 write 0.
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for (int n = 0; n < SK / 8; n++) {
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float p0 = (lane == 0) ? s_vals[n*8+0] : 0;
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float p1 = (lane == 0) ? s_vals[n*8+1] : 0;
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float p2 = (lane == 0) ? s_vals[n*8+2] : 0;
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float p3 = (lane == 0) ? s_vals[n*8+3] : 0;
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float p4 = (lane == 0) ? s_vals[n*8+4] : 0;
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float p5 = (lane == 0) ? s_vals[n*8+5] : 0;
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float p6 = (lane == 0) ? s_vals[n*8+6] : 0;
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float p7 = (lane == 0) ? s_vals[n*8+7] : 0;
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asm volatile("tcgen05.st.sync.aligned.32x32b.x8.b32 [%0],{%1,%2,%3,%4,%5,%6,%7,%8};" :: "r"(tb + n*8), "f"(p0), "f"(p1), "f"(p2), "f"(p3), "f"(p4), "f"(p5), "f"(p6), "f"(p7));
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}
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tmem_fence_store();
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}
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__syncthreads();
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// Read P back from TMEM to verify
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if (wid == 0) {
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float p_vals[SK];
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for (int n = 0; n < SK / 8; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb + n * 8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) {
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for (int c = 0; c < 8; c++) p_vals[n * 8 + c] = tmp[c];
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}
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}
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if (lane == 0) {
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for (int j = 0; j < SK; j++) p_out[j] = f32_to_bf16(p_vals[j]);
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}
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}
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__syncthreads();
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// Scalar softmax reference
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if (tid == 0) {
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float s[SK];
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for (int j = 0; j < SK; j++) {
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float dot = 0.0f;
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for (int d = 0; d < HD; d++)
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dot += bf16_to_f32(q[d]) * bf16_to_f32(k[j * HD + d]);
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s[j] = dot * scale;
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}
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float mx = -INFINITY;
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for (int j = 0; j < SK; j++) mx = fmaxf(mx, s[j]);
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float sm = 0.0f;
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for (int j = 0; j < SK; j++) { s[j] = expf(s[j] - mx); sm += s[j]; }
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for (int j = 0; j < SK; j++) p_scalar[j] = s[j] / sm;
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}
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if (wid == 0) tmem_dealloc(tb, 128);
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}
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int main() {
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printf("=== UMMA FMHA Softmax HD=64 ===\n");
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const float SCALE = 1.0f / sqrtf((float)HD);
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bf16_t* h_q = (bf16_t*)malloc(HD * sizeof(bf16_t));
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bf16_t* h_k = (bf16_t*)malloc(SK * HD * sizeof(bf16_t));
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bf16_t* h_p = (bf16_t*)calloc(SK, sizeof(bf16_t));
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float* h_p_scalar = (float*)calloc(SK, sizeof(float));
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srand(42);
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for (int d = 0; d < HD; d++) h_q[d] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
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for (int i = 0; i < SK*HD; i++) h_k[i] = f32_to_bf16_host((float)(rand()%100)/100.0f - 0.5f);
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bf16_t *d_q, *d_k, *d_p; float *d_p_scalar;
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cudaMalloc(&d_q, HD*sizeof(bf16_t));
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cudaMalloc(&d_k, SK*HD*sizeof(bf16_t));
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cudaMalloc(&d_p, SK*sizeof(bf16_t));
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cudaMalloc(&d_p_scalar, SK*sizeof(float));
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cudaMemcpy(d_q, h_q, HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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cudaMemcpy(d_k, h_k, SK*HD*sizeof(bf16_t), cudaMemcpyHostToDevice);
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int smem = (4 + 16 + 2*NKT*TILE_SZ*sizeof(bf16_t) + 256 + 127) & ~127;
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test_softmax<<<1, 128, smem>>>(d_q, d_k, d_p, d_p_scalar, SCALE);
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cudaError_t err = cudaDeviceSynchronize();
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if (err != cudaSuccess) { printf("CUDA ERROR: %s\n", cudaGetErrorString(err)); return 1; }
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cudaMemcpy(h_p, d_p, SK*sizeof(bf16_t), cudaMemcpyDeviceToHost);
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cudaMemcpy(h_p_scalar, d_p_scalar, SK*sizeof(float), cudaMemcpyDeviceToHost);
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printf("P[0,0..7] MMA: "); for(int j=0;j<8;j++) printf("%.6f ",bf16_to_f32_host(h_p[j])); printf("\n");
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printf("P[0,0..7] ref: "); for(int j=0;j<8;j++) printf("%.6f ",h_p_scalar[j]); printf("\n");
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printf("P[0,64..71] MMA: "); for(int j=64;j<72;j++) printf("%.6f ",bf16_to_f32_host(h_p[j])); printf("\n");
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printf("P[0,64..71] ref: "); for(int j=64;j<72;j++) printf("%.6f ",h_p_scalar[j]); printf("\n");
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float max_diff = 0.0f, max_val = 0.0f;
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for (int j = 0; j < SK; j++) {
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float diff = fabsf(bf16_to_f32_host(h_p[j]) - h_p_scalar[j]);
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max_diff = fmaxf(max_diff, diff);
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max_val = fmaxf(max_val, fabsf(h_p_scalar[j]));
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}
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float rel_err = max_val > 0 ? max_diff / max_val : max_diff;
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// Also check sum ≈ 1.0
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float p_sum = 0.0f;
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for (int j = 0; j < SK; j++) p_sum += bf16_to_f32_host(h_p[j]);
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printf("Row 0 max rel err: %.8f | sum: %.6f\n", rel_err, p_sum);
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printf("Test %s\n", (rel_err < 0.01f && fabsf(p_sum - 1.0f) < 0.01f) ? "PASSED" : "FAILED");
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cudaFree(d_q); cudaFree(d_k); cudaFree(d_p); cudaFree(d_p_scalar);
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free(h_q); free(h_k); free(h_p); free(h_p_scalar);
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return (rel_err < 0.01f && fabsf(p_sum - 1.0f) < 0.01f) ? 0 : 1;
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}
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