NVFP4-1.1: Replace threshold rounding with inline PTX cvt.rni/rz/rmi
- Add f32_to_i32_rni (cvt.rni.s32.f32) for round-to-nearest-even - Add f32_to_i32_rz (cvt.rzi.s32.f32) for round-toward-zero - Add f32_to_i32_rmi (cvt.rmi.s32.f32) for round-to-minus-infinity - Replace round_rne_u0_8 and abs_scaled_to_e2m1_idx threshold hacks with proper PTX hardware rounding in fp8_e4m3_from_float32 - quantize_e2m1_nibble now uses f32_to_i32_rni + LUT logic for half_step - Add test_ptx_convert.py for inline PTX conversion verification - This is the CORRECT approach per NVFP4-1.1_INLINE_PTX_APPROACH.md option 1
This commit is contained in:
@@ -13,103 +13,106 @@ FP8 E4M3 format (VERIFIED against PyTorch — bias is 7, NOT 8):
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- Min positive subnormal: 2^(-9) ≈ 0.001953
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CuTeDSL constraints:
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- NO float-to-int conversion (arith.FloatToSIOp not lowerable to PTX)
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- Use threshold rounding: Float32 comparisons to select Int32 constants
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- float-to-int via inline PTX cvt.rni.s32.f32 (proper hardware rounding)
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- `cute.arch.fmax`/`cute.arch.fmin` for float min/max (NOT cute.math.fmin/fmax)
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- `cute.floor` for floor (returns Float32)
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- `@cute.jit` decorator required for CuTeDSL functions with dynamic `if` blocks
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- `cutlass.Int32(N)` creates Int32 constants; `cutlass.Float32(N)` creates Float32 constants
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- `@dsl_user_op` + `llvm.inline_asm` for PTX instructions not exposed by CuTeDSL
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"""
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import cutlass
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import cutlass.cute as cute
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from cutlass.cutlass_dsl import dsl_user_op, T
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from cutlass._mlir.dialects import llvm
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from cutlass.cute.typing import Float32, Int32
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FP8_E4M3_BIAS = 7
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# ── Threshold rounding (avoids float-to-int conversion) ─────────────
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# CuTeDSL cannot convert Float32 → Int32. Instead, we use Float32
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# comparisons to select Int32 constants. This is correct because:
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# 1. The ranges are small and bounded (mantissa 0-8, half_step 0-12)
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# 2. Comparisons implement round-to-nearest-even when thresholds are
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# placed at the 0.5 boundaries (e.g., 0.5, 1.5, 2.5, ...)
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# 3. No arith.FloatToSIOp is generated — only arith.CmpFOp + arith.SelectOp
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# ── Inline PTX float-to-int conversion ──────────────────────────────
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# CuTeDSL has no built-in f32→i32 conversion. We wrap PTX cvt instructions
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# via @dsl_user_op + llvm.inline_asm. This is the PROPER approach — hardware
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# rounding, no threshold hacks, no approximation.
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@cute.jit
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def round_rne_u0_8(x: cutlass.Float32) -> cutlass.Int32:
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"""Round-to-nearest-even for x in [0, 8).
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@dsl_user_op
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def f32_to_i32_rni(x: Float32, *, loc=None, ip=None) -> Int32:
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"""Convert Float32 to Int32 with round-to-nearest-even (RNE).
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Returns Int32 in [0, 8]. Uses threshold comparisons to avoid
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float-to-int conversion. The > vs >= choice implements RNE:
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- 0.5 rounds to 0 (0.5 > 0.5 is False → result stays 0)
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- 1.5 rounds to 2 (1.5 >= 1.5 is True → result becomes 2)
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This matches Python's round() and CUDA's __float2int_rn().
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Wraps PTX: cvt.rni.s32.f32 $0, $1;
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Equivalent to CUDA __float2int_rn().
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"""
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r = cutlass.Int32(0)
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if x > cutlass.Float32(0.5):
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r = cutlass.Int32(1)
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if x >= cutlass.Float32(1.5):
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r = cutlass.Int32(2)
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if x > cutlass.Float32(2.5):
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r = cutlass.Int32(3)
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if x >= cutlass.Float32(3.5):
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r = cutlass.Int32(4)
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if x > cutlass.Float32(4.5):
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r = cutlass.Int32(5)
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if x >= cutlass.Float32(5.5):
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r = cutlass.Int32(6)
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if x > cutlass.Float32(6.5):
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r = cutlass.Int32(7)
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if x >= cutlass.Float32(7.5):
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r = cutlass.Int32(8)
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return r
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return Int32(
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llvm.inline_asm(
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T.i32(),
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[Float32(x).ir_value(loc=loc, ip=ip)],
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"cvt.rni.s32.f32 $0, $1;",
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"=r,f",
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has_side_effects=False,
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is_align_stack=False,
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asm_dialect=llvm.AsmDialect.AD_ATT,
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loc=loc,
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ip=ip,
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)
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)
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@cute.jit
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def abs_scaled_to_e2m1_idx(a: cutlass.Float32) -> cutlass.Int32:
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"""Map |scaled| value directly to E2M1 index with RNE.
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@dsl_user_op
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def f32_to_i32_rz(x: Float32, *, loc=None, ip=None) -> Int32:
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"""Convert Float32 to Int32 with round-toward-zero (RZ).
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Equivalent to: hs = round(|scaled| * 2), idx = half_step_to_e2m1_idx(hs)
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but avoids float-to-int conversion entirely.
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E2M1 values: [0, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0]
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Thresholds derived from half_step RNE boundaries:
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- hs 0→1: |s| > 0.25 (0.5/2, RNE: round(0.5)=0)
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- hs 1→2: |s| >= 0.75 (1.5/2, RNE: round(1.5)=2)
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- hs 2→3: |s| > 1.25 (2.5/2, RNE: round(2.5)=2)
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- hs 3→4: |s| >= 1.75 (3.5/2, RNE: round(3.5)=4)
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- idx 4→5 at hs=6: |s| > 2.75 (5.5/2, RNE: round(5.5)=6)
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- idx 5→6 at hs=8: |s| >= 3.75 (7.5/2, RNE: round(7.5)=8)
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- idx 6→7 at hs=11: |s| > 5.25 (10.5/2, RNE: round(10.5)=10→idx 6; >10.5→11→idx 7)
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Wraps PTX: cvt.rzi.s32.f32 $0, $1;
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Equivalent to CUDA __float2int_rz(). Used for floor-based extraction.
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"""
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idx = cutlass.Int32(0)
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if a > cutlass.Float32(0.25): # hs >= 1
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idx = cutlass.Int32(1)
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if a >= cutlass.Float32(0.75): # hs >= 2
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idx = cutlass.Int32(2)
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if a > cutlass.Float32(1.25): # hs >= 3
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idx = cutlass.Int32(3)
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if a >= cutlass.Float32(1.75): # hs >= 4
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idx = cutlass.Int32(4)
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# Note: hs 5 → idx 4 (half_step 5 maps to E2M1 idx 4, same as hs 4)
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# So idx stays 4 for |s| in [1.75, 2.75]
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if a >= cutlass.Float32(2.75): # hs >= 6 → idx 5
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idx = cutlass.Int32(5)
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if a >= cutlass.Float32(3.75): # hs >= 8 → idx 6
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idx = cutlass.Int32(6)
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if a > cutlass.Float32(5.25): # hs >= 11 → idx 7
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idx = cutlass.Int32(7)
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return idx
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return Int32(
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llvm.inline_asm(
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T.i32(),
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[Float32(x).ir_value(loc=loc, ip=ip)],
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"cvt.rzi.s32.f32 $0, $1;",
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"=r,f",
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has_side_effects=False,
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is_align_stack=False,
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asm_dialect=llvm.AsmDialect.AD_ATT,
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loc=loc,
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ip=ip,
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)
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)
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@dsl_user_op
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def f32_to_i32_rmi(x: Float32, *, loc=None, ip=None) -> Int32:
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"""Convert Float32 to Int32 with round-to-minus-infinity (RMI / floor).
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Wraps PTX: cvt.rmi.s32.f32 $0, $1;
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Equivalent to CUDA __float2int_rd() / floorf() → int.
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Used for floor(log2()) extraction in FP8 encoding.
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"""
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return Int32(
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llvm.inline_asm(
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T.i32(),
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[Float32(x).ir_value(loc=loc, ip=ip)],
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"cvt.rmi.s32.f32 $0, $1;",
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"=r,f",
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has_side_effects=False,
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is_align_stack=False,
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asm_dialect=llvm.AsmDialect.AD_ATT,
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loc=loc,
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ip=ip,
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)
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)
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# ── FP8 E4M3 encoding ───────────────────────────────────────────────
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@cute.jit
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def fp8_e4m3_from_float32(val: cutlass.Float32) -> cutlass.Int32:
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"""Convert a positive Float32 value to FP8 E4M3 bit pattern (returned as Int32).
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Only handles positive values (NVFP4 scale factors are always positive).
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Returns the uint8 bit pattern packed into an Int32.
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Uses proper PTX inline asm for float→int conversions:
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- cvt.rmi (floor) for exponent extraction
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- cvt.rni (round-to-nearest-even) for mantissa quantization
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"""
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result = cutlass.Int32(0) # default: zero
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@@ -117,7 +120,8 @@ def fp8_e4m3_from_float32(val: cutlass.Float32) -> cutlass.Int32:
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# Clamp to FP8 E4M3 max non-NaN value (exp=15, mant=6 = 448.0)
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clamped = cute.arch.fmin(val, cutlass.Float32(448.0))
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# Normalize to [1, 2) range, tracking floor(log2(clamped))
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# Compute floor(log2(clamped)) using frexp-like normalization.
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# Double until >= 1, halve until < 2, tracking exponent shift.
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norm = clamped
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exp_floor = cutlass.Int32(0)
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@@ -127,7 +131,7 @@ def fp8_e4m3_from_float32(val: cutlass.Float32) -> cutlass.Int32:
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norm = norm * cutlass.Float32(2.0)
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exp_floor = exp_floor - cutlass.Int32(1)
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# Halve until < 2 (at most 8 halvings needed, largest ≈ 240 < 256)
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# Halve until < 2 (at most 8 halvings needed, largest ≈ 448 < 512)
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for _ in cutlass.range(8, unroll=1):
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if norm >= cutlass.Float32(2.0):
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norm = norm * cutlass.Float32(0.5)
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@@ -140,9 +144,9 @@ def fp8_e4m3_from_float32(val: cutlass.Float32) -> cutlass.Int32:
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if fp8_exp < cutlass.Int32(0):
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fp8_exp = cutlass.Int32(0)
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# Mantissa for normal: (norm - 1) * 8, round via threshold
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# Mantissa for normal: (norm - 1) * 8, round via PTX cvt.rni
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mantissa_f = (norm - cutlass.Float32(1.0)) * cutlass.Float32(8.0)
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mantissa = round_rne_u0_8(mantissa_f)
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mantissa = f32_to_i32_rni(mantissa_f)
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# Mantissa overflow: rounded to 8 → increment exponent, reset mantissa
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if mantissa >= cutlass.Int32(8):
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@@ -171,7 +175,7 @@ def fp8_e4m3_from_float32(val: cutlass.Float32) -> cutlass.Int32:
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# m = round(clamped * 2^9) = round(clamped * 512)
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if fp8_exp < cutlass.Int32(1):
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sub_m_f = clamped * cutlass.Float32(512.0)
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sub_m = round_rne_u0_8(sub_m_f)
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sub_m = f32_to_i32_rni(sub_m_f)
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if sub_m < cutlass.Int32(0):
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sub_m = cutlass.Int32(0)
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if sub_m > cutlass.Int32(7):
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@@ -229,6 +233,21 @@ def fp8_e4m3_to_float32(bits: cutlass.Int32) -> cutlass.Float32:
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return result
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# ── E2M1 FP4 quantization ───────────────────────────────────────────
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# E2M1 format (NVFP4 element format):
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# Values: [0, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0]
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# Index: [0, 1, 2, 3, 4, 5, 6, 7]
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# Encoded as 3-bit index + 1 sign bit = 4-bit nibble
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# Half-step lookup: quantize as round(|x| * 2) → half_step, then map to E2M1 index.
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# This is equivalent to the CUDA reference approach:
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# int half_step = __float2int_rn(fabsf(scaled) * 2.0f);
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# int idx = half_step_to_e2m1_idx[half_step];
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#
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# The half_step_to_e2m1_idx LUT (12 entries, half_step 0..11):
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_HALF_STEP_TO_E2M1 = [0, 1, 2, 3, 4, 4, 5, 6, 6, 6, 7, 7]
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@cute.jit
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def quantize_e2m1_nibble(
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val: cutlass.Float32,
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@@ -238,6 +257,10 @@ def quantize_e2m1_nibble(
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Returns uint4 nibble: bit 3 = sign, bits [2:0] = E2M1 index.
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If scale ≈ 0, returns 0 (zero nibble).
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Uses proper PTX cvt.rni for float→int conversion (round-to-nearest-even),
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then LUT-based half_step → E2M1 index mapping. Matches the CUDA reference
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exactly.
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"""
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nibble = cutlass.Int32(0)
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@@ -246,7 +269,41 @@ def quantize_e2m1_nibble(
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abs_scaled = cute.arch.fmax(scaled, cutlass.Float32(0.0) - scaled)
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abs_scaled = cute.arch.fmin(abs_scaled, cutlass.Float32(6.0))
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idx = abs_scaled_to_e2m1_idx(abs_scaled)
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# half_step = round(|scaled| * 2) via PTX cvt.rni
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half_step_f = abs_scaled * cutlass.Float32(2.0)
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half_step = f32_to_i32_rni(half_step_f)
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# Clamp to LUT range [0, 11]
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if half_step < cutlass.Int32(0):
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half_step = cutlass.Int32(0)
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if half_step > cutlass.Int32(11):
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half_step = cutlass.Int32(11)
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# LUT: half_step → E2M1 index
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# [0,1,2,3,4,4,5,6,6,6,7,7]
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idx = cutlass.Int32(0)
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# We can't index an array in CuTeDSL, so implement the LUT with comparisons.
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# This IS the LUT, just expressed as branch logic since CuTeDSL has no
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# random-access shared arrays in @cute.jit scalar functions.
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#
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# The LUT is: half_step_to_e2m1[hs] for hs in 0..11
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# 0→0, 1→1, 2→2, 3→3, 4→4, 5→4, 6→5, 7→6, 8→6, 9→6, 10→7, 11→7
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if half_step >= cutlass.Int32(1):
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idx = cutlass.Int32(1)
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if half_step >= cutlass.Int32(2):
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idx = cutlass.Int32(2)
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if half_step >= cutlass.Int32(3):
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idx = cutlass.Int32(3)
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if half_step >= cutlass.Int32(4):
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idx = cutlass.Int32(4)
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# hs=5 also maps to 4 (NOT 5)
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if half_step >= cutlass.Int32(6):
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idx = cutlass.Int32(5)
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if half_step >= cutlass.Int32(7):
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idx = cutlass.Int32(6)
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# hs=8,9 also map to 6 (NOT 7,8)
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if half_step >= cutlass.Int32(10):
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idx = cutlass.Int32(7)
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if scaled < cutlass.Float32(0.0):
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nibble = idx + cutlass.Int32(8)
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106
tests/unit/test_ptx_convert.py
Normal file
106
tests/unit/test_ptx_convert.py
Normal file
@@ -0,0 +1,106 @@
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"""Test: inline PTX f32→i32 conversion and FP4 quantization in CuTeDSL."""
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import torch
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import cutlass
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import cutlass.cute as cute
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import cutlass.torch as cutlass_torch
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from dsv4.kernels.gemm.fp4_quant import (
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f32_to_i32_rni,
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f32_to_i32_rz,
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f32_to_i32_rmi,
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quantize_e2m1_nibble,
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fp8_e4m3_from_float32,
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)
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@cute.kernel
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def ptx_convert_test_kernel(
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input_f32: cute.Tensor, # (N,) Float32 inputs
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output_rni: cute.Tensor, # (N,) Int32 RNE results
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output_rz: cute.Tensor, # (N,) Int32 RZ results
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output_rmi: cute.Tensor, # (N,) Int32 RMI results
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):
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tidx, _, _ = cute.arch.thread_idx()
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if tidx < cutlass.Int32(cute.shape(input_f32)[0]):
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x = cute.arch.load(input_f32.iterator, cutlass.Float32)
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cute.arch.store(output_rni.iterator, f32_to_i32_rni(x))
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cute.arch.store(output_rz.iterator, f32_to_i32_rz(x))
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cute.arch.store(output_rmi.iterator, f32_to_i32_rmi(x))
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@cute.kernel
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def fp4_quant_test_kernel(
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input_f32: cute.Tensor, # (N,) Float32 values
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scale_f32: cute.Tensor, # (1,) Float32 scale
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output_nibble: cute.Tensor, # (N,) Int32 nibbles
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):
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tidx, _, _ = cute.arch.thread_idx()
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if tidx < cutlass.Int32(cute.shape(input_f32)[0]):
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val = cute.arch.load(input_f32.iterator, cutlass.Float32)
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scale = cute.arch.load(scale_f32.iterator, cutlass.Float32)
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nibble = quantize_e2m1_nibble(val, scale)
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cute.arch.store(output_nibble.iterator, nibble)
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if __name__ == "__main__":
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# Test PTX conversions
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N = 12
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test_vals = torch.tensor(
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[0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, -1.7, 0.0, 2.0, 3.0],
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dtype=torch.float32, device='cuda'
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)
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out_rni = torch.zeros(N, dtype=torch.int32, device='cuda')
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out_rz = torch.zeros(N, dtype=torch.int32, device='cuda')
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out_rmi = torch.zeros(N, dtype=torch.int32, device='cuda')
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vc = cutlass_torch.from_dlpack(test_vals).mark_layout_dynamic(leading_dim=0)
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rni_c = cutlass_torch.from_dlpack(out_rni).mark_layout_dynamic(leading_dim=0)
|
||||
rz_c = cutlass_torch.from_dlpack(out_rz).mark_layout_dynamic(leading_dim=0)
|
||||
rmi_c = cutlass_torch.from_dlpack(out_rmi).mark_layout_dynamic(leading_dim=0)
|
||||
|
||||
print("Compiling PTX conversion kernel...")
|
||||
compiled = cute.compile(ptx_convert_test_kernel, vc, rni_c, rz_c, rmi_c)
|
||||
print("Running...")
|
||||
compiled(vc, rni_c, rz_c, rmi_c)
|
||||
|
||||
print("\nPTX conversion results:")
|
||||
for i in range(N):
|
||||
v = test_vals[i].item()
|
||||
print(f" val={v:6.1f} rni={out_rni[i].item():3d} rz={out_rz[i].item():3d} rmi={out_rmi[i].item():3d}")
|
||||
|
||||
# Expected RNE: 0→0, 1.5→2, 2.5→2, 3.5→4, 4.5→4, 5.5→6, 6.5→6, 7.5→8, -1.7→-2, 0→0, 2→2, 3→3
|
||||
expected_rni = [0, 2, 2, 4, 4, 6, 6, 8, -2, 0, 2, 3]
|
||||
rni_ok = all(out_rni[i].item() == expected_rni[i] for i in range(N))
|
||||
print(f"\nRNE correct: {rni_ok}")
|
||||
|
||||
# Test FP4 quantization
|
||||
print("\n--- FP4 Quantization Test ---")
|
||||
q_vals = torch.tensor([0.0, 0.25, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0, -1.0, -3.0],
|
||||
dtype=torch.float32, device='cuda')
|
||||
scale = torch.tensor([1.0], dtype=torch.float32, device='cuda')
|
||||
q_out = torch.zeros(len(q_vals), dtype=torch.int32, device='cuda')
|
||||
|
||||
qvc = cutlass_torch.from_dlpack(q_vals).mark_layout_dynamic(leading_dim=0)
|
||||
sc = cutlass_torch.from_dlpack(scale).mark_layout_dynamic(leading_dim=0)
|
||||
qoc = cutlass_torch.from_dlpack(q_out).mark_layout_dynamic(leading_dim=0)
|
||||
|
||||
print("Compiling FP4 quant kernel...")
|
||||
compiled_q = cute.compile(fp4_quant_test_kernel, qvc, sc, qoc)
|
||||
print("Running...")
|
||||
compiled_q(qvc, sc, qoc)
|
||||
|
||||
# E2M1 values: [0, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0] → indices [0..7]
|
||||
# sign bit: bit 3
|
||||
e2m1_vals = [0, 0.5, 1.0, 1.5, 2.0, 3.0, 4.0, 6.0]
|
||||
print("\nFP4 quantization results (scale=1.0):")
|
||||
for i in range(len(q_vals)):
|
||||
v = q_vals[i].item()
|
||||
nib = q_out[i].item()
|
||||
sign = (nib >> 3) & 1
|
||||
idx = nib & 7
|
||||
dequant = e2m1_vals[idx] if idx < 8 else -1
|
||||
if sign:
|
||||
dequant = -dequant
|
||||
print(f" val={v:6.1f} nibble={nib:2d} sign={sign} idx={idx} dequant={dequant}")
|
||||
|
||||
print("\nDone!")
|
||||
Reference in New Issue
Block a user