test: write O to tb (overwriting P), same as isolated test
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@@ -119,11 +119,11 @@ test_fmha_ts(const bf16_t* q, const bf16_t* k, const bf16_t* v,
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__syncthreads();
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*/
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// Zero O TMEM region
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// Zero O TMEM region at tb (overwriting P — same as isolated test)
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if (wid == 0) {
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for (int n = 0; n < TMEM_O / 8; n++) {
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for (int n = 0; n < 2; n++) { // 16 cols / 8 = 2 iterations
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float z0=0,z1=0,z2=0,z3=0,z4=0,z5=0,z6=0,z7=0;
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asm volatile("tcgen05.st.sync.aligned.32x32b.x8.b32 [%0],{%1,%2,%3,%4,%5,%6,%7,%8};" :: "r"(tb_o+n*8),"f"(z0),"f"(z1),"f"(z2),"f"(z3),"f"(z4),"f"(z5),"f"(z6),"f"(z7));
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asm volatile("tcgen05.st.sync.aligned.32x32b.x8.b32 [%0],{%1,%2,%3,%4,%5,%6,%7,%8};" :: "r"(tb+n*8),"f"(z0),"f"(z1),"f"(z2),"f"(z3),"f"(z4),"f"(z5),"f"(z6),"f"(z7));
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}
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tmem_fence_store();
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}
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@@ -139,7 +139,7 @@ test_fmha_ts(const bf16_t* q, const bf16_t* k, const bf16_t* v,
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uint64_t dv = make_umma_desc_kmajor_none(__cvta_generic_to_shared(sV_base), 16);
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uint32_t tmem_a = tb; // P's first 16 columns
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if (tid == 0) umma_ts_f16(tb_o, tmem_a, dv, idesc_pv, false); // no accumulate for first tile
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if (tid == 0) umma_ts_f16(tb, tmem_a, dv, idesc_pv, false); // Write C to tb (overwriting P)
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asm volatile("tcgen05.fence::after_thread_sync;" ::: "memory");
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__syncthreads();
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}
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@@ -151,7 +151,7 @@ test_fmha_ts(const bf16_t* q, const bf16_t* k, const bf16_t* v,
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float o_vals[HD];
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for (int n = 0; n < HD / 8; n++) {
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float tmp[8];
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb_o + n*8));
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asm volatile("tcgen05.ld.sync.aligned.32x32b.x8.b32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8];" : "=f"(tmp[0]),"=f"(tmp[1]),"=f"(tmp[2]),"=f"(tmp[3]),"=f"(tmp[4]),"=f"(tmp[5]),"=f"(tmp[6]),"=f"(tmp[7]) : "r"(tb + n*8));
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asm volatile("tcgen05.wait::ld.sync.aligned;");
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if (lane == 0) for (int c=0;c<8;c++) o_vals[n*8+c] = tmp[c] * 2.0f; // Undo MMA 0.5 scale
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}
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