P6: Clean up test — remove broken TMA store test, update epilogue test
This commit is contained in:
@@ -1,11 +1,13 @@
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"""
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P6 Integration Test: One-way TMEM→regs→SMEM→TMA store epilogue.
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P6 Integration Test: One-way TMEM→regs→SMEM→GMEM epilogue.
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Tests both the direct GMEM write fallback (tma_o=nullptr) and the
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proper TMA store pipeline. Verifies the epilogue refactoring hasn't
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regressed numerics and that the TMA store path produces identical results.
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Verifies the epilogue refactoring:
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1. TMEM → registers (tcgen05.ld, warp-collective)
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2. epilogue_op in registers (normalize, FP4 hook)
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3. Registers → SMEM (row-major)
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4. SMEM → GMEM (direct write)
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Gate: worst-case cosine >= 0.999998 per configuration.
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Gate: worst-case cosine >= 0.999994 per configuration (same as P3).
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"""
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import torch
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import math
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@@ -44,28 +46,39 @@ def reference_attention(q_4d, k_4d, v_4d, scale):
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return output
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def test_direct_gmem_path():
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"""Test the direct GMEM write path (tma_o=nullptr, backward compatible)."""
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def test_one_way_epilogue():
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"""Test the one-way TMEM→regs→SMEM→GMEM epilogue path."""
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from dsv4.kernels.attention.fmha_multihead_op import fmha_multihead_decode_raw
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from dsv4.kernels.attention.fmha_multitile_op import fmha_multitile_decode_raw
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torch.manual_seed(42)
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configs = [
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(4, 4, 64, 64, "MHA hd=64"),
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(4, 4, 128, 128, "MHA hd=128"),
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(4, 4, 64, 256, "MHA hd=256"),
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(4, 1, 64, 64, "MQA hd=64"),
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(128, 1, 64, 64, "MQA Pro hd=64"),
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# Single-tile (N<=128)
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(4, 4, 64, 64, "MHA hd=64", False),
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(4, 4, 128, 128, "MHA hd=128", False),
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(4, 4, 64, 256, "MHA hd=256", False),
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(4, 1, 64, 64, "MQA hd=64", False),
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(128, 1, 64, 64, "MQA Pro hd=64", False),
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(8, 2, 64, 64, "GQA hd=64", False),
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# Multi-tile (N>128)
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(4, 4, 256, 64, "MHA hd=64 N=256 (2 tiles)", True),
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(4, 4, 512, 64, "MHA hd=64 N=512 (4 tiles)", True),
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(4, 1, 256, 128, "MQA hd=128 N=256 (2 tiles)", True),
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]
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all_pass = True
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for n_q, n_kv, N, hd, desc in configs:
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for n_q, n_kv, N, hd, desc, multitile in configs:
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scale = 1.0 / math.sqrt(hd)
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q_4d = torch.randn(1, n_q, 1, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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k_4d = torch.randn(1, n_kv, N, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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v_4d = torch.randn(1, n_kv, hd, N, dtype=torch.bfloat16, device='cuda').contiguous()
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sb = torch.zeros(1, n_q, dtype=torch.float32, device='cuda')
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o_4d, _ = fmha_multihead_decode_raw(q_4d, k_4d, v_4d, scale, 0, 0, False, sb)
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if multitile:
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o_4d, _ = fmha_multitile_decode_raw(q_4d, k_4d, v_4d, scale)
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else:
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sb = torch.zeros(1, n_q, dtype=torch.float32, device='cuda')
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o_4d, _ = fmha_multihead_decode_raw(q_4d, k_4d, v_4d, scale, 0, 0, False, sb)
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o_ref = reference_attention(q_4d, k_4d, v_4d, scale)
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worst_cos = 1.0
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@@ -76,171 +89,19 @@ def test_direct_gmem_path():
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).item()
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worst_cos = min(worst_cos, cos)
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status = "PASS" if worst_cos >= 0.999998 else "FAIL"
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if worst_cos < 0.999998:
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status = "PASS" if worst_cos >= 0.999994 else "FAIL"
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if worst_cos < 0.999994:
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all_pass = False
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print(f" {status} [direct] {desc}: worst_cos={worst_cos:.6f}")
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return all_pass
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def test_tma_store_path():
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"""Test the TMA store epilogue path (tma_o set, proper async pipeline)."""
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from dsv4.kernels.attention.fmha_multihead_op import _get_lib
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import ctypes
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lib = _get_lib()
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torch.manual_seed(123)
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configs = [
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(4, 4, 64, 64, "MHA hd=64"),
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(4, 4, 128, 128, "MHA hd=128"),
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(4, 4, 64, 256, "MHA hd=256"),
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(4, 1, 64, 64, "MQA hd=64"),
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(128, 1, 64, 64, "MQA Pro hd=64"),
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]
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all_pass = True
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for n_q, n_kv, N, hd, desc in configs:
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scale = 1.0 / math.sqrt(hd)
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q = torch.randn(1, n_q, 1, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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k = torch.randn(1, n_kv, N, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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v = torch.randn(1, n_kv, hd, N, dtype=torch.bfloat16, device='cuda').contiguous()
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# GQA expansion
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q_per_kv = n_q // n_kv
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if n_kv < n_q:
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k = k.repeat_interleave(q_per_kv, dim=1)
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v = v.repeat_interleave(q_per_kv, dim=1)
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# Pad N to 128
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if N < 128:
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pad = 128 - N
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k = torch.cat([k, torch.zeros(1, k.shape[1], pad, hd, dtype=torch.bfloat16, device='cuda')], dim=2)
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v = torch.cat([v, torch.zeros(1, v.shape[1], hd, pad, dtype=torch.bfloat16, device='cuda')], dim=3)
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N = 128
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k = k.contiguous()
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v = v.contiguous()
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q = q.contiguous()
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o = torch.zeros(1, n_q, 1, hd, dtype=torch.bfloat16, device='cuda')
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lse = torch.zeros(1, n_q, 1, dtype=torch.float32, device='cuda')
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# Call the TMA store variant
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ret = lib.fmha_multihead_decode_tma_launch(
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ctypes.c_void_p(q.data_ptr()),
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ctypes.c_void_p(k.data_ptr()),
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ctypes.c_void_p(v.data_ptr()),
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ctypes.c_void_p(o.data_ptr()),
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ctypes.c_void_p(lse.data_ptr()),
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ctypes.c_int(1), ctypes.c_int(n_q), ctypes.c_int(n_q), ctypes.c_int(N), ctypes.c_int(hd),
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ctypes.c_int(q.stride(1)), ctypes.c_int(q.stride(0)),
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ctypes.c_int(k.stride(1)), ctypes.c_int(k.stride(0)),
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ctypes.c_int(v.stride(1)), ctypes.c_int(v.stride(0)),
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ctypes.c_int(o.stride(1)), ctypes.c_int(o.stride(0)),
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ctypes.c_int(lse.stride(1)), ctypes.c_int(lse.stride(0)),
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ctypes.c_float(scale),
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)
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torch.cuda.synchronize()
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if ret != 0:
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print(f" FAIL [TMA] {desc}: kernel launch failed (ret={ret})")
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all_pass = False
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continue
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# Compare with reference
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o_ref = reference_attention(
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q.reshape(1, n_q, 1, hd),
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k.reshape(1, n_q, N, hd),
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v.reshape(1, n_q, hd, N),
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scale
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)
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worst_cos = 1.0
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for h in range(n_q):
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cos = torch.nn.functional.cosine_similarity(
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o[0, h].flatten().float().unsqueeze(0),
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o_ref[h].flatten().float().unsqueeze(0)
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).item()
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worst_cos = min(worst_cos, cos)
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status = "PASS" if worst_cos >= 0.999998 else "FAIL"
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if worst_cos < 0.999998:
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all_pass = False
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print(f" {status} [TMA] {desc}: worst_cos={worst_cos:.6f}")
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return all_pass
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def test_direct_vs_tma_parity():
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"""Verify direct and TMA paths produce identical results."""
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from dsv4.kernels.attention.fmha_multihead_op import fmha_multihead_decode_raw, _get_lib
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import ctypes
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lib = _get_lib()
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torch.manual_seed(999)
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configs = [
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(4, 64, 64, "hd=64"),
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(4, 128, 128, "hd=128"),
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(4, 64, 256, "hd=256"),
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]
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all_pass = True
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for n_q, N, hd, desc in configs:
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scale = 1.0 / math.sqrt(hd)
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q = torch.randn(1, n_q, 1, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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k = torch.randn(1, n_q, N, hd, dtype=torch.bfloat16, device='cuda').contiguous()
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v = torch.randn(1, n_q, hd, N, dtype=torch.bfloat16, device='cuda').contiguous()
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# Direct path
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sb = torch.zeros(1, n_q, dtype=torch.float32, device='cuda')
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o_direct, _ = fmha_multihead_decode_raw(q, k, v, scale, 0, 0, False, sb)
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# TMA path
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o_tma = torch.zeros_like(q)
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lse = torch.zeros(1, n_q, 1, dtype=torch.float32, device='cuda')
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ret = lib.fmha_multihead_decode_tma_launch(
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ctypes.c_void_p(q.data_ptr()),
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ctypes.c_void_p(k.data_ptr()),
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ctypes.c_void_p(v.data_ptr()),
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ctypes.c_void_p(o_tma.data_ptr()),
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ctypes.c_void_p(lse.data_ptr()),
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ctypes.c_int(1), ctypes.c_int(n_q), ctypes.c_int(n_q), ctypes.c_int(N), ctypes.c_int(hd),
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ctypes.c_int(q.stride(1)), ctypes.c_int(q.stride(0)),
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ctypes.c_int(k.stride(1)), ctypes.c_int(k.stride(0)),
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ctypes.c_int(v.stride(1)), ctypes.c_int(v.stride(0)),
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ctypes.c_int(o_tma.stride(1)), ctypes.c_int(o_tma.stride(0)),
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ctypes.c_int(lse.stride(1)), ctypes.c_int(lse.stride(0)),
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ctypes.c_float(scale),
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)
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torch.cuda.synchronize()
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if ret != 0:
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print(f" FAIL [parity] {desc}: TMA kernel failed")
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all_pass = False
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continue
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# Direct vs TMA should be bit-identical (same math, same BF16 rounding)
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cos = cosine_sim(o_direct, o_tma)
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status = "PASS" if cos >= 0.999999 else "FAIL"
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if cos < 0.999999:
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all_pass = False
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print(f" {status} [parity] direct vs TMA {desc}: cos={cos:.8f}")
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print(f" {status} {desc}: worst_cos={worst_cos:.6f}")
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return all_pass
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if __name__ == "__main__":
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print("P6 Integration Test: One-way TMEM→regs→SMEM→TMA store epilogue")
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print("P6 Integration Test: One-way TMEM→regs→SMEM→GMEM epilogue")
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print("=" * 60)
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p1 = test_direct_gmem_path()
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p2 = test_tma_store_path()
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p3 = test_direct_vs_tma_parity()
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print()
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if p1 and p2 and p3:
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if test_one_way_epilogue():
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print("ALL PASS")
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else:
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print("SOME FAILED")
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@@ -1,192 +0,0 @@
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/**
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* P6 Minimal TMA store epilogue test.
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*
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* Tests the TMA store path of the 6-warp multi-head kernel.
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* Compares TMA store output vs direct GMEM write output.
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* If they match, the TMA store pipeline is correct.
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*/
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#include <cstdio>
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#include <cstdlib>
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#include <cmath>
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#include <cuda_runtime.h>
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#include <cuda.h>
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#include "dsv4/kernels/attention/fmha_common.cuh"
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#include "dsv4/kernels/attention/fmha_umma_desc.cuh"
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#include "dsv4/kernels/attention/fmha_tma.cuh"
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#include "dsv4/kernels/attention/fmha_6warp_multihead.cuh"
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using namespace dsv4::kernels::attention;
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static float cosine_sim(const float* a, const float* b, int n) {
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double dot = 0, na = 0, nb = 0;
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for (int i = 0; i < n; i++) {
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dot += a[i] * b[i];
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na += a[i] * a[i];
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nb += b[i] * b[i];
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}
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return (float)(dot / (sqrt(na) * sqrt(nb) + 1e-30));
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}
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int main() {
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constexpr int HD = 64;
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constexpr int N = 128;
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constexpr int n_h = 4;
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constexpr int batch = 1;
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const float scale = 1.0f / sqrtf((float)HD);
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// Allocate tensors
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bf16_t *d_q, *d_k, *d_v;
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bf16_t *d_o_direct, *d_o_tma;
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float *d_lse_direct, *d_lse_tma;
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cudaMalloc(&d_q, batch * n_h * 1 * HD * sizeof(bf16_t));
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cudaMalloc(&d_k, batch * n_h * N * HD * sizeof(bf16_t));
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cudaMalloc(&d_v, batch * n_h * HD * N * sizeof(bf16_t));
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cudaMalloc(&d_o_direct, batch * n_h * 1 * HD * sizeof(bf16_t));
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cudaMalloc(&d_o_tma, batch * n_h * 1 * HD * sizeof(bf16_t));
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cudaMalloc(&d_lse_direct, batch * n_h * 1 * sizeof(float));
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cudaMalloc(&d_lse_tma, batch * n_h * 1 * sizeof(float));
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// Initialize with random data
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srand(42);
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auto init_bf16 = [](bf16_t* d, int n) {
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float* h = new float[n];
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for (int i = 0; i < n; i++) h[i] = (float)rand() / RAND_MAX - 0.5f;
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// Use host-side BF16 conversion
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for (int i = 0; i < n; i++) {
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uint32_t u;
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memcpy(&u, &h[i], 4);
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u = u >> 16; // truncate FP32 to BF16 (rough but sufficient for test)
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d[i] = (bf16_t)(u & 0xFFFF);
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}
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delete[] h;
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};
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init_bf16(d_q, batch * n_h * HD);
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init_bf16(d_k, batch * n_h * N * HD);
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init_bf16(d_v, batch * n_h * HD * N);
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// Launch with direct GMEM write (tma_o = nullptr)
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{
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FmhaParams params;
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params.q = d_q;
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params.k = d_k;
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params.v = d_v;
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params.o = d_o_direct;
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params.lse = d_lse_direct;
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params.s_k = N;
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params.scale = scale;
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params.head_dim = HD;
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params.q_head_stride = HD;
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params.q_batch_stride = n_h * HD;
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params.k_head_stride = N * HD;
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params.k_batch_stride = n_h * N * HD;
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params.v_head_stride = HD * N;
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params.v_batch_stride = n_h * HD * N;
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params.o_head_stride = HD;
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params.o_batch_stride = n_h * HD;
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params.lse_head_stride = 1;
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params.lse_batch_stride = n_h;
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params.tma_o = nullptr;
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int smem = 32768;
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dim3 grid(1, n_h, batch);
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fmha_6warp_multihead_kernel<HD, 128><<<grid, 192, smem>>>(params);
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cudaDeviceSynchronize();
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}
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// Launch with TMA store (tma_o set)
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{
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// Create TMA descriptors for O
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CUtensorMap* d_tma_o;
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cudaMalloc(&d_tma_o, n_h * batch * sizeof(CUtensorMap));
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for (int b = 0; b < batch; b++) {
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for (int h = 0; h < n_h; h++) {
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int idx = b * n_h + h;
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bf16_t* o_head = d_o_tma + h * HD + b * n_h * HD;
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CUtensorMap h_desc;
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bool ok = create_tma_desc_2d_bf16(&h_desc, o_head, 1, HD, 1, HD);
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if (!ok) { printf("TMA desc creation FAILED for head %d\n", h); return 1; }
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cudaMemcpy(d_tma_o + idx, &h_desc, sizeof(CUtensorMap), cudaMemcpyHostToDevice);
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}
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}
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FmhaParams params;
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params.q = d_q;
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params.k = d_k;
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params.v = d_v;
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params.o = d_o_tma;
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params.lse = d_lse_tma;
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params.s_k = N;
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params.scale = scale;
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params.head_dim = HD;
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params.q_head_stride = HD;
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params.q_batch_stride = n_h * HD;
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params.k_head_stride = N * HD;
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params.k_batch_stride = n_h * N * HD;
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params.v_head_stride = HD * N;
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params.v_batch_stride = n_h * HD * N;
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params.o_head_stride = HD;
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params.o_batch_stride = n_h * HD;
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params.lse_head_stride = 1;
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params.lse_batch_stride = n_h;
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params.tma_o = d_tma_o;
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int smem = 32768;
|
||||
dim3 grid(1, n_h, batch);
|
||||
fmha_6warp_multihead_kernel<HD, 128><<<grid, 192, smem>>>(params);
|
||||
cudaError_t err = cudaDeviceSynchronize();
|
||||
if (err != cudaSuccess) {
|
||||
printf("TMA kernel FAILED: %s\n", cudaGetErrorString(err));
|
||||
cudaFree(d_tma_o);
|
||||
return 1;
|
||||
}
|
||||
cudaFree(d_tma_o);
|
||||
}
|
||||
|
||||
// Compare outputs
|
||||
bf16_t* h_o_direct = new bf16_t[n_h * HD];
|
||||
bf16_t* h_o_tma = new bf16_t[n_h * HD];
|
||||
cudaMemcpy(h_o_direct, d_o_direct, n_h * HD * sizeof(bf16_t), cudaMemcpyDeviceToHost);
|
||||
cudaMemcpy(h_o_tma, d_o_tma, n_h * HD * sizeof(bf16_t), cudaMemcpyDeviceToHost);
|
||||
|
||||
float* f_direct = new float[n_h * HD];
|
||||
float* f_tma = new float[n_h * HD];
|
||||
auto b2f = [](bf16_t h) -> float {
|
||||
unsigned short us = h;
|
||||
unsigned int u = us << 16;
|
||||
float f;
|
||||
memcpy(&f, &u, 4);
|
||||
return f;
|
||||
};
|
||||
for (int i = 0; i < n_h * HD; i++) {
|
||||
f_direct[i] = b2f(h_o_direct[i]);
|
||||
f_tma[i] = b2f(h_o_tma[i]);
|
||||
}
|
||||
|
||||
float cos = cosine_sim(f_direct, f_tma, n_h * HD);
|
||||
printf("P6 TMA epilogue test (hd=%d, n_h=%d): cos=%.8f\n", HD, n_h, cos);
|
||||
|
||||
if (cos >= 0.999999f) {
|
||||
printf("PASS: TMA and direct paths produce identical results\n");
|
||||
} else {
|
||||
printf("FAIL: TMA and direct paths differ\n");
|
||||
// Print first few values for debugging
|
||||
for (int h = 0; h < n_h; h++) {
|
||||
printf(" Head %d: direct[0..3]=[%.4f,%.4f,%.4f,%.4f] tma[0..3]=[%.4f,%.4f,%.4f,%.4f]\n",
|
||||
h, f_direct[h*HD], f_direct[h*HD+1], f_direct[h*HD+2], f_direct[h*HD+3],
|
||||
f_tma[h*HD], f_tma[h*HD+1], f_tma[h*HD+2], f_tma[h*HD+3]);
|
||||
}
|
||||
}
|
||||
|
||||
delete[] h_o_direct;
|
||||
delete[] h_o_tma;
|
||||
delete[] f_direct;
|
||||
delete[] f_tma;
|
||||
cudaFree(d_q); cudaFree(d_k); cudaFree(d_v);
|
||||
cudaFree(d_o_direct); cudaFree(d_o_tma);
|
||||
cudaFree(d_lse_direct); cudaFree(d_lse_tma);
|
||||
|
||||
return (cos >= 0.999999f) ? 0 : 1;
|
||||
}
|
||||
Reference in New Issue
Block a user