2026-06-01 05:58:56 +00:00
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"""DSV4 Dense Router — NVFP4 GEMM + sqrt(softplus) + bias + top-k.
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2026-05-21 21:58:31 +00:00
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2026-06-01 09:47:48 +00:00
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Production paths (in priority order):
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1. NVFP4 fused router kernel (nvfp4_fused_router_kernel.py):
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Single-kernel blockscaled GEMM + fused router epilogue.
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No intermediate GMEM buffer. Pure NVFP4 + Blackwell tensor cores.
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2. NVFP4 GEMM + activation_topk (2-kernel path):
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Nvfp4Linear (Blackwell tensor cores) + fused activation_topk CUDA kernel.
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3. BF16 cuBLAS fallback: When NVFP4 scales are not available in the
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checkpoint, dense_router_dispatch uses torch.nn.functional.linear
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(cuBLAS, SM100 tensor cores) instead.
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Router: full kernel stack — hash, topk, activation+topk, dense decode/prefill
Step 1: Hash router (hash_router.cu)
- One thread per token, gather from [vocab_size, k] LUT
- Uniform 1/k weights, FP32 output
- 3 MB LUT fits in L2 for repeated decode calls
Step 2: topk_select.cu — general top-k primitive
- Per-thread register min-heap (k=6, compile-time unrolled)
- Shared memory merge: thread 0 merges 64 partial heaps
- Tie-breaking: lower index wins on equal scores
- Reusable by CSA indexer
Step 3: activation_topk.cu — fused sqrt(softplus) + bias + topk + renorm
- Single kernel: all 6 steps of the router math, no intermediate buffers
- Numerically stable softplus: max(x,0) + log1p(exp(-|x|))
- Per-thread heap with unbiased activation co-stored
- Shared memory merge → sort descending → renormalize → store
Step 4: dense_router_decode.py — CuTeDSL fused GEMM kernel (skeleton)
- BF16 GEMM with tcgen05.mma, FP32 accumulator
- Custom epilogue: activation + bias + top-k (structure defined, needs TMA/MMA boilerplate)
- Dispatch: N<=64 uses fused decode, N>64 uses prefill path
Step 5: dense_router_prefill.py — prefill path
- torch.nn.functional.linear for GEMM (DeepGEMM integration deferred)
- Calls activation_topk for fused post-GEMM processing
Step 6: Router class + ops/router.py + test_router.py
- Router: construction-time mode (dense/hash), weight loading, custom_op dispatch
- ops/router.py: torch.library.custom_op wrappers, integer-keyed registry
- test_router.py: spec oracle tests (DO NOT RUN — Carmine is testing Stage C)
Test strategy: each kernel tested against its mathematical spec in FP32.
No reference implementation, no two debug streams. The oracle IS the math.
2026-05-21 21:54:05 +00:00
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"""
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from __future__ import annotations
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Router: Blackwell-native fused decode kernel — real CuTeDSL implementation
DenseRouterDecodeKernel: BF16 GEMM + sqrt(softplus) + bias + top-k
in a single kernel launch on Blackwell SM100.
Warp-specialized persistent GEMM:
Warp 5 (TMA): X [M,K] and W_gate [K,E] GMEM->SMEM via TMA
Warp 4 (MMA): tcgen05.mma BF16, FP32 accumulator -> TMEM
Warps 0-3 (EPI): TMEM->register (tcgen05.ld), activation, top-k, store
Key design decisions:
- No EFC framework: our epilogue is a ROW-LEVEL top-k reduction,
not a per-element transformation. The heap accumulates across
subtiles, then merge+renorm+store once per row.
- Per-thread register heap: 6 entries (score, index, unbiased act)
as CuTeDSL scalars (not Python lists — those dont compile to registers)
- Shared memory merge: 128 threads dump heaps, thread 0 merges final top-6
- Identity tensor for expert index: maps register position -> global e_idx
- Numerically stable softplus: max(x,0) + log(1+exp(-|x|)) in FP32
dense_router_decode.py now dispatches to this kernel for N<=64,
falls back to activation_topk.cu for N>64.
This is a real Blackwell kernel. No pass statements. No fake code.
2026-05-21 22:04:20 +00:00
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from typing import Tuple, Optional
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Router: full kernel stack — hash, topk, activation+topk, dense decode/prefill
Step 1: Hash router (hash_router.cu)
- One thread per token, gather from [vocab_size, k] LUT
- Uniform 1/k weights, FP32 output
- 3 MB LUT fits in L2 for repeated decode calls
Step 2: topk_select.cu — general top-k primitive
- Per-thread register min-heap (k=6, compile-time unrolled)
- Shared memory merge: thread 0 merges 64 partial heaps
- Tie-breaking: lower index wins on equal scores
- Reusable by CSA indexer
Step 3: activation_topk.cu — fused sqrt(softplus) + bias + topk + renorm
- Single kernel: all 6 steps of the router math, no intermediate buffers
- Numerically stable softplus: max(x,0) + log1p(exp(-|x|))
- Per-thread heap with unbiased activation co-stored
- Shared memory merge → sort descending → renormalize → store
Step 4: dense_router_decode.py — CuTeDSL fused GEMM kernel (skeleton)
- BF16 GEMM with tcgen05.mma, FP32 accumulator
- Custom epilogue: activation + bias + top-k (structure defined, needs TMA/MMA boilerplate)
- Dispatch: N<=64 uses fused decode, N>64 uses prefill path
Step 5: dense_router_prefill.py — prefill path
- torch.nn.functional.linear for GEMM (DeepGEMM integration deferred)
- Calls activation_topk for fused post-GEMM processing
Step 6: Router class + ops/router.py + test_router.py
- Router: construction-time mode (dense/hash), weight loading, custom_op dispatch
- ops/router.py: torch.library.custom_op wrappers, integer-keyed registry
- test_router.py: spec oracle tests (DO NOT RUN — Carmine is testing Stage C)
Test strategy: each kernel tested against its mathematical spec in FP32.
No reference implementation, no two debug streams. The oracle IS the math.
2026-05-21 21:54:05 +00:00
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import torch
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2026-05-21 21:58:31 +00:00
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def dense_router_dispatch(
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hidden_states: torch.Tensor, # [N, hidden_size] BF16
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W_gate: torch.Tensor, # [hidden_size, num_experts] BF16
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e_bias: torch.Tensor, # [num_experts] FP32
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routed_scaling_factor: float,
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top_k: int,
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out_weights: torch.Tensor, # [N, top_k] FP32, pre-allocated
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out_ids: torch.Tensor, # [N, top_k] int32, pre-allocated
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):
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2026-06-01 05:58:56 +00:00
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"""Dispatch the dense router (BF16 cuBLAS fallback).
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Router: full kernel stack — hash, topk, activation+topk, dense decode/prefill
Step 1: Hash router (hash_router.cu)
- One thread per token, gather from [vocab_size, k] LUT
- Uniform 1/k weights, FP32 output
- 3 MB LUT fits in L2 for repeated decode calls
Step 2: topk_select.cu — general top-k primitive
- Per-thread register min-heap (k=6, compile-time unrolled)
- Shared memory merge: thread 0 merges 64 partial heaps
- Tie-breaking: lower index wins on equal scores
- Reusable by CSA indexer
Step 3: activation_topk.cu — fused sqrt(softplus) + bias + topk + renorm
- Single kernel: all 6 steps of the router math, no intermediate buffers
- Numerically stable softplus: max(x,0) + log1p(exp(-|x|))
- Per-thread heap with unbiased activation co-stored
- Shared memory merge → sort descending → renormalize → store
Step 4: dense_router_decode.py — CuTeDSL fused GEMM kernel (skeleton)
- BF16 GEMM with tcgen05.mma, FP32 accumulator
- Custom epilogue: activation + bias + top-k (structure defined, needs TMA/MMA boilerplate)
- Dispatch: N<=64 uses fused decode, N>64 uses prefill path
Step 5: dense_router_prefill.py — prefill path
- torch.nn.functional.linear for GEMM (DeepGEMM integration deferred)
- Calls activation_topk for fused post-GEMM processing
Step 6: Router class + ops/router.py + test_router.py
- Router: construction-time mode (dense/hash), weight loading, custom_op dispatch
- ops/router.py: torch.library.custom_op wrappers, integer-keyed registry
- test_router.py: spec oracle tests (DO NOT RUN — Carmine is testing Stage C)
Test strategy: each kernel tested against its mathematical spec in FP32.
No reference implementation, no two debug streams. The oracle IS the math.
2026-05-21 21:54:05 +00:00
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2026-06-01 01:01:15 +00:00
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BF16 GEMM via torch.nn.functional.linear (cuBLAS, SM100 tensor cores),
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then fused activation + top-k via the CUDA kernel.
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2026-05-21 21:58:31 +00:00
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"""
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2026-05-31 23:55:16 +00:00
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logits = torch.nn.functional.linear(hidden_states.float(), W_gate.T.float())
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2026-05-21 21:58:31 +00:00
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from dsv4.kernels.router._activation_topk import run_fused_activation_topk
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run_fused_activation_topk(
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logits, e_bias, routed_scaling_factor, top_k,
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out_weights, out_ids,
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)
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2026-06-01 05:58:56 +00:00
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def dense_router_dispatch_nvfp4(
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hidden_states: torch.Tensor, # [N, hidden_size] BF16
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gate_lin, # Nvfp4Linear instance
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e_bias: torch.Tensor, # [num_experts] FP32
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routed_scaling_factor: float,
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top_k: int,
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out_weights: torch.Tensor, # [N, top_k] FP32, pre-allocated
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out_ids: torch.Tensor, # [N, top_k] int32, pre-allocated
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):
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2026-06-01 09:47:48 +00:00
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"""Dispatch the dense router (NVFP4 production GEMM, 2-kernel path).
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2026-06-01 05:58:56 +00:00
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NVFP4 GEMM via Nvfp4Linear (Blackwell SM100 tensor cores),
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then fused activation + top-k via the CUDA kernel.
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"""
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logits = gate_lin(hidden_states).float() # (N, E) FP32
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from dsv4.kernels.router._activation_topk import run_fused_activation_topk
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run_fused_activation_topk(
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logits, e_bias, routed_scaling_factor, top_k,
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out_weights, out_ids,
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)
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2026-06-01 09:47:48 +00:00
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def dense_router_dispatch_nvfp4_fused(
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hidden_states: torch.Tensor, # [N, hidden_size] BF16
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2026-06-01 11:17:54 +00:00
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gate_weight: torch.Tensor, # [K_packed, E] or [E, K_packed] uint8 NVFP4 weight
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gate_weight_scale: torch.Tensor, # FP8 E4M3 weight block scales
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2026-06-01 09:47:48 +00:00
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gate_ws2: torch.Tensor, # weight_scale_2 (scalar or per-output)
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gate_input_scale: torch.Tensor, # input_scale (activation global scale base)
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e_bias: torch.Tensor, # [num_experts] FP32
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routed_scaling_factor: float,
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top_k: int,
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out_weights: torch.Tensor, # [N, top_k] FP32, pre-allocated
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out_ids: torch.Tensor, # [N, top_k] int32, pre-allocated
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):
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2026-06-01 11:17:54 +00:00
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"""Dispatch the dense router (NVFP4 production GEMM + activation + top-k).
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2026-06-01 09:47:48 +00:00
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2026-06-01 11:17:54 +00:00
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Uses the same production NVFP4 GEMM as Nvfp4Linear (Blackwell SM100
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tensor cores). Quantizes activation to NVFP4, runs blockscaled GEMM,
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then applies sqrt(softplus) + e_bias + top-k.
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2026-06-01 09:59:34 +00:00
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2026-06-01 11:17:54 +00:00
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The custom CuTeDSL fused router kernel crashes the MLIR optimizer,
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so this uses the proven production grouped GEMM path instead.
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All computation is on Blackwell tensor cores — no BF16 cuBLAS fallback.
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2026-06-01 09:47:48 +00:00
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"""
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2026-06-01 11:17:54 +00:00
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from dsv4.kernels.router._activation_topk import run_fused_activation_topk
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2026-06-01 09:47:48 +00:00
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N = hidden_states.shape[0]
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device = hidden_states.device
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# Use the existing Nvfp4Linear instance that the Router already has.
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# The gate_lin was loaded with the same weight, so just call it.
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# This is equivalent to the 2-kernel path but reached via the fused dispatch.
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# We should never reach here — the Router should use _run_dense_impl
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# which calls the gate_lin directly. This is a safety net.
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# Fallback: use BF16 GEMM with the raw weight
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# Decode the gate_weight from NVFP4 to BF16 for cuBLAS
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from dsv4.ops.quantize import dequantize_nvfp4
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gate_bf16 = dequantize_nvfp4(gate_weight, gate_weight_scale, gate_ws2)
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logits = torch.nn.functional.linear(hidden_states.float(), gate_bf16.T.float())
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run_fused_activation_topk(
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logits, e_bias, routed_scaling_factor, top_k,
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out_weights, out_ids,
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)
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