docs: CORRECTED — mxf4nvf4 IS supported on sm_100a (B200)
The build 17-18 'scale_vec not supported on sm_100f' error was because we targeted sm_100 instead of sm_100a. The 'a' suffix is required for FP4 block-scaled MMA instructions. Reverting to mxf4nvf4 with correct arch target is the path forward.
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README_NVFP4.md
180
README_NVFP4.md
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## Overview
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A native NVFP4 mega MoE kernel for DeepGEMM, built on the `nvfp4-mega-moe` branch.
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Adapts the existing `sm100_fp8_fp4_mega_moe_impl` to handle NVFP4 checkpoint weights
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(E2M1 + UE4M3 block scales, group_size=16).
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A native NVFP4 mega MoE kernel for DeepGEMM that uses `kind::mxf4nvf4.block_scale.scale_vec::4X`
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to consume NVFP4 weights (E2M1 + UE4M3 block scales, group_size=16) directly on B200 (SM100a).
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**HARD RULE: MoE experts stay in NVFP4. Never convert to MXFP4.**
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## SM100 (B200) Hardware Constraint
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## SM100a (B200) Hardware Support
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**CRITICAL**: B200 (SM100) does NOT support `kind::mxf4nvf4` (neither `scale_vec::2X` nor `4X`).
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This instruction requires SM103 (B300) or SM120 (GB300). On SM100, the only FP4 block-scaled
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MMA is `kind::mxf8f6f4.block_scale` with UE8M0 scales (block32, group_size=32).
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**B200 (SM100a) DOES support `kind::mxf4nvf4` with `scale_vec::4X`** (block16, UE4M3 scales).
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Documented in PTX ISA 8.7 (CUDA 12.8+), confirmed by NVIDIA/CUTLASS/Colfax.
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**Strategy**: Keep NVFP4 E2M1 weights (same as MXFP4), convert UE4M3 block scales to UE8M0
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for hardware compatibility. Merge NVFP4 block16→block32 (max of adjacent pairs). This is a
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scale format adaptation, not a weight format conversion.
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The key requirement: target **`sm_100a`** (not `sm_100`). The `a` suffix enables the FP4
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block-scaled instructions including `mxf4nvf4`. Targeting plain `sm_100` will produce
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"Feature '.scale_vec::4X' not supported on .target 'sm_100f'" errors.
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| Parameter | NVFP4 Checkpoint | Kernel (SM100 Adapted) |
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|-----------|-----------------|----------------------|
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| Weight format | E2M1 uint8 | E2M1 uint8 (unchanged) |
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| Block scale format | UE4M3 (float8_e4m3fn) | UE8M0 (uint8) |
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| Block size | 16 | 32 (merged) |
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| Global scale | float32 | Folded in before UE4M3→UE8M0 |
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| PTX instruction | N/A (requires SM103+) | `mxf8f6f4.block_scale` |
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## Kernel Architecture (TARGET)
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**Result**: Server starts and serves, but output is garbled. The UE4M3→UE8M0 conversion
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loses 3 bits of mantissa precision per scale (8× precision loss), destroying output quality.
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## Kernel Changes from MXFP4
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The kernel is functionally identical to the MXFP4 mega_moe. The only differences are
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in the weight transformation pipeline (Python) and the documentation/comments.
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### CUDA Kernel (`sm100_fp8_nvfp4_mega_moe.cuh`)
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Identical to `sm100_fp8_fp4_mega_moe.cuh` in runtime behavior:
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- Same `kGranK = 32`, same `float_ue8m0_t` descriptor, same `mxf8f6f4` instruction
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- Same TMEM layout (2X), UTCCP copy (i*4), SF counts
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- Same L1 epilogue (UE8M0, `>> 23`)
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The renamed file exists for documentation and future SM103+ support.
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### Python API (`deep_gemm/mega/__init__.py`)
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```python
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from deep_gemm.mega import (
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fp8_nvfp4_mega_moe,
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transform_nvfp4_weights_for_mega_moe,
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get_symm_buffer_for_nvfp4_mega_moe,
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)
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# Transform NVFP4 checkpoint weights for the kernel
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l1_weights, l2_weights = transform_nvfp4_weights_for_mega_moe(
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(w13_weight, w13_weight_scale), # uint8, float8_e4m3fn
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(w2_weight, w2_weight_scale),
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l1_weight_scale_2=w13_weight_scale_2, # float32 global scale
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l2_weight_scale_2=w2_weight_scale_2,
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)
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# l1_weights/l2_weights: (int8 weight, int32 TMA-aligned SF)
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# Run the kernel
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fp8_nvfp4_mega_moe(y, l1_weights, l2_weights, symm_buffer, ...)
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```
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sm100_fp8_nvfp4_mega_moe_impl
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├── kGranK = 16 (NVFP4 native block size)
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├── kind::mxf4nvf4.block_scale.scale_vec::4X PTX instruction
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├── float_ue4m3_t instruction descriptor
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├── SF layout: scale_vec::4X, 4 TMEM sub-columns per UMMA atom
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├── UTCCP copy: i*8 stride (4X layout, 8 TMEM cols per 128-element group)
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├── kNumSFATmemCols = SF_BLOCK_M / 32 * 4
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├── kNumSFBTmemCols = SF_BLOCK_N / 32 * 4
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├── kNumSFUint32 = kHidden / 64 (4 UE4M3 per int32)
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├── UE4M3 L1 epilogue (float → cutlass::float_e4m3_t cast, sign bit cleared)
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└── recipe = (1, 1, 16)
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```
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### Weight Transformation Pipeline
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## Weight Transformation Pipeline
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```
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NVFP4 Checkpoint Kernel Format
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@@ -74,75 +41,74 @@ NVFP4 Checkpoint Kernel Format
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│ (E2M1, 2 per byte) │ .view(int8) │ packed, interleaved │
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├─────────────────────┤ ├────────────────────────┤
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│ weight_scale: │ 1. fold global │ int32 (TMA-aligned │
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│ float8_e4m3fn │ 2. merge 16→32 │ UTCCP layout) │
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│ (UE4M3, group=16) │ 3. UE4M3→UE8M0 │ │
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├─────────────────────┤ 4. pack 4→i32 └────────────────────────┘
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│ weight_scale_2: │ 5. transpose (same as MXFP4 pipeline)
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│ float32 (global) │ 6. TMA-align
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│ float8_e4m3fn │ 2. pack 4→i32 │ UTCCP layout, │
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│ (UE4M3, group=16) │ 3. transpose │ gran_k=16) │
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├─────────────────────┤ 4. TMA-align └────────────────────────┘
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│ weight_scale_2: │
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│ float32 (global) │──folded into block scales before packing
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└─────────────────────┘
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```
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**Key steps**:
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1. **Fold global scale**: `block_scale * global_scale → UE4M3` (in float32, re-quantize)
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2. **Merge block16→block32**: `max(adjacent_pair)` — max preserves magnitude
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3. **UE4M3→UE8M0**: `float32 → (bits >> 23) & 0xFF → uint8` (extract IEEE 754 exponent)
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4. **Pack**: 4 uint8 UE8M0 values → 1 int32
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5. **Transpose**: MN-major layout
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6. **TMA-align**: `transform_sf_into_required_layout(sf, mn, k, (1,32), num_experts)`
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**NO UE4M3→UE8M0 conversion. NO block16→block32 merge.** The kernel consumes
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native UE4M3 scales with block16 grouping.
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### C++ Changes
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## Key Differences from MXFP4 mega_moe
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| File | Change |
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|------|--------|
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| `csrc/apis/mega_nvfp4.hpp` | NVFP4 SymmBuffer (SF stride K/32, K/128 packed) |
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| `csrc/apis/layout.hpp` | gran_k=32 support (already existed, just documented) |
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| `csrc/jit_kernels/impls/sm100_fp8_nvfp4_mega_moe.hpp` | JIT kernel header |
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| `csrc/python_api.cpp` | Register NVFP4 APIs |
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| Parameter | MXFP4 | NVFP4 (this kernel) |
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|-----------|-------|---------------------|
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| `kGranK` | 32 | 16 |
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| PTX instruction | `mxf8f6f4.block_scale` | `mxf4nvf4.block_scale.scale_vec::4X` |
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| Scale factor type | `float_ue8m0_t` | `float_ue4m3_t` |
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| SF vector size | block32 / 2X | block16 / 4X |
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| TMEM SF cols (SFA) | `SF_BLOCK_M / 32` | `SF_BLOCK_M / 32 * 4` |
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| UTCCP col stride | `i * 4` | `i * 8` |
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| `kNumSFUint32` | `kHidden / 128` | `kHidden / 64` |
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| L1 epilogue | UE8M0 (`>> 23`) | UE4M3 (float→e4m3 cast) |
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| recipe | `(1, 1, 32)` | `(1, 1, 16)` |
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### PTX Wrappers Added (`tcgen05.cuh`)
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## Critical Implementation Details
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- `SM100_MMA_MXF4NVF4_2x1SM_SS` — for future SM103+ support
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- `SM100_MMA_MXF4NVF4_SS` — single-CTA variant
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### scale_format_ constraint
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The CUTLASS instruction descriptor has a single `scale_format_` bit (0=E4M3, 1=E8M0)
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that applies to BOTH A and B scale factors. For NVFP4 (E4M3), both activation (SFA)
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and weight (SFB) scales must use UE4M3. The L1 epilogue outputs UE4M3 activation scales
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(float → `cutlass::float_e4m3_t` with sign bit cleared).
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**Note**: These are NOT used on SM100. The kernel uses `SM100_MMA_MXF8F6F4_2x1SM_SS` instead.
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### Arch flag
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The JIT compiler MUST target `sm_100a`, not `sm_100`. Without the `a` suffix, the
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`mxf4nvf4` instruction is unavailable and compilation will fail with
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"Feature '.scale_vec::4X' not supported on .target 'sm_100f'".
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## Debugging Log (Builds 1–22)
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### Weight scale_2 folding
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The NVFP4 checkpoint has dual-level scaling: per-block UE4M3 + per-tensor float32.
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The `weight_scale_2` must be folded into the block scales before packing:
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`effective_scale = block_scale * global_scale`, then re-quantize to UE4M3.
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## Build History
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| Build | Error | Fix |
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|-------|-------|-----|
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| 1–6 | Dockerfile/build issues | NVRTC symlink, CPATH, PYTHONPATH |
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| 7 | `kPackedFP4` type mismatch | uint8→int8 view |
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| 9 | SF stride assertion | MN-major layout + TMA alignment |
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| 10 | `transform_sf` no gran_k=16 | C++ fix (later reverted to 32) |
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| 11 | SF dtype float8_e4m3fn rejected | Pack to int32 first |
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| 10 | `transform_sf` no gran_k=16 | C++ fix |
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| 11 | SF dtype float8_e4m3fn rejected | Pack UE4M3→int32 first |
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| 12–14 | SF stride layout | Transpose to MN-major |
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| 15 | SymmBuffer too small | NVFP4-specific SymmBuffer |
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| 15 | SymmBuffer too small | NVFP4-specific SymmBuffer (2× SF) |
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| 16 | `ImportError` | Python wrapper |
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| 17 | NVCC: `scale_vec::4X` not on sm_100f | Hardware limit |
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| 18 | NVCC: `scale_vec::2X` also not on sm_100f | Hardware limit |
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| 19 | kGranK=16 in C++ binding | → 32 |
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| **17** | **NVCC: `scale_vec::4X` not on sm_100f** | **Wrong arch: need `sm_100a`** |
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| 18 | `scale_vec::2X` also failed | Same — `sm_100a` required |
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| 19 | kGranK still 16 in C++ binding | Should stay 16 — was wrongly changed to 32 |
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| 20 | `uint32 >> 23` fails | Cast to int32 first |
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| 22 | Garbled output | UE4M3→UE8M0 precision loss (unfixable on SM100) |
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| 22 | Garbled output | Fell back to mxf8f6f4 — should use mxf4nvf4 on sm_100a |
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## Path Forward
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## Remaining Work
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### For SM103+ (B300/GB300)
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The `SM100_MMA_MXF4NVF4` PTX wrappers are already in the code. On SM103+:
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1. Switch kernel to use `mxf4nvf4.block_scale.scale_vec::4X` (block16)
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2. Keep UE4M3 scales (no conversion to UE8M0)
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3. Update TMEM layout to 4X (i*8 stride, 4 sub-columns)
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4. This should produce correct output with full NVFP4 precision
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### For SM100 (B200)
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The UE4M3→UE8M0 conversion is fundamentally lossy. Options:
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1. **FlashInfer FP4 MoE** — dequant NVFP4→BF16, use BF16 GEMM (avoids scale conversion)
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2. **BF16 mega_moe** — dequant in shared memory, use BF16 MMA
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3. **Accept the precision loss** — only viable if the model is robust to scale quantization
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## Integration with vLLM
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The `mega-moe-nvfp4` branch of `deepseek-v4-quant` wires this kernel into
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`DeepseekV4MegaMoEExperts`:
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- `finalize_weights()`: calls `transform_nvfp4_weights_for_mega_moe()`
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- `forward()`: calls `fp8_nvfp4_mega_moe()` with `recipe=(1,1,32)`
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- `get_symm_buffer()`: uses `get_symm_buffer_for_nvfp4_mega_moe()`
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- [ ] Fix DeepGEMM JIT to target `sm_100a` instead of `sm_100`
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- [ ] Add NVFP4 MMA kind enum to DeepGEMM runtime (not just MXFP8FP4 with NVFP4 hat)
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- [ ] Revert to Build 17's `mxf4nvf4.scale_vec::4X` instruction (was correct, just wrong arch)
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- [ ] Revert `kGranK` to 16, UE4M3 scales, block16 SF layout
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- [ ] Add `get_sf_uttcp_aligned_block_sizes` branch for block16 layout
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- [ ] Remove UE4M3→UE8M0 conversion and block16→block32 merge from Python
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- [ ] Verify TMEM 4X layout (i*8 stride, 4 sub-columns)
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- [ ] End-to-end quality test on B200
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