Kunshang Ji da14ae0fad [XPU][CI]disable lm cache uts (#28696) ...

Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>

2025-11-14 03:15:50 +00:00

..

lm-eval-harness

Disable nm-testing models with issues in CI (#28206)

2025-11-06 06:19:07 -08:00

performance-benchmarks

[CI/Build][Intel] Enable performance benchmarks for Intel Gaudi 3 (#26919)

2025-10-31 07:57:22 +08:00

scripts

[XPU][CI]disable lm cache uts (#28696)

2025-11-14 03:15:50 +00:00

check-wheel-size.py

[CI] Raise VLLM_MAX_SIZE_MB to 500 due to failing Build wheel - CUDA 12.9 (#26722)

2025-10-14 10:52:05 -07:00

generate_index.py

[ci/build] Fix abi tag for aarch64 (#23329)

2025-08-21 23:32:55 +08:00

release-pipeline.yaml

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

test-amd.yaml

Mirrored test group definitions for AMD (2025-11-11) (#28573)

2025-11-14 00:16:34 +00:00

test-pipeline.yaml

[Bugfix] Eliminate tuple inputs to submodules in graph partitioning (#28533)

2025-11-13 15:09:05 -05:00