typer-J 4184653775 feat: add RISC-V support for CPU backend (v2) (#36578) ...

Signed-off-by: typer-J <2236066784@qq.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>

2026-03-10 21:51:39 -07:00

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micro_gemm

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sgl-kernels

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activation.cpp

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cpu_arch_macros.h

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cpu_attn_amx.hpp

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cpu_attn_impl.hpp

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cpu_attn_neon_bfmmla.hpp

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cpu_attn_neon.hpp

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cpu_attn_vec16.hpp

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cpu_attn_vec.hpp

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cpu_attn_vxe.hpp

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cpu_attn.cpp

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cpu_fused_moe.cpp

[Bugfix][CPU] Fix llama4 inference on CPU (#34321)

2026-02-11 19:07:23 +08:00

cpu_types_arm.hpp

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cpu_types_riscv.hpp

feat: add RISC-V support for CPU backend (v2) (#36578)

2026-03-10 21:51:39 -07:00

cpu_types_scalar.hpp

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cpu_types_vsx.hpp

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cpu_types_vxe.hpp

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cpu_types_x86.hpp

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cpu_types.hpp

feat: add RISC-V support for CPU backend (v2) (#36578)

2026-03-10 21:51:39 -07:00

cpu_wna16.cpp

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dnnl_helper.cpp

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dnnl_helper.h

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dnnl_kernels.cpp

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float_convert.hpp

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generate_cpu_attn_dispatch.py

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layernorm.cpp

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mla_decode.cpp

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pos_encoding.cpp

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shm.cpp

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torch_bindings.cpp

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utils.cpp

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utils.hpp

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