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d0d97e2974250edb61fbff6964e95a5b6d22d763
vllm/tests/v1/kv_connector/nixl_integration
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liranschour 8322d4e47f Enable Cross layers KV cache layout at NIXL Connector V2 (#33339)
Signed-off-by: Liran Schour <lirans@il.ibm.com>
Signed-off-by: liranschour <liranschour@users.noreply.github.com>
Co-authored-by: Or Ozeri <or@ozery.com>
Co-authored-by: Nicolò Lucchesi <nicolo.lucchesi@gmail.com>
Co-authored-by: Nicolò Lucchesi <nlucches@redhat.com>
2026-02-05 02:17:02 -08:00
..
config_sweep_accuracy_test.sh
Enable Cross layers KV cache layout at NIXL Connector V2 (#33339)
2026-02-05 02:17:02 -08:00
run_accuracy_test.sh
Enable Cross layers KV cache layout at NIXL Connector V2 (#33339)
2026-02-05 02:17:02 -08:00
run_edge_case_test.sh
[Hybrid allocator + kv connector] revert connector test changes related to hybrid allocator (#28011)
2025-11-05 10:36:31 +00:00
run_tpu_disagg_accuracy_test.sh
[V0 Deprecation] Remove VLLM_USE_V1 from tests (#26341)
2025-10-07 15:42:31 +00:00
run_tpu_edge_case_test.sh
[V0 Deprecation] Remove VLLM_USE_V1 from tests (#26341)
2025-10-07 15:42:31 +00:00
test_accuracy.py
[CI] Nixl integration tests (#27010)
2025-10-17 07:13:31 -07:00
test_disagg_accuracy.py
…
test_edge_cases.py
…
toy_proxy_server.py
[Disagg] Support large batch size in proxy server and update NixlConnector doc for DP (#28782)
2025-12-09 00:01:08 +00:00
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