404 lines
16 KiB
Plaintext
404 lines
16 KiB
Plaintext
#include "common.cuh"
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#include "dispatch_utils.h"
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#include "cub_helpers.h"
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#include "libtorch_stable/quantization/vectorization_utils.cuh"
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#include <c10/cuda/CUDAGuard.h>
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#include <ATen/cuda/Exceptions.h>
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#include <tuple>
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namespace vllm {
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// STRIDE_I_ZERO: true if scale_stride_i == 0 (per-tensor or per-channel)
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// STRIDE_J_ZERO: true if scale_stride_j == 0 (per-tensor or per-token)
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template <typename scalar_t, typename fp8_type, bool STRIDE_I_ZERO,
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bool STRIDE_J_ZERO>
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__global__ void scaled_fp8_quant_kernel_strided_group_shape(
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fp8_type* __restrict__ out, const scalar_t* __restrict__ input,
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const float* __restrict__ scale, int hidden_size, int64_t in_row_stride,
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int64_t out_row_stride, int group_m, int group_n, int64_t scale_stride_i,
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int64_t scale_stride_j) {
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const int64_t token_idx = blockIdx.x;
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const int tid = threadIdx.x;
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const scalar_t* token_in = input + token_idx * in_row_stride;
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fp8_type* token_out = out + token_idx * out_row_stride;
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// Precompute row-level base offset for scale access (compile-time eliminated
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// when STRIDE_I_ZERO)
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const int64_t scale_row_base =
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STRIDE_I_ZERO ? 0
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: static_cast<int>(token_idx) / group_m * scale_stride_i;
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auto get_inv_scale = [&](int gj) {
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return 1.0f / scale[scale_row_base + gj * scale_stride_j];
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};
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int cached_gj = -1;
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float cached_inv_scale = 0.0f;
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auto get_inv_scale_cached = [&](int gj) {
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if (gj != cached_gj) {
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cached_inv_scale = 1.0f / scale[scale_row_base + gj * scale_stride_j];
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cached_gj = gj;
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}
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return cached_inv_scale;
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};
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constexpr int VEC_SIZE = 16; // FP8 so vectorize to 128 bits
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auto scaled_fp8_conversion_vectorized = [&](const scalar_t* in, fp8_type* out,
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int size, float inv_scale) {
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vectorize_with_alignment<VEC_SIZE>(
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in, out, size, tid, blockDim.x,
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[=] __device__(fp8_type & dst, const scalar_t& src) {
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dst = scaled_fp8_conversion<true, fp8_type>(static_cast<float>(src),
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inv_scale);
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});
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};
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if (STRIDE_J_ZERO && hidden_size % VEC_SIZE == 0) {
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// Per-tensor or per-token: single scale per row, vectorize full row
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scaled_fp8_conversion_vectorized(token_in, token_out, hidden_size,
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get_inv_scale(0));
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} else if (group_n % VEC_SIZE == 0) {
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// Multiple column groups with vectorization
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const int num_groups_n = hidden_size / group_n;
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for (int gj = 0; gj < num_groups_n; gj++) {
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scaled_fp8_conversion_vectorized(token_in + gj * group_n,
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token_out + gj * group_n, group_n,
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get_inv_scale(gj));
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}
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} else {
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// Scalar path for small column groups (group_n < VEC_SIZE)
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for (int n = tid; n < hidden_size; n += blockDim.x) {
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const int gj = n / group_n;
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token_out[n] = scaled_fp8_conversion<true, fp8_type>(
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static_cast<float>(token_in[n]), get_inv_scale_cached(gj));
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}
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}
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}
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template <typename scalar_t, typename fp8_type>
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__global__ void segmented_max_reduction_strided(
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float* __restrict__ scale, const scalar_t* __restrict__ input,
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int hidden_size, int64_t in_row_stride, int64_t num_tokens) {
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__shared__ float cache[256];
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const int tid = threadIdx.x;
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int64_t token_idx = blockIdx.x;
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// one block per token. Guard in case gridDim.x > num_tokens.
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if (token_idx >= num_tokens) {
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return;
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}
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const scalar_t* row_ptr = input + token_idx * in_row_stride;
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// each thread scans elements of the row in a strided fashion.
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float thread_max = 0.0f;
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for (int e = tid; e < hidden_size; e += blockDim.x) {
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float v = fabsf(static_cast<float>(row_ptr[e]));
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thread_max = fmaxf(thread_max, v);
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}
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cache[tid] = thread_max;
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__syncthreads();
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// parallel reduction to find row max.
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for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
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if (tid < offset) {
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cache[tid] = fmaxf(cache[tid], cache[tid + offset]);
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}
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__syncthreads();
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}
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// thread 0 updates global scale (per-tensor) atomically.
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if (tid == 0) {
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atomicMaxFloat(scale, cache[0] / quant_type_max_v<fp8_type>);
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}
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}
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template <typename scalar_t, typename fp8_type>
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__global__ void scaled_fp8_quant_kernel_strided_dynamic(
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fp8_type* __restrict__ out, const scalar_t* __restrict__ input,
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const float* __restrict__ scale, int hidden_size, int64_t in_row_stride,
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int64_t out_row_stride) {
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const int64_t token_idx = blockIdx.x;
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const int tid = threadIdx.x;
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const scalar_t* token_in = input + token_idx * in_row_stride;
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fp8_type* token_out = out + token_idx * out_row_stride;
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const float reciprocal_scale = 1.0f / (*scale);
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vectorize_with_alignment<16>(
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token_in, token_out, hidden_size, tid, blockDim.x,
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[=] __device__(fp8_type & dst, const scalar_t& src) {
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dst = scaled_fp8_conversion<true, fp8_type>(static_cast<float>(src),
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reciprocal_scale);
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});
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}
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template <typename scalar_t, typename fp8_type>
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__global__ void dynamic_per_token_scaled_fp8_quant_kernel_strided(
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fp8_type* __restrict__ out, float* __restrict__ scale,
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const scalar_t* __restrict__ input, const float* __restrict__ scale_ub,
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int hidden_size, int64_t in_row_stride, int64_t out_row_stride) {
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const int64_t token_idx = blockIdx.x;
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const int tid = threadIdx.x;
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// Use int64 to avoid overflowing an int32 when calculating this offset
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int64_t in_offset = static_cast<int64_t>(token_idx) * in_row_stride;
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int64_t out_offset = static_cast<int64_t>(token_idx) * out_row_stride;
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const scalar_t* token_in = input + in_offset;
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fp8_type* token_out = out + out_offset;
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// 1) per-token absmax
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float absmax_val = 0.f;
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vectorize_read_with_alignment<16>(
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token_in, hidden_size, tid, blockDim.x, [&] __device__(scalar_t v) {
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absmax_val = fmaxf(absmax_val, fabsf(static_cast<float>(v)));
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});
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using BlockReduce = cub::BlockReduce<float, 256>;
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__shared__ typename BlockReduce::TempStorage tmp;
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const float block_max =
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BlockReduce(tmp).Reduce(absmax_val, CubMaxOp{}, blockDim.x);
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__shared__ float token_scale;
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if (tid == 0) {
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token_scale = scale_ub ? fminf(block_max, *scale_ub) : block_max;
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token_scale = fmaxf(token_scale / quant_type_max_v<fp8_type>,
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min_scaling_factor<fp8_type>::val());
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scale[token_idx] = token_scale;
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}
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__syncthreads();
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// 2) quantize
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vectorize_with_alignment<16>(
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token_in, token_out, hidden_size, tid, blockDim.x,
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[=] __device__(fp8_type & dst, const scalar_t& src) {
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dst = scaled_fp8_conversion<false, fp8_type>(static_cast<float>(src),
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token_scale);
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});
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}
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} // namespace vllm
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void static_scaled_fp8_quant(
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torch::Tensor& out, // [..., d]
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torch::Tensor const& input, // [..., d]
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torch::Tensor const& scale, // various shapes
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std::optional<std::tuple<int64_t, int64_t>>
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opt_group_shape) // optional explicit (group_m, group_n)
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{
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TORCH_CHECK(input.stride(-1) == 1,
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"last dimension of input must be contiguous");
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TORCH_CHECK(out.stride(-1) == 1,
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"last dimension of output must be contiguous");
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const int hidden_size = input.size(-1); // N (columns)
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const int num_tokens = input.numel() / hidden_size; // M (rows)
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// Determine group_m, group_n, and scale strides from scale shape
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// Scale indexing: scale[gi * scale_stride_j + gj * scale_stride_i]
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// where gi = m / group_m, gj = n / group_n
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int group_m, group_n;
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int64_t scale_stride_i, scale_stride_j;
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if (scale.dim() == 0 || scale.numel() == 1) {
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// Per-tensor: one scale for the entire tensor
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group_m = num_tokens;
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group_n = hidden_size;
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scale_stride_i = 0;
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scale_stride_j = 0;
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} else if (scale.dim() == 1) {
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// 1D scale: require explicit group_shape to disambiguate per-channel vs
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// per-token (avoids edge case where num_tokens == hidden_size)
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TORCH_CHECK(opt_group_shape.has_value(),
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"1D scale requires explicit group_shape to disambiguate "
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"per-channel vs per-token quantization. "
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"Use group_shape=(-1, 1) for per-channel or group_shape=(1, "
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"-1) for per-token.");
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const auto& [opt_group_m, opt_group_n] = opt_group_shape.value();
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group_m = opt_group_m == -1 ? num_tokens : static_cast<int>(opt_group_m);
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group_n = opt_group_n == -1 ? hidden_size : static_cast<int>(opt_group_n);
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// Validate the explicit group shape matches the 1D scale
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const int64_t scale_len = scale.numel();
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const int64_t expected_scale_m = num_tokens / group_m;
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const int64_t expected_scale_n = hidden_size / group_n;
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const int64_t expected_scale_numel = expected_scale_m * expected_scale_n;
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TORCH_CHECK(scale_len == expected_scale_numel, "1D scale length (",
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scale_len, ") does not match expected size (",
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expected_scale_numel, ") for group_shape (", opt_group_m, ", ",
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opt_group_n, ") with input shape (", num_tokens, ", ",
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hidden_size, ")");
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// For 1D scale, determine strides based on which dim is trivial
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// Scale indexing: scale[gi * scale_stride_i + gj * scale_stride_j]
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// where gi = m / group_m (row group), gj = n / group_n (col group)
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if (expected_scale_m == 1) {
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// Per-channel style: one scale in M dim, scale varies along N
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// gi = 0 always, gj varies, so stride_1 traverses the scale
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scale_stride_i = 0;
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scale_stride_j = scale.stride(0);
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} else if (expected_scale_n == 1) {
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// Per-token style: one scale in N dim, scale varies along M
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// gj = 0 always, gi varies, so stride_0 traverses the scale
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scale_stride_i = scale.stride(0);
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scale_stride_j = 0;
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} else {
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TORCH_CHECK(
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false,
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"1D scale can only be used when one of the scale dimensions is 1. "
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"For 2D group scaling, use a 2D scale tensor.");
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}
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} else if (scale.dim() == 2) {
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// 2D scale: infer group sizes from scale dimensions (or use explicit if
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// provided)
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const int64_t scale_size_0 = scale.size(0);
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const int64_t scale_size_1 = scale.size(1);
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TORCH_CHECK(num_tokens % scale_size_0 == 0, "num_tokens (", num_tokens,
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") must be divisible by scale.size(0) (", scale_size_0, ")");
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TORCH_CHECK(hidden_size % scale_size_1 == 0, "hidden_size (", hidden_size,
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") must be divisible by scale.size(1) (", scale_size_1, ")");
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// Infer from 2D scale shape
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int inferred_group_m = num_tokens / scale_size_0;
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int inferred_group_n = hidden_size / scale_size_1;
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// Use explicit if provided, otherwise use inferred
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if (opt_group_shape.has_value()) {
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const auto& [opt_group_m, opt_group_n] = opt_group_shape.value();
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group_m = opt_group_m == -1 ? num_tokens : static_cast<int>(opt_group_m);
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group_n = opt_group_n == -1 ? hidden_size : static_cast<int>(opt_group_n);
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// Validate explicit matches inferred
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TORCH_CHECK(group_m == inferred_group_m && group_n == inferred_group_n,
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"Explicit group_shape (", opt_group_m, ", ", opt_group_n,
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") does not match inferred group shape (", inferred_group_m,
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", ", inferred_group_n, ") from 2D scale tensor shape (",
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scale_size_0, ", ", scale_size_1, ")");
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} else {
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group_m = inferred_group_m;
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group_n = inferred_group_n;
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}
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scale_stride_i = scale.stride(0);
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scale_stride_j = scale.stride(1);
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} else {
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TORCH_CHECK(false, "scale must be 0D, 1D, or 2D tensor, but got ",
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scale.dim(), "D");
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}
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const int block_size = 256;
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dim3 grid(num_tokens);
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dim3 block(block_size);
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const int64_t in_row_stride = input.stride(-2);
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const int64_t out_row_stride = out.stride(-2);
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const at::cuda::OptionalCUDAGuard device_guard(device_of(input));
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const cudaStream_t stream = at::cuda::getCurrentCUDAStream();
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// Dispatch to template-specialized kernel based on stride pattern
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VLLM_DISPATCH_FLOATING_TYPES(
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input.scalar_type(), "scaled_fp8_quant_kernel_scalar_type", [&] {
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VLLM_DISPATCH_FP8_TYPES(
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out.scalar_type(), "scaled_fp8_quant_kernel_fp8_type", [&] {
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VLLM_DISPATCH_BOOL(scale_stride_i == 0, S0_ZERO, [&] {
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VLLM_DISPATCH_BOOL(scale_stride_j == 0, S1_ZERO, [&] {
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vllm::scaled_fp8_quant_kernel_strided_group_shape<
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scalar_t, fp8_t, S0_ZERO, S1_ZERO>
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<<<grid, block, 0, stream>>>(
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out.data_ptr<fp8_t>(), input.data_ptr<scalar_t>(),
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scale.data_ptr<float>(), hidden_size, in_row_stride,
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out_row_stride, group_m, group_n, scale_stride_i,
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scale_stride_j);
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});
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});
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});
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});
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}
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void dynamic_scaled_fp8_quant(torch::Tensor& out, // [..., d]
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torch::Tensor const& input, // [..., d]
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torch::Tensor& scale) // [1]
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{
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TORCH_CHECK(input.stride(-1) == 1,
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"last dimension of input must be contiguous");
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TORCH_CHECK(out.stride(-1) == 1,
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"last dimension of output must be contiguous");
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const int hidden_size = input.size(-1);
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const int num_tokens = input.numel() / hidden_size;
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const int block_size = 256;
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dim3 grid(num_tokens);
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dim3 block(block_size);
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const int64_t in_row_stride = input.stride(-2);
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const int64_t out_row_stride = out.stride(-2);
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const at::cuda::OptionalCUDAGuard device_guard(device_of(input));
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const cudaStream_t stream = at::cuda::getCurrentCUDAStream();
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// scale tensor should be initialised to <=0 before reduction
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AT_CUDA_CHECK(
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cudaMemsetAsync(scale.data_ptr<float>(), 0, sizeof(float), stream));
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VLLM_DISPATCH_FLOATING_TYPES(
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input.scalar_type(), "scaled_fp8_quant_kernel_scalar_type", [&] {
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VLLM_DISPATCH_FP8_TYPES(
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out.scalar_type(), "scaled_fp8_quant_kernel_fp8_type", [&] {
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vllm::segmented_max_reduction_strided<scalar_t, fp8_t>
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<<<grid, block, 0, stream>>>(
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scale.data_ptr<float>(), input.data_ptr<scalar_t>(),
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hidden_size, in_row_stride,
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static_cast<int64_t>(num_tokens));
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vllm::scaled_fp8_quant_kernel_strided_dynamic<scalar_t, fp8_t>
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<<<grid, block, 0, stream>>>(
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out.data_ptr<fp8_t>(), input.data_ptr<scalar_t>(),
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scale.data_ptr<float>(), hidden_size, in_row_stride,
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out_row_stride);
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});
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});
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}
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void dynamic_per_token_scaled_fp8_quant(
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torch::Tensor& out, // [..., d]
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torch::Tensor const& input, // [..., d]
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torch::Tensor& scales, std::optional<at::Tensor> const& scale_ub) {
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TORCH_CHECK(input.stride(-1) == 1,
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"last dimension of input must be contiguous");
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TORCH_CHECK(out.stride(-1) == 1,
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"last dimension of output must be contiguous");
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const int hidden_size = input.size(-1);
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const int num_tokens = input.numel() / hidden_size;
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const int block_size = 256;
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dim3 grid(num_tokens);
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dim3 block(std::min(hidden_size, block_size));
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const int64_t in_row_stride = input.stride(-2);
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const int64_t out_row_stride = out.stride(-2);
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const at::cuda::OptionalCUDAGuard device_guard(device_of(input));
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const cudaStream_t stream = at::cuda::getCurrentCUDAStream();
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VLLM_DISPATCH_FLOATING_TYPES(
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input.scalar_type(),
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"dynamic_per_token_scaled_fp8_quant_kernel_scalar_type", [&] {
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VLLM_DISPATCH_FP8_TYPES(
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out.scalar_type(),
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"dynamic_per_token_scaled_fp8_quant_kernel_fp8_type", [&] {
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vllm::dynamic_per_token_scaled_fp8_quant_kernel_strided<
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scalar_t, fp8_t><<<grid, block, 0, stream>>>(
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out.data_ptr<fp8_t>(), scales.data_ptr<float>(),
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input.data_ptr<scalar_t>(),
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scale_ub.has_value() ? scale_ub->data_ptr<float>() : nullptr,
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hidden_size, in_row_stride, out_row_stride);
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});
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});
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}
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