b4a2f3ac36
Signed-off-by: johnnynunez <johnnynuca14@gmail.com> Signed-off-by: Johnny <johnnynuca14@gmail.com>
164 lines
6.7 KiB
Plaintext
164 lines
6.7 KiB
Plaintext
/*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <torch/all.h>
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#include "cutlass_extensions/common.hpp"
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#include "nvfp4_utils.cuh"
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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void scaled_fp4_quant_sm1xxa(torch::Tensor const& output,
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torch::Tensor const& input,
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torch::Tensor const& output_sf,
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torch::Tensor const& input_sf,
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bool is_sf_swizzled_layout);
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#endif
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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void scaled_fp4_experts_quant_sm1xxa(
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torch::Tensor& output, torch::Tensor& output_scale,
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torch::Tensor const& input, torch::Tensor const& input_global_scale,
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torch::Tensor const& input_offset_by_experts,
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torch::Tensor const& output_scale_offset_by_experts);
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#endif
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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void silu_and_mul_nvfp4_quant_sm1xxa(torch::Tensor& output,
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torch::Tensor& output_sf,
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torch::Tensor& input,
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torch::Tensor& input_sf);
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#endif
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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void silu_and_mul_scaled_fp4_experts_quant_sm1xxa(
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torch::Tensor& output, torch::Tensor& output_scale,
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torch::Tensor const& input, torch::Tensor const& input_global_scale,
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torch::Tensor const& input_offset_by_experts,
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torch::Tensor const& output_scale_offset_by_experts);
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#endif
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static bool nvfp4_quant_sm_supported() {
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const int32_t sm = get_sm_version_num();
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#if defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100
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if (sm >= 100 && sm < 120) return true;
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#endif
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#if defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120
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if (sm >= 120 && sm < 130) return true;
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#endif
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return false;
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}
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void scaled_fp4_quant_out(torch::Tensor const& input,
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torch::Tensor const& input_sf,
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bool is_sf_swizzled_layout, torch::Tensor& output,
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torch::Tensor& output_sf) {
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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TORCH_CHECK(nvfp4_quant_sm_supported(),
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"No compiled nvfp4 quantization kernel for SM ",
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get_sm_version_num(),
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". Recompile with the appropriate CUDA arch.");
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return scaled_fp4_quant_sm1xxa(output, input, output_sf, input_sf,
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is_sf_swizzled_layout);
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#endif
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TORCH_CHECK_NOT_IMPLEMENTED(false, "No compiled nvfp4 quantization kernel");
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}
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std::tuple<torch::Tensor, torch::Tensor> scaled_fp4_quant_func(
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torch::Tensor const& input, torch::Tensor const& input_sf,
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bool is_sf_swizzled_layout) {
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int64_t n = input.size(-1);
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int64_t m = input.numel() / n;
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auto device = input.device();
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// Two fp4 values packed into a uint8
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auto output = torch::empty(
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{m, n / 2}, torch::TensorOptions().device(device).dtype(torch::kUInt8));
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torch::Tensor output_sf;
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if (is_sf_swizzled_layout) {
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auto [sf_m, sf_n] = vllm::computeSwizzledSFShape(m, n);
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output_sf = torch::empty(
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{sf_m, sf_n},
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torch::TensorOptions().device(device).dtype(torch::kInt32));
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} else {
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output_sf = torch::empty(
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{m, n / CVT_FP4_SF_VEC_SIZE},
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torch::TensorOptions().device(device).dtype(torch::kUInt8));
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}
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scaled_fp4_quant_out(input, input_sf, is_sf_swizzled_layout, output,
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output_sf);
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return {output, output_sf};
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}
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void scaled_fp4_experts_quant(
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torch::Tensor& output, torch::Tensor& output_scale,
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torch::Tensor const& input, torch::Tensor const& input_global_scale,
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torch::Tensor const& input_offset_by_experts,
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torch::Tensor const& output_scale_offset_by_experts) {
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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TORCH_CHECK(nvfp4_quant_sm_supported(),
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"No compiled nvfp4 experts quantization kernel for SM ",
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get_sm_version_num(),
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". Recompile with the appropriate CUDA arch.");
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return scaled_fp4_experts_quant_sm1xxa(
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output, output_scale, input, input_global_scale, input_offset_by_experts,
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output_scale_offset_by_experts);
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#endif
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TORCH_CHECK_NOT_IMPLEMENTED(false,
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"No compiled nvfp4 experts quantization kernel");
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}
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void silu_and_mul_nvfp4_quant(torch::Tensor& output, torch::Tensor& output_sf,
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torch::Tensor& input, torch::Tensor& input_sf) {
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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TORCH_CHECK(nvfp4_quant_sm_supported(),
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"No compiled silu_and_mul nvfp4 quantization kernel for SM ",
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get_sm_version_num(),
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". Recompile with the appropriate CUDA arch.");
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return silu_and_mul_nvfp4_quant_sm1xxa(output, output_sf, input, input_sf);
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#endif
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TORCH_CHECK_NOT_IMPLEMENTED(
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false, "No compiled silu_and_mul nvfp4 quantization kernel");
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}
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void silu_and_mul_scaled_fp4_experts_quant(
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torch::Tensor& output, torch::Tensor& output_scale,
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torch::Tensor const& input, torch::Tensor const& input_global_scale,
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torch::Tensor const& input_offset_by_experts,
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torch::Tensor const& output_scale_offset_by_experts) {
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#if (defined(ENABLE_NVFP4_SM100) && ENABLE_NVFP4_SM100) || \
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(defined(ENABLE_NVFP4_SM120) && ENABLE_NVFP4_SM120)
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TORCH_CHECK(nvfp4_quant_sm_supported(),
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"No compiled silu_and_mul nvfp4 experts quantization kernel "
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"for SM ",
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get_sm_version_num(),
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". Recompile with the appropriate CUDA arch.");
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return silu_and_mul_scaled_fp4_experts_quant_sm1xxa(
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output, output_scale, input, input_global_scale, input_offset_by_experts,
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output_scale_offset_by_experts);
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#endif
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TORCH_CHECK_NOT_IMPLEMENTED(
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false, "No compiled silu_and_mul nvfp4 experts quantization kernel");
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}
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